Index: lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
===================================================================
--- lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+++ lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
@@ -152,8 +152,10 @@
   for (MachineInstr *InstToMove : InstsToMove) {
     if (!InstToMove->mayLoadOrStore())
       continue;
-    if (!TII->areMemAccessesTriviallyDisjoint(MemOp, *InstToMove, AA))
-      return false;
+    if (!TII->areMemAccessesTriviallyDisjoint(MemOp, *InstToMove, AA)) {
+      if (MemOp.mayStore() || InstToMove->mayStore())
+        return false;
+    }
   }
   return true;
 }
@@ -212,12 +214,19 @@
         return E;
 
       if (MBBI->mayLoadOrStore() &&
-          !TII->areMemAccessesTriviallyDisjoint(*I, *MBBI, AA)) {
-        // We fail condition #1, but we may still be able to satisfy condition
-        // #2.  Add this instruction to the move list and then we will check
-        // if condition #2 holds once we have selected the matching instruction.
-        InstsToMove.push_back(&*MBBI);
-        addDefsToList(*MBBI, DefsToMove);
+        !TII->areMemAccessesTriviallyDisjoint(*I, *MBBI, AA)) {
+        /*
+           RAW or WAR - cannot reorder
+           WAW - cannot reorder
+           RAR - safe to reorder
+        */
+        if (MBBI->mayStore() || I->mayStore()) {
+          // We fail condition #1, but we may still be able to satisfy condition
+          // #2.  Add this instruction to the move list and then we will check
+          // if condition #2 holds once we have selected the matching instruction.
+          InstsToMove.push_back(&*MBBI);
+          addDefsToList(*MBBI, DefsToMove);
+        }
         continue;
       }
 
@@ -269,7 +278,9 @@
     // it was safe to move I and also all the instruction in InstsToMove
     // down past this instruction.
     // FIXME: This is too conservative.
-    break;
+    if (!TII->areMemAccessesTriviallyDisjoint(*I, *MBBI, AA) &&
+     (I->mayStore() || MBBI->mayStore()))
+      break;
   }
   return E;
 }
Index: test/CodeGen/AMDGPU/cgemm_loopunroll_ds_combine.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/cgemm_loopunroll_ds_combine.ll
@@ -0,0 +1,533 @@
+; RUN: llc -O2 -mtriple amdgcn--amdhsa -mcpu=fiji -filetype=asm < %s | FileCheck -check-prefix=SI %s
+; SI-LABEL: _ZZ26cgemm_NoTransAB_loopunrollRN2
+; SI-NOT: ds_read_b32
+
+; ModuleID = 'fiji.opt.bc'
+source_filename = "llvm-link"
+target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
+target triple = "amdgcn--amdhsa"
+
+; Function Attrs: nounwind
+declare void @llvm.amdgcn.s.waitcnt(i32) #2
+
+; Function Attrs: nounwind
+declare void @llvm.amdgcn.s.dcache.wb() #2
+
+; Function Attrs: convergent nounwind
+declare void @llvm.amdgcn.s.barrier() #3
+
+; Function Attrs: nounwind readnone
+declare float @llvm.fabs.f32(float) #4
+
+; Function Attrs: nounwind readnone
+declare i1 @llvm.amdgcn.class.f32(float, i32) #4
+
+; Function Attrs: nounwind readnone
+declare i1 @llvm.amdgcn.class.f64(double, i32) #4
+
+; Function Attrs: nounwind readnone
+declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #4
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.amdgcn.workitem.id.x() #4
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.amdgcn.workgroup.id.x() #4
+
+; Function Attrs: nounwind readnone
+declare i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() #4
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.amdgcn.workitem.id.y() #4
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.amdgcn.workgroup.id.y() #4
+
+; Function Attrs: nounwind readnone
+declare i32 @llvm.amdgcn.workgroup.id.z() #4
+
+%"class.hc::short_vector::float_2.0" = type { float, float }
+
+@"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Bsreal.2" = internal unnamed_addr addrspace(3) global [16 x [16 x float]] undef, align 4
+
+@"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Bsimg.3" = internal unnamed_addr addrspace(3) global [16 x [16 x float]] undef, align 4
+
+@"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Asreal.4" = internal unnamed_addr addrspace(3) global [16 x [16 x float]] undef, align 4
+
+@"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Asimg.5" = internal unnamed_addr addrspace(3) global [16 x [16 x float]] undef, align 4
+
+define amdgpu_kernel void @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff"(i32, i32, %"class.hc::short_vector::float_2.0" addrspace(1)* nocapture readonly, i64, i32, i32, %"class.hc::short_vector::float_2.0" addrspace(1)* nocapture readonly, i64, i32, %"class.hc::short_vector::float_2.0" addrspace(1)* nocapture, i64, i32, float, float, float, float) local_unnamed_addr #0 align 2 {
+  %17 = tail call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #4
+  %18 = tail call i32 @llvm.amdgcn.workitem.id.y() #4
+  %19 = tail call i32 @llvm.amdgcn.workgroup.id.y() #4
+  %20 = getelementptr inbounds i8, i8 addrspace(2)* %17, i64 6
+  %21 = bitcast i8 addrspace(2)* %20 to i16 addrspace(2)*
+  %22 = load i16, i16 addrspace(2)* %21, align 2, !tbaa !232
+  %23 = zext i16 %22 to i32
+  %24 = mul i32 %23, %19
+  %25 = add i32 %24, %18
+  %26 = tail call i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() #4
+  %27 = getelementptr inbounds i8, i8 addrspace(2)* %26, i64 8
+  %28 = zext i32 %25 to i64
+  %29 = bitcast i8 addrspace(2)* %27 to i64 addrspace(2)*
+  %30 = load i64, i64 addrspace(2)* %29, align 8, !tbaa !241
+  %31 = add i64 %28, %30
+  %32 = tail call i32 @llvm.amdgcn.workitem.id.x() #4
+  %33 = tail call i32 @llvm.amdgcn.workgroup.id.x() #4
+  %34 = getelementptr inbounds i8, i8 addrspace(2)* %17, i64 4
+  %35 = bitcast i8 addrspace(2)* %34 to i16 addrspace(2)*
+  %36 = load i16, i16 addrspace(2)* %35, align 4, !tbaa !242
+  %37 = zext i16 %36 to i32
+  %38 = mul i32 %37, %33
+  %39 = add i32 %38, %32
+  %40 = zext i32 %39 to i64
+  %41 = bitcast i8 addrspace(2)* %26 to i64 addrspace(2)*
+  %42 = load i64, i64 addrspace(2)* %41, align 8, !tbaa !241
+  %conv.i.i.i = trunc i64 %31 to i32
+  %mul.i = shl nsw i32 %19, 4
+  %add.i = add nsw i32 %mul.i, %18
+  %mul5.i = shl nsw i32 %33, 4
+  %add8.i = add nsw i32 %mul5.i, %32
+  %cmp1281.i = icmp sgt i32 %0, 0
+  br i1 %cmp1281.i, label %.lr.ph.i, label %._crit_edge.i
+
+.lr.ph.i:                                         ; preds = %16
+  %conv781288.i = zext i32 %add8.i to i64
+  %cmp15.i = icmp slt i32 %add.i, %1
+  %mul16.i = mul nsw i32 %add.i, %4
+  %conv1115.i = zext i32 %mul16.i to i64
+  %add17.i = add i64 %conv1115.i, %3
+  %43 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Bsreal.2", i32 0, i32 %18, i32 %32
+  %44 = bitcast float addrspace(3)* %43 to i32 addrspace(3)*
+  %45 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Bsimg.3", i32 0, i32 %18, i32 %32
+  %cmp70.i = icmp slt i32 %add8.i, %5
+  %add77.i = add i64 %conv781288.i, %7
+  %46 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Asreal.4", i32 0, i32 %18, i32 %32
+  %47 = bitcast float addrspace(3)* %46 to i32 addrspace(3)*
+  %48 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Asimg.5", i32 0, i32 %18, i32 %32
+  %49 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Bsreal.2", i32 0, i32 %18, i32 0
+  %50 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Asreal.4", i32 0, i32 0, i32 %32
+  %51 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Bsimg.3", i32 0, i32 %18, i32 0
+  %52 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Asimg.5", i32 0, i32 0, i32 %32
+  %53 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Bsreal.2", i32 0, i32 %18, i32 1
+  %54 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Asreal.4", i32 0, i32 1, i32 %32
+  %55 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Bsimg.3", i32 0, i32 %18, i32 1
+  %56 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Asimg.5", i32 0, i32 1, i32 %32
+  %57 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Bsreal.2", i32 0, i32 %18, i32 2
+  %58 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Asreal.4", i32 0, i32 2, i32 %32
+  %59 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Bsimg.3", i32 0, i32 %18, i32 2
+  %60 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Asimg.5", i32 0, i32 2, i32 %32
+  %61 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Bsreal.2", i32 0, i32 %18, i32 3
+  %62 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Asreal.4", i32 0, i32 3, i32 %32
+  %63 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Bsimg.3", i32 0, i32 %18, i32 3
+  %64 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Asimg.5", i32 0, i32 3, i32 %32
+  %65 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Bsreal.2", i32 0, i32 %18, i32 4
+  %66 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Asreal.4", i32 0, i32 4, i32 %32
+  %67 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Bsimg.3", i32 0, i32 %18, i32 4
+  %68 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Asimg.5", i32 0, i32 4, i32 %32
+  %69 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Bsreal.2", i32 0, i32 %18, i32 5
+  %70 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Asreal.4", i32 0, i32 5, i32 %32
+  %71 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Bsimg.3", i32 0, i32 %18, i32 5
+  %72 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Asimg.5", i32 0, i32 5, i32 %32
+  %73 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Bsreal.2", i32 0, i32 %18, i32 6
+  %74 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Asreal.4", i32 0, i32 6, i32 %32
+  %75 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Bsimg.3", i32 0, i32 %18, i32 6
+  %76 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Asimg.5", i32 0, i32 6, i32 %32
+  %77 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Bsreal.2", i32 0, i32 %18, i32 7
+  %78 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Asreal.4", i32 0, i32 7, i32 %32
+  %79 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Bsimg.3", i32 0, i32 %18, i32 7
+  %80 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Asimg.5", i32 0, i32 7, i32 %32
+  %81 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Bsreal.2", i32 0, i32 %18, i32 8
+  %82 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Asreal.4", i32 0, i32 8, i32 %32
+  %83 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Bsimg.3", i32 0, i32 %18, i32 8
+  %84 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Asimg.5", i32 0, i32 8, i32 %32
+  %85 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Bsreal.2", i32 0, i32 %18, i32 9
+  %86 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Asreal.4", i32 0, i32 9, i32 %32
+  %87 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Bsimg.3", i32 0, i32 %18, i32 9
+  %88 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Asimg.5", i32 0, i32 9, i32 %32
+  %89 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Bsreal.2", i32 0, i32 %18, i32 10
+  %90 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Asreal.4", i32 0, i32 10, i32 %32
+  %91 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Bsimg.3", i32 0, i32 %18, i32 10
+  %92 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Asimg.5", i32 0, i32 10, i32 %32
+  %93 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Bsreal.2", i32 0, i32 %18, i32 11
+  %94 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Asreal.4", i32 0, i32 11, i32 %32
+  %95 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Bsimg.3", i32 0, i32 %18, i32 11
+  %96 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Asimg.5", i32 0, i32 11, i32 %32
+  %97 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Bsreal.2", i32 0, i32 %18, i32 12
+  %98 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Asreal.4", i32 0, i32 12, i32 %32
+  %99 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Bsimg.3", i32 0, i32 %18, i32 12
+  %100 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Asimg.5", i32 0, i32 12, i32 %32
+  %101 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Bsreal.2", i32 0, i32 %18, i32 13
+  %102 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Asreal.4", i32 0, i32 13, i32 %32
+  %103 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Bsimg.3", i32 0, i32 %18, i32 13
+  %104 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Asimg.5", i32 0, i32 13, i32 %32
+  %105 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Bsreal.2", i32 0, i32 %18, i32 14
+  %106 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Asreal.4", i32 0, i32 14, i32 %32
+  %107 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Bsimg.3", i32 0, i32 %18, i32 14
+  %108 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Asimg.5", i32 0, i32 14, i32 %32
+  %109 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Bsreal.2", i32 0, i32 %18, i32 15
+  %110 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE6Asreal.4", i32 0, i32 15, i32 %32
+  %111 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Bsimg.3", i32 0, i32 %18, i32 15
+  %112 = getelementptr [16 x [16 x float]], [16 x [16 x float]] addrspace(3)* @"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_EN3$_019__cxxamp_trampolineEiiS4_liiS4_liS4_liffff._ZZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEEE5Asimg.5", i32 0, i32 15, i32 %32
+  %add9.i = add nuw nsw i32 %0, 15
+  %div.i = sdiv i32 %add9.i, 16
+  br label %._crit_edge1286.i
+
+._crit_edge.i.loopexit:                           ; preds = %130
+  br label %._crit_edge.i
+
+._crit_edge.i:                                    ; preds = %._crit_edge.i.loopexit, %16
+  %CValue1.0.lcssa.i = phi float [ 0.000000e+00, %16 ], [ %add827.i, %._crit_edge.i.loopexit ]
+  %CValue.0.lcssa.i = phi float [ 0.000000e+00, %16 ], [ %add475.i, %._crit_edge.i.loopexit ]
+  %cmp829.i = icmp slt i32 %add.i, %1
+  %cmp830.i = icmp slt i32 %add8.i, %5
+  %or.cond34 = and i1 %cmp829.i, %cmp830.i
+  br i1 %or.cond34, label %195, label %"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEE.exit"
+
+._crit_edge1286.i:                                ; preds = %130, %.lr.ph.i
+  %k.01284.i = phi i32 [ 0, %.lr.ph.i ], [ %inc.i, %130 ]
+  %CValue.01283.i = phi float [ 0.000000e+00, %.lr.ph.i ], [ %add475.i, %130 ]
+  %CValue1.01282.i = phi float [ 0.000000e+00, %.lr.ph.i ], [ %add827.i, %130 ]
+  %mul10.i = shl nsw i32 %k.01284.i, 4
+  %add13.i = add nsw i32 %mul10.i, %32
+  %cmp14.i = icmp slt i32 %add13.i, %0
+  %or.cond = and i1 %cmp15.i, %cmp14.i
+  br i1 %or.cond, label %113, label %120
+
+; <label>:113:                                    ; preds = %._crit_edge1286.i
+  %conv221116.i = zext i32 %add13.i to i64
+  %add23.i = add i64 %add17.i, %conv221116.i
+  %sext4 = shl i64 %add23.i, 32
+  %114 = ashr exact i64 %sext4, 32
+  %115 = getelementptr %"class.hc::short_vector::float_2.0", %"class.hc::short_vector::float_2.0" addrspace(1)* %2, i64 %114, i32 0
+  %116 = bitcast float addrspace(1)* %115 to i32 addrspace(1)*
+  %117 = load i32, i32 addrspace(1)* %116, align 4, !tbaa !243
+  store i32 %117, i32 addrspace(3)* %44, align 4, !tbaa !248
+  %118 = getelementptr %"class.hc::short_vector::float_2.0", %"class.hc::short_vector::float_2.0" addrspace(1)* %2, i64 %114, i32 1
+  %119 = load float, float addrspace(1)* %118, align 4, !tbaa !249
+  br label %121
+
+; <label>:120:                                    ; preds = %._crit_edge1286.i
+  store float 0.000000e+00, float addrspace(3)* %43, align 4, !tbaa !248
+  br label %121
+
+; <label>:121:                                    ; preds = %120, %113
+  %.sink.i = phi float [ 0.000000e+00, %120 ], [ %119, %113 ]
+  store float %.sink.i, float addrspace(3)* %45, align 4, !tbaa !248
+  %add68.i = add nsw i32 %mul10.i, %18
+  %cmp69.i = icmp slt i32 %add68.i, %0
+  %or.cond33 = and i1 %cmp70.i, %cmp69.i
+  br i1 %or.cond33, label %122, label %129
+
+; <label>:122:                                    ; preds = %121
+  %mul75.i = mul nsw i32 %add68.i, %8
+  %conv761113.i = zext i32 %mul75.i to i64
+  %add79.i = add i64 %add77.i, %conv761113.i
+  %sext2 = shl i64 %add79.i, 32
+  %123 = ashr exact i64 %sext2, 32
+  %124 = getelementptr %"class.hc::short_vector::float_2.0", %"class.hc::short_vector::float_2.0" addrspace(1)* %6, i64 %123, i32 0
+  %125 = bitcast float addrspace(1)* %124 to i32 addrspace(1)*
+  %126 = load i32, i32 addrspace(1)* %125, align 4, !tbaa !243
+  store i32 %126, i32 addrspace(3)* %47, align 4, !tbaa !248
+  %127 = getelementptr %"class.hc::short_vector::float_2.0", %"class.hc::short_vector::float_2.0" addrspace(1)* %6, i64 %123, i32 1
+  %128 = load float, float addrspace(1)* %127, align 4, !tbaa !249
+  br label %130
+
+; <label>:129:                                    ; preds = %121
+  store float 0.000000e+00, float addrspace(3)* %46, align 4, !tbaa !248
+  br label %130
+
+; <label>:130:                                    ; preds = %129, %122
+  %.sink905.i = phi float [ 0.000000e+00, %129 ], [ %128, %122 ]
+  store float %.sink905.i, float addrspace(3)* %48, align 4, !tbaa !248
+  tail call void @llvm.amdgcn.s.waitcnt(i32 0) #2
+  tail call void @llvm.amdgcn.s.dcache.wb() #2
+  tail call void @llvm.amdgcn.s.barrier() #2
+  %131 = load float, float addrspace(3)* %49, align 4, !tbaa !248
+  %132 = load float, float addrspace(3)* %50, align 4, !tbaa !248
+  %mul134.i = fmul float %131, %132
+  %133 = load float, float addrspace(3)* %51, align 4, !tbaa !248
+  %134 = load float, float addrspace(3)* %52, align 4, !tbaa !248
+  %mul144.i = fmul float %133, %134
+  %sub.i = fsub float %mul134.i, %mul144.i
+  %135 = load float, float addrspace(3)* %53, align 4, !tbaa !248
+  %136 = load float, float addrspace(3)* %54, align 4, !tbaa !248
+  %mul154.i = fmul float %135, %136
+  %add155.i = fadd float %sub.i, %mul154.i
+  %137 = load float, float addrspace(3)* %55, align 4, !tbaa !248
+  %138 = load float, float addrspace(3)* %56, align 4, !tbaa !248
+  %mul165.i = fmul float %137, %138
+  %sub166.i = fsub float %add155.i, %mul165.i
+  %139 = load float, float addrspace(3)* %57, align 4, !tbaa !248
+  %140 = load float, float addrspace(3)* %58, align 4, !tbaa !248
+  %mul176.i = fmul float %139, %140
+  %add177.i = fadd float %sub166.i, %mul176.i
+  %141 = load float, float addrspace(3)* %59, align 4, !tbaa !248
+  %142 = load float, float addrspace(3)* %60, align 4, !tbaa !248
+  %mul187.i = fmul float %141, %142
+  %sub188.i = fsub float %add177.i, %mul187.i
+  %143 = load float, float addrspace(3)* %61, align 4, !tbaa !248
+  %144 = load float, float addrspace(3)* %62, align 4, !tbaa !248
+  %mul198.i = fmul float %143, %144
+  %add199.i = fadd float %sub188.i, %mul198.i
+  %145 = load float, float addrspace(3)* %63, align 4, !tbaa !248
+  %146 = load float, float addrspace(3)* %64, align 4, !tbaa !248
+  %mul209.i = fmul float %145, %146
+  %sub210.i = fsub float %add199.i, %mul209.i
+  %147 = load float, float addrspace(3)* %65, align 4, !tbaa !248
+  %148 = load float, float addrspace(3)* %66, align 4, !tbaa !248
+  %mul220.i = fmul float %147, %148
+  %add221.i = fadd float %sub210.i, %mul220.i
+  %149 = load float, float addrspace(3)* %67, align 4, !tbaa !248
+  %150 = load float, float addrspace(3)* %68, align 4, !tbaa !248
+  %mul231.i = fmul float %149, %150
+  %sub232.i = fsub float %add221.i, %mul231.i
+  %151 = load float, float addrspace(3)* %69, align 4, !tbaa !248
+  %152 = load float, float addrspace(3)* %70, align 4, !tbaa !248
+  %mul242.i = fmul float %151, %152
+  %add243.i = fadd float %sub232.i, %mul242.i
+  %153 = load float, float addrspace(3)* %71, align 4, !tbaa !248
+  %154 = load float, float addrspace(3)* %72, align 4, !tbaa !248
+  %mul253.i = fmul float %153, %154
+  %sub254.i = fsub float %add243.i, %mul253.i
+  %155 = load float, float addrspace(3)* %73, align 4, !tbaa !248
+  %156 = load float, float addrspace(3)* %74, align 4, !tbaa !248
+  %mul264.i = fmul float %155, %156
+  %add265.i = fadd float %sub254.i, %mul264.i
+  %157 = load float, float addrspace(3)* %75, align 4, !tbaa !248
+  %158 = load float, float addrspace(3)* %76, align 4, !tbaa !248
+  %mul275.i = fmul float %157, %158
+  %sub276.i = fsub float %add265.i, %mul275.i
+  %159 = load float, float addrspace(3)* %77, align 4, !tbaa !248
+  %160 = load float, float addrspace(3)* %78, align 4, !tbaa !248
+  %mul286.i = fmul float %159, %160
+  %add287.i = fadd float %sub276.i, %mul286.i
+  %161 = load float, float addrspace(3)* %79, align 4, !tbaa !248
+  %162 = load float, float addrspace(3)* %80, align 4, !tbaa !248
+  %mul297.i = fmul float %161, %162
+  %sub298.i = fsub float %add287.i, %mul297.i
+  %163 = load float, float addrspace(3)* %81, align 4, !tbaa !248
+  %164 = load float, float addrspace(3)* %82, align 4, !tbaa !248
+  %mul308.i = fmul float %163, %164
+  %add309.i = fadd float %sub298.i, %mul308.i
+  %165 = load float, float addrspace(3)* %83, align 4, !tbaa !248
+  %166 = load float, float addrspace(3)* %84, align 4, !tbaa !248
+  %mul319.i = fmul float %165, %166
+  %sub320.i = fsub float %add309.i, %mul319.i
+  %167 = load float, float addrspace(3)* %85, align 4, !tbaa !248
+  %168 = load float, float addrspace(3)* %86, align 4, !tbaa !248
+  %mul330.i = fmul float %167, %168
+  %add331.i = fadd float %sub320.i, %mul330.i
+  %169 = load float, float addrspace(3)* %87, align 4, !tbaa !248
+  %170 = load float, float addrspace(3)* %88, align 4, !tbaa !248
+  %mul341.i = fmul float %169, %170
+  %sub342.i = fsub float %add331.i, %mul341.i
+  %171 = load float, float addrspace(3)* %89, align 4, !tbaa !248
+  %172 = load float, float addrspace(3)* %90, align 4, !tbaa !248
+  %mul352.i = fmul float %171, %172
+  %add353.i = fadd float %sub342.i, %mul352.i
+  %173 = load float, float addrspace(3)* %91, align 4, !tbaa !248
+  %174 = load float, float addrspace(3)* %92, align 4, !tbaa !248
+  %mul363.i = fmul float %173, %174
+  %sub364.i = fsub float %add353.i, %mul363.i
+  %175 = load float, float addrspace(3)* %93, align 4, !tbaa !248
+  %176 = load float, float addrspace(3)* %94, align 4, !tbaa !248
+  %mul374.i = fmul float %175, %176
+  %add375.i = fadd float %sub364.i, %mul374.i
+  %177 = load float, float addrspace(3)* %95, align 4, !tbaa !248
+  %178 = load float, float addrspace(3)* %96, align 4, !tbaa !248
+  %mul385.i = fmul float %177, %178
+  %sub386.i = fsub float %add375.i, %mul385.i
+  %179 = load float, float addrspace(3)* %97, align 4, !tbaa !248
+  %180 = load float, float addrspace(3)* %98, align 4, !tbaa !248
+  %mul396.i = fmul float %179, %180
+  %add397.i = fadd float %sub386.i, %mul396.i
+  %181 = load float, float addrspace(3)* %99, align 4, !tbaa !248
+  %182 = load float, float addrspace(3)* %100, align 4, !tbaa !248
+  %mul407.i = fmul float %181, %182
+  %sub408.i = fsub float %add397.i, %mul407.i
+  %183 = load float, float addrspace(3)* %101, align 4, !tbaa !248
+  %184 = load float, float addrspace(3)* %102, align 4, !tbaa !248
+  %mul418.i = fmul float %183, %184
+  %add419.i = fadd float %sub408.i, %mul418.i
+  %185 = load float, float addrspace(3)* %103, align 4, !tbaa !248
+  %186 = load float, float addrspace(3)* %104, align 4, !tbaa !248
+  %mul429.i = fmul float %185, %186
+  %sub430.i = fsub float %add419.i, %mul429.i
+  %187 = load float, float addrspace(3)* %105, align 4, !tbaa !248
+  %188 = load float, float addrspace(3)* %106, align 4, !tbaa !248
+  %mul440.i = fmul float %187, %188
+  %add441.i = fadd float %sub430.i, %mul440.i
+  %189 = load float, float addrspace(3)* %107, align 4, !tbaa !248
+  %190 = load float, float addrspace(3)* %108, align 4, !tbaa !248
+  %mul451.i = fmul float %189, %190
+  %sub452.i = fsub float %add441.i, %mul451.i
+  %191 = load float, float addrspace(3)* %109, align 4, !tbaa !248
+  %192 = load float, float addrspace(3)* %110, align 4, !tbaa !248
+  %mul462.i = fmul float %191, %192
+  %add463.i = fadd float %sub452.i, %mul462.i
+  %193 = load float, float addrspace(3)* %111, align 4, !tbaa !248
+  %194 = load float, float addrspace(3)* %112, align 4, !tbaa !248
+  %mul473.i = fmul float %193, %194
+  %sub474.i = fsub float %add463.i, %mul473.i
+  %add475.i = fadd float %CValue.01283.i, %sub474.i
+  %mul485.i = fmul float %131, %134
+  %mul495.i = fmul float %132, %133
+  %add496.i = fadd float %mul495.i, %mul485.i
+  %mul506.i = fmul float %135, %138
+  %add507.i = fadd float %add496.i, %mul506.i
+  %mul517.i = fmul float %136, %137
+  %add518.i = fadd float %mul517.i, %add507.i
+  %mul528.i = fmul float %139, %142
+  %add529.i = fadd float %add518.i, %mul528.i
+  %mul539.i = fmul float %140, %141
+  %add540.i = fadd float %mul539.i, %add529.i
+  %mul550.i = fmul float %143, %146
+  %add551.i = fadd float %add540.i, %mul550.i
+  %mul561.i = fmul float %144, %145
+  %add562.i = fadd float %mul561.i, %add551.i
+  %mul572.i = fmul float %147, %150
+  %add573.i = fadd float %add562.i, %mul572.i
+  %mul583.i = fmul float %148, %149
+  %add584.i = fadd float %mul583.i, %add573.i
+  %mul594.i = fmul float %151, %154
+  %add595.i = fadd float %add584.i, %mul594.i
+  %mul605.i = fmul float %152, %153
+  %add606.i = fadd float %mul605.i, %add595.i
+  %mul616.i = fmul float %155, %158
+  %add617.i = fadd float %add606.i, %mul616.i
+  %mul627.i = fmul float %156, %157
+  %add628.i = fadd float %mul627.i, %add617.i
+  %mul638.i = fmul float %159, %162
+  %add639.i = fadd float %add628.i, %mul638.i
+  %mul649.i = fmul float %160, %161
+  %add650.i = fadd float %mul649.i, %add639.i
+  %mul660.i = fmul float %163, %166
+  %add661.i = fadd float %add650.i, %mul660.i
+  %mul671.i = fmul float %164, %165
+  %add672.i = fadd float %mul671.i, %add661.i
+  %mul682.i = fmul float %167, %170
+  %add683.i = fadd float %add672.i, %mul682.i
+  %mul693.i = fmul float %168, %169
+  %add694.i = fadd float %mul693.i, %add683.i
+  %mul704.i = fmul float %171, %174
+  %add705.i = fadd float %add694.i, %mul704.i
+  %mul715.i = fmul float %172, %173
+  %add716.i = fadd float %mul715.i, %add705.i
+  %mul726.i = fmul float %175, %178
+  %add727.i = fadd float %add716.i, %mul726.i
+  %mul737.i = fmul float %176, %177
+  %add738.i = fadd float %mul737.i, %add727.i
+  %mul748.i = fmul float %179, %182
+  %add749.i = fadd float %add738.i, %mul748.i
+  %mul759.i = fmul float %180, %181
+  %add760.i = fadd float %mul759.i, %add749.i
+  %mul770.i = fmul float %183, %186
+  %add771.i = fadd float %add760.i, %mul770.i
+  %mul781.i = fmul float %184, %185
+  %add782.i = fadd float %mul781.i, %add771.i
+  %mul792.i = fmul float %187, %190
+  %add793.i = fadd float %add782.i, %mul792.i
+  %mul803.i = fmul float %188, %189
+  %add804.i = fadd float %mul803.i, %add793.i
+  %mul814.i = fmul float %191, %194
+  %add815.i = fadd float %add804.i, %mul814.i
+  %mul825.i = fmul float %192, %193
+  %add826.i = fadd float %mul825.i, %add815.i
+  %add827.i = fadd float %CValue1.01282.i, %add826.i
+  tail call void @llvm.amdgcn.s.waitcnt(i32 0) #2
+  tail call void @llvm.amdgcn.s.dcache.wb() #2
+  tail call void @llvm.amdgcn.s.barrier() #2
+  %inc.i = add nuw nsw i32 %k.01284.i, 1
+  %cmp.i = icmp slt i32 %inc.i, %div.i
+  br i1 %cmp.i, label %._crit_edge1286.i, label %._crit_edge.i.loopexit
+
+; <label>:195:                                    ; preds = %._crit_edge.i
+  %mul832.i = mul nsw i32 %conv.i.i.i, %11
+  %conv8331105.i = zext i32 %mul832.i to i64
+  %196 = add i64 %42, %10
+  %add834.i = add i64 %196, %conv8331105.i
+  %add838.i = add i64 %add834.i, %40
+  %sext = shl i64 %add838.i, 32
+  %197 = ashr exact i64 %sext, 32
+  %198 = getelementptr %"class.hc::short_vector::float_2.0", %"class.hc::short_vector::float_2.0" addrspace(1)* %9, i64 %197, i32 0
+  %199 = load float, float addrspace(1)* %198, align 4, !tbaa !243
+  %200 = getelementptr %"class.hc::short_vector::float_2.0", %"class.hc::short_vector::float_2.0" addrspace(1)* %9, i64 %197, i32 1
+  %201 = load float, float addrspace(1)* %200, align 4, !tbaa !249
+  %202 = fcmp uno float %199, 0.000000e+00
+  br i1 %202, label %205, label %203
+
+; <label>:203:                                    ; preds = %195
+  %204 = tail call zeroext i1 @llvm.amdgcn.class.f32(float %199, i32 516) #4
+  %..i = select i1 %204, float 0.000000e+00, float %199
+  br label %205
+
+; <label>:205:                                    ; preds = %195, %203
+  %cond.i = phi float [ 0.000000e+00, %195 ], [ %..i, %203 ]
+  %206 = fcmp uno float %201, 0.000000e+00
+  br i1 %206, label %209, label %207
+
+; <label>:207:                                    ; preds = %205
+  %208 = tail call zeroext i1 @llvm.amdgcn.class.f32(float %201, i32 516) #4
+  %.907.i = select i1 %208, float 0.000000e+00, float %201
+  br label %209
+
+; <label>:209:                                    ; preds = %205, %207
+  %cond859.i = phi float [ 0.000000e+00, %205 ], [ %.907.i, %207 ]
+  %mul861.i = fmul float %cond.i, %12
+  %mul863.i = fmul float %cond859.i, %13
+  %sub864.i = fsub float %mul861.i, %mul863.i
+  %mul866.i = fmul float %cond.i, %13
+  %mul868.i = fmul float %cond859.i, %12
+  %add869.i = fadd float %mul866.i, %mul868.i
+  %mul871.i = fmul float %CValue.0.lcssa.i, %14
+  %mul873.i = fmul float %CValue1.0.lcssa.i, %15
+  %sub874.i = fsub float %mul871.i, %mul873.i
+  %add875.i = fadd float %sub874.i, %sub864.i
+  store float %add875.i, float addrspace(1)* %198, align 4, !tbaa !243
+  %mul888.i = fmul float %CValue.0.lcssa.i, %15
+  %mul890.i = fmul float %CValue1.0.lcssa.i, %14
+  %add891.i = fadd float %mul890.i, %mul888.i
+  %add892.i = fadd float %add891.i, %add869.i
+  store float %add892.i, float addrspace(1)* %200, align 4, !tbaa !249
+  br label %"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEE.exit"
+
+"_ZZ26cgemm_NoTransAB_loopunrollRN2hc16accelerator_viewEPNS_12short_vector7float_2ElS4_lS4_liiiiiiS3_S3_ENK3$_0clERNS_11tiled_indexILi2EEE.exit": ; preds = %209, %._crit_edge.i
+  ret void
+}
+
+attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="fiji" "target-features"="+fp64-denormals,-fp32-denormals" "unsafe-fp-math"="false" "use-soft-float"="false" }
+attributes #1 = { argmemonly nounwind }
+attributes #2 = { nounwind }
+attributes #3 = { convergent nounwind }
+attributes #4 = { nounwind readnone }
+
+
+!232 = !{!233, !234, i64 6}
+!233 = !{!"hsa_kernel_dispatch_packet_s", !234, i64 0, !234, i64 2, !234, i64 4, !234, i64 6, !234, i64 8, !234, i64 10, !237, i64 12, !237, i64 16, !237, i64 20, !237, i64 24, !237, i64 28, !238, i64 32, !239, i64 40, !237, i64 48, !238, i64 56, !240, i64 64}
+!234 = !{!"short", !235, i64 0}
+!235 = !{!"omnipotent char", !236, i64 0}
+!236 = !{!"Simple C/C++ TBAA"}
+!237 = !{!"int", !235, i64 0}
+!238 = !{!"long", !235, i64 0}
+!239 = !{!"any pointer", !235, i64 0}
+!240 = !{!"hsa_signal_s", !238, i64 0}
+!241 = !{!238, !238, i64 0}
+!242 = !{!233, !234, i64 4}
+!243 = !{!244, !245, i64 0}
+!244 = !{!"_ZTSN2hc12short_vector7float_2E", !245, i64 0, !245, i64 4}
+!245 = !{!"float", !246, i64 0}
+!246 = !{!"omnipotent char", !247, i64 0}
+!247 = !{!"Simple C++ TBAA"}
+!248 = !{!245, !245, i64 0}
+!249 = !{!244, !245, i64 4}
+!250 = !{!251, !251, i64 0}
+!251 = !{!"double", !246, i64 0}
+!252 = !{!233, !237, i64 16}
+!253 = !{!254, !254, i64 0}
+!254 = !{!"any pointer", !246, i64 0}
+!255 = !{!256, !256, i64 0}
+!256 = !{!"long", !246, i64 0}
+!257 = !{!258, !258, i64 0}
+!258 = !{!"int", !246, i64 0}
+!259 = !{!233, !237, i64 12}