Index: include/llvm/CodeGen/LiveRangeEdit.h
===================================================================
--- include/llvm/CodeGen/LiveRangeEdit.h
+++ include/llvm/CodeGen/LiveRangeEdit.h
@@ -74,7 +74,7 @@
 
   /// DeadRemats - The saved instructions which have already been dead after
   /// rematerialization but not deleted yet -- to be done in postOptimization.
-  SmallPtrSet<MachineInstr *, 32> *DeadRemats;
+  SmallSetVector<MachineInstr *, 32> *DeadRemats;
 
   /// Remattable - Values defined by remattable instructions as identified by
   /// tii.isTriviallyReMaterializable().
@@ -126,7 +126,7 @@
   LiveRangeEdit(LiveInterval *parent, SmallVectorImpl<unsigned> &newRegs,
                 MachineFunction &MF, LiveIntervals &lis, VirtRegMap *vrm,
                 Delegate *delegate = nullptr,
-                SmallPtrSet<MachineInstr *, 32> *deadRemats = nullptr)
+                SmallSetVector<MachineInstr *, 32> *deadRemats = nullptr)
       : Parent(parent), NewRegs(newRegs), MRI(MF.getRegInfo()), LIS(lis),
         VRM(vrm), TII(*MF.getSubtarget().getInstrInfo()), TheDelegate(delegate),
         FirstNew(newRegs.size()), ScannedRemattable(false),
Index: lib/CodeGen/CodeGenPrepare.cpp
===================================================================
--- lib/CodeGen/CodeGenPrepare.cpp
+++ lib/CodeGen/CodeGenPrepare.cpp
@@ -15,6 +15,7 @@
 
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/ADT/DenseMap.h"
+#include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/SmallSet.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/Analysis/InstructionSimplify.h"
@@ -301,7 +302,7 @@
 
   if (!DisableBranchOpts) {
     MadeChange = false;
-    SmallPtrSet<BasicBlock*, 8> WorkList;
+    SmallSetVector<BasicBlock*, 8> WorkList;
     for (BasicBlock &BB : F) {
       SmallVector<BasicBlock *, 2> Successors(succ_begin(&BB), succ_end(&BB));
       MadeChange |= ConstantFoldTerminator(&BB, true);
@@ -317,7 +318,7 @@
     MadeChange |= !WorkList.empty();
     while (!WorkList.empty()) {
       BasicBlock *BB = *WorkList.begin();
-      WorkList.erase(BB);
+      WorkList.remove(BB);
       SmallVector<BasicBlock*, 2> Successors(succ_begin(BB), succ_end(BB));
 
       DeleteDeadBlock(BB);
Index: lib/CodeGen/InlineSpiller.cpp
===================================================================
--- lib/CodeGen/InlineSpiller.cpp
+++ lib/CodeGen/InlineSpiller.cpp
@@ -77,7 +77,7 @@
   // Map from pair of (StackSlot and Original VNI) to a set of spills which
   // have the same stackslot and have equal values defined by Original VNI.
   // These spills are mergeable and are hoist candiates.
-  typedef MapVector<std::pair<int, VNInfo *>, SmallPtrSet<MachineInstr *, 16>>
+  typedef MapVector<std::pair<int, VNInfo *>, SmallSetVector<MachineInstr *, 16>>
       MergeableSpillsMap;
   MergeableSpillsMap MergeableSpills;
 
@@ -90,19 +90,19 @@
                      unsigned &LiveReg);
 
   void rmRedundantSpills(
-      SmallPtrSet<MachineInstr *, 16> &Spills,
+      SmallSetVector<MachineInstr *, 16> &Spills,
       SmallVectorImpl<MachineInstr *> &SpillsToRm,
       DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill);
 
   void getVisitOrders(
-      MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills,
+      MachineBasicBlock *Root, SmallSetVector<MachineInstr *, 16> &Spills,
       SmallVectorImpl<MachineDomTreeNode *> &Orders,
       SmallVectorImpl<MachineInstr *> &SpillsToRm,
       DenseMap<MachineDomTreeNode *, unsigned> &SpillsToKeep,
       DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill);
 
   void runHoistSpills(unsigned OrigReg, VNInfo &OrigVNI,
-                      SmallPtrSet<MachineInstr *, 16> &Spills,
+                      SmallSetVector<MachineInstr *, 16> &Spills,
                       SmallVectorImpl<MachineInstr *> &SpillsToRm,
                       DenseMap<MachineBasicBlock *, unsigned> &SpillsToIns);
 
@@ -1074,7 +1074,7 @@
   SlotIndex Idx = LIS.getInstructionIndex(Spill);
   VNInfo *OrigVNI = LIS.getInterval(Original).getVNInfoAt(Idx.getRegSlot());
   std::pair<int, VNInfo *> MIdx = std::make_pair(StackSlot, OrigVNI);
-  return MergeableSpills[MIdx].erase(&Spill);
+  return MergeableSpills[MIdx].remove(&Spill);
 }
 
 /// Check BB to see if it is a possible target BB to place a hoisted spill,
@@ -1108,7 +1108,7 @@
 /// SpillsToRm, and save the spill to keep and its BB in SpillBBToSpill map.
 ///
 void HoistSpillHelper::rmRedundantSpills(
-    SmallPtrSet<MachineInstr *, 16> &Spills,
+    SmallSetVector<MachineInstr *, 16> &Spills,
     SmallVectorImpl<MachineInstr *> &SpillsToRm,
     DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill) {
   // For each spill saw, check SpillBBToSpill[] and see if its BB already has
@@ -1130,7 +1130,7 @@
     }
   }
   for (const auto SpillToRm : SpillsToRm)
-    Spills.erase(SpillToRm);
+    Spills.remove(SpillToRm);
 }
 
 /// Starting from \p Root find a top-down traversal order of the dominator
@@ -1141,7 +1141,7 @@
 /// \post SpillsToRm.union(Spills\@post) == Spills\@pre
 ///
 void HoistSpillHelper::getVisitOrders(
-    MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills,
+    MachineBasicBlock *Root, SmallSetVector<MachineInstr *, 16> &Spills,
     SmallVectorImpl<MachineDomTreeNode *> &Orders,
     SmallVectorImpl<MachineInstr *> &SpillsToRm,
     DenseMap<MachineDomTreeNode *, unsigned> &SpillsToKeep,
@@ -1229,7 +1229,7 @@
 /// \p SpillsToIns.
 ///
 void HoistSpillHelper::runHoistSpills(
-    unsigned OrigReg, VNInfo &OrigVNI, SmallPtrSet<MachineInstr *, 16> &Spills,
+    unsigned OrigReg, VNInfo &OrigVNI, SmallSetVector<MachineInstr *, 16> &Spills,
     SmallVectorImpl<MachineInstr *> &SpillsToRm,
     DenseMap<MachineBasicBlock *, unsigned> &SpillsToIns) {
   // Visit order of dominator tree nodes.
@@ -1387,7 +1387,7 @@
     unsigned OrigReg = SlotToOrigReg[Slot];
     LiveInterval &OrigLI = LIS.getInterval(OrigReg);
     VNInfo *OrigVNI = Ent.first.second;
-    SmallPtrSet<MachineInstr *, 16> &EqValSpills = Ent.second;
+    SmallSetVector<MachineInstr *, 16> &EqValSpills = Ent.second;
     if (Ent.second.empty())
       continue;
 
Index: lib/CodeGen/MachineBlockPlacement.cpp
===================================================================
--- lib/CodeGen/MachineBlockPlacement.cpp
+++ lib/CodeGen/MachineBlockPlacement.cpp
@@ -1608,7 +1608,7 @@
   buildChain(&F->front(), FunctionChain);
 
 #ifndef NDEBUG
-  typedef SmallPtrSet<MachineBasicBlock *, 16> FunctionBlockSetType;
+  typedef SmallSetVector<MachineBasicBlock *, 16> FunctionBlockSetType;
 #endif
   DEBUG({
     // Crash at the end so we get all of the debugging output first.
@@ -1618,7 +1618,7 @@
       FunctionBlockSet.insert(&MBB);
 
     for (MachineBasicBlock *ChainBB : FunctionChain)
-      if (!FunctionBlockSet.erase(ChainBB)) {
+      if (!FunctionBlockSet.remove(ChainBB)) {
         BadFunc = true;
         dbgs() << "Function chain contains a block not in the function!\n"
                << "  Bad block:    " << getBlockName(ChainBB) << "\n";
Index: lib/CodeGen/MachinePipeliner.cpp
===================================================================
--- lib/CodeGen/MachinePipeliner.cpp
+++ lib/CodeGen/MachinePipeliner.cpp
@@ -254,14 +254,14 @@
 
   /// We may create a new instruction, so remember it because it
   /// must be deleted when the pass is finished.
-  SmallPtrSet<MachineInstr *, 4> NewMIs;
+  SmallSetVector<MachineInstr *, 4> NewMIs;
 
   /// Helper class to implement Johnson's circuit finding algorithm.
   class Circuits {
     std::vector<SUnit> &SUnits;
     SetVector<SUnit *> Stack;
     BitVector Blocked;
-    SmallVector<SmallPtrSet<SUnit *, 4>, 10> B;
+    SmallVector<SmallSetVector<SUnit *, 4>, 10> B;
     SmallVector<SmallVector<int, 4>, 16> AdjK;
     unsigned NumPaths;
     static unsigned MaxPaths;
@@ -274,7 +274,7 @@
     void reset() {
       Stack.clear();
       Blocked.reset();
-      B.assign(SUnits.size(), SmallPtrSet<SUnit *, 4>());
+      B.assign(SUnits.size(), SmallSetVector<SUnit *, 4>());
       NumPaths = 0;
     }
     void createAdjacencyStructure(SwingSchedulerDAG *DAG);
@@ -1501,12 +1501,12 @@
 /// Unblock a node in the circuit finding algorithm.
 void SwingSchedulerDAG::Circuits::unblock(int U) {
   Blocked.reset(U);
-  SmallPtrSet<SUnit *, 4> &BU = B[U];
+  SmallSetVector<SUnit *, 4> &BU = B[U];
   while (!BU.empty()) {
-    SmallPtrSet<SUnit *, 4>::iterator SI = BU.begin();
+    SmallSetVector<SUnit *, 4>::iterator SI = BU.begin();
     assert(SI != BU.end() && "Invalid B set.");
     SUnit *W = *SI;
-    BU.erase(W);
+    BU.remove(W);
     if (Blocked.test(W->NodeNum))
       unblock(W->NodeNum);
   }
Index: lib/CodeGen/MachineVerifier.cpp
===================================================================
--- lib/CodeGen/MachineVerifier.cpp
+++ lib/CodeGen/MachineVerifier.cpp
@@ -27,6 +27,7 @@
 #include "llvm/ADT/DenseSet.h"
 #include "llvm/ADT/DepthFirstIterator.h"
 #include "llvm/ADT/SetOperations.h"
+#include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/Analysis/EHPersonalities.h"
 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
@@ -1443,7 +1444,7 @@
 void MachineVerifier::calcRegsPassed() {
   // First push live-out regs to successors' vregsPassed. Remember the MBBs that
   // have any vregsPassed.
-  SmallPtrSet<const MachineBasicBlock*, 8> todo;
+  SmallSetVector<const MachineBasicBlock*, 8> todo;
   for (const auto &MBB : *MF) {
     BBInfo &MInfo = MBBInfoMap[&MBB];
     if (!MInfo.reachable)
@@ -1460,7 +1461,7 @@
   // final state regardless of DenseSet iteration order.
   while (!todo.empty()) {
     const MachineBasicBlock *MBB = *todo.begin();
-    todo.erase(MBB);
+    todo.remove(MBB);
     BBInfo &MInfo = MBBInfoMap[MBB];
     for (MachineBasicBlock::const_succ_iterator SuI = MBB->succ_begin(),
            SuE = MBB->succ_end(); SuI != SuE; ++SuI) {
@@ -1478,7 +1479,7 @@
 // similar to calcRegsPassed, only backwards.
 void MachineVerifier::calcRegsRequired() {
   // First push live-in regs to predecessors' vregsRequired.
-  SmallPtrSet<const MachineBasicBlock*, 8> todo;
+  SmallSetVector<const MachineBasicBlock*, 8> todo;
   for (const auto &MBB : *MF) {
     BBInfo &MInfo = MBBInfoMap[&MBB];
     for (MachineBasicBlock::const_pred_iterator PrI = MBB.pred_begin(),
@@ -1493,7 +1494,7 @@
   // same final state regardless of DenseSet iteration order.
   while (!todo.empty()) {
     const MachineBasicBlock *MBB = *todo.begin();
-    todo.erase(MBB);
+    todo.remove(MBB);
     BBInfo &MInfo = MBBInfoMap[MBB];
     for (MachineBasicBlock::const_pred_iterator PrI = MBB->pred_begin(),
            PrE = MBB->pred_end(); PrI != PrE; ++PrI) {
Index: lib/CodeGen/OptimizePHIs.cpp
===================================================================
--- lib/CodeGen/OptimizePHIs.cpp
+++ lib/CodeGen/OptimizePHIs.cpp
@@ -13,6 +13,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "llvm/CodeGen/Passes.h"
+#include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
@@ -47,8 +48,8 @@
     }
 
   private:
-    typedef SmallPtrSet<MachineInstr*, 16> InstrSet;
-    typedef SmallPtrSetIterator<MachineInstr*> InstrSetIterator;
+    typedef SmallSetVector<MachineInstr*, 16> InstrSet;
+    typedef SmallSetVector<MachineInstr*, 16>::iterator InstrSetIterator;
 
     bool IsSingleValuePHICycle(MachineInstr *MI, unsigned &SingleValReg,
                                InstrSet &PHIsInCycle);
@@ -92,7 +93,7 @@
   unsigned DstReg = MI->getOperand(0).getReg();
 
   // See if we already saw this register.
-  if (!PHIsInCycle.insert(MI).second)
+  if (!PHIsInCycle.insert(MI))
     return true;
 
   // Don't scan crazily complex things.
@@ -137,7 +138,7 @@
          "PHI destination is not a virtual register");
 
   // See if we already saw this register.
-  if (!PHIsInCycle.insert(MI).second)
+  if (!PHIsInCycle.insert(MI))
     return true;
 
   // Don't scan crazily complex things.
Index: lib/CodeGen/PHIElimination.cpp
===================================================================
--- lib/CodeGen/PHIElimination.cpp
+++ lib/CodeGen/PHIElimination.cpp
@@ -15,6 +15,7 @@
 
 #include "PHIEliminationUtils.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/SmallPtrSet.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
@@ -96,7 +97,7 @@
     VRegPHIUse VRegPHIUseCount;
 
     // Defs of PHI sources which are implicit_def.
-    SmallPtrSet<MachineInstr*, 4> ImpDefs;
+    SmallSetVector<MachineInstr*, 4> ImpDefs;
 
     // Map reusable lowered PHI node -> incoming join register.
     typedef DenseMap<MachineInstr*, unsigned,
Index: lib/CodeGen/PrologEpilogInserter.cpp
===================================================================
--- lib/CodeGen/PrologEpilogInserter.cpp
+++ lib/CodeGen/PrologEpilogInserter.cpp
@@ -406,7 +406,7 @@
   // - Restore -> LiveOut.
   // The live-out is not attached to the block, so no need to keep
   // Restore in this set.
-  SmallPtrSet<MachineBasicBlock *, 8> Visited;
+  SmallSetVector<MachineBasicBlock *, 8> Visited;
   SmallVector<MachineBasicBlock *, 8> WorkList;
   MachineBasicBlock *Entry = &MF.front();
   MachineBasicBlock *Save = MFI.getSavePoint();
@@ -436,7 +436,7 @@
     // Enqueue all the successors not already visited.
     // Those are by construction either before Save or after Restore.
     for (MachineBasicBlock *SuccBB : CurBB->successors())
-      if (Visited.insert(SuccBB).second)
+      if (Visited.insert(SuccBB))
         WorkList.push_back(SuccBB);
   }
 
Index: lib/CodeGen/RegAllocBase.h
===================================================================
--- lib/CodeGen/RegAllocBase.h
+++ lib/CodeGen/RegAllocBase.h
@@ -37,6 +37,7 @@
 #ifndef LLVM_LIB_CODEGEN_REGALLOCBASE_H
 #define LLVM_LIB_CODEGEN_REGALLOCBASE_H
 
+#include "llvm/ADT/SetVector.h"
 #include "llvm/CodeGen/LiveInterval.h"
 #include "llvm/CodeGen/RegisterClassInfo.h"
 
@@ -69,7 +70,7 @@
   /// dead after remat is saved in DeadRemats. The deletion of such inst is
   /// postponed till all the allocations are done, so its remat expr is
   /// always available for the remat of all the siblings of the original reg.
-  SmallPtrSet<MachineInstr *, 32> DeadRemats;
+  SmallSetVector<MachineInstr *, 32> DeadRemats;
 
   RegAllocBase()
     : TRI(nullptr), MRI(nullptr), VRM(nullptr), LIS(nullptr), Matrix(nullptr) {}
Index: lib/CodeGen/RegAllocGreedy.cpp
===================================================================
--- lib/CodeGen/RegAllocGreedy.cpp
+++ lib/CodeGen/RegAllocGreedy.cpp
@@ -109,7 +109,7 @@
                  private LiveRangeEdit::Delegate {
   // Convenient shortcuts.
   typedef std::priority_queue<std::pair<unsigned, unsigned> > PQueue;
-  typedef SmallPtrSet<LiveInterval *, 4> SmallLISet;
+  typedef SmallSetVector<LiveInterval *, 4> SmallLISet;
   typedef SmallSet<unsigned, 16> SmallVirtRegSet;
 
   // context
Index: lib/CodeGen/RegAllocPBQP.cpp
===================================================================
--- lib/CodeGen/RegAllocPBQP.cpp
+++ lib/CodeGen/RegAllocPBQP.cpp
@@ -130,7 +130,7 @@
   /// dead after remat is saved in DeadRemats. The deletion of such inst is
   /// postponed till all the allocations are done, so its remat expr is
   /// always available for the remat of all the siblings of the original reg.
-  SmallPtrSet<MachineInstr *, 32> DeadRemats;
+  SmallSetVector<MachineInstr *, 32> DeadRemats;
 
   /// \brief Finds the initial set of vreg intervals to allocate.
   void findVRegIntervalsToAlloc(const MachineFunction &MF, LiveIntervals &LIS);
Index: lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -5959,7 +5959,7 @@
 
   // Clear the operands list, updating used nodes to remove this from their
   // use list.  Keep track of any operands that become dead as a result.
-  SmallPtrSet<SDNode*, 16> DeadNodeSet;
+  SmallSetVector<SDNode*, 16> DeadNodeSet;
   for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ) {
     SDUse &Use = *I++;
     SDNode *Used = Use.getNode();
Index: lib/CodeGen/SjLjEHPrepare.cpp
===================================================================
--- lib/CodeGen/SjLjEHPrepare.cpp
+++ lib/CodeGen/SjLjEHPrepare.cpp
@@ -321,7 +321,7 @@
     LandingPadInst *LPI = UnwindBlock->getLandingPadInst();
 
     // Place PHIs into a set to avoid invalidating the iterator.
-    SmallPtrSet<PHINode *, 8> PHIsToDemote;
+    SmallSetVector<PHINode *, 8> PHIsToDemote;
     for (BasicBlock::iterator PN = UnwindBlock->begin(); isa<PHINode>(PN); ++PN)
       PHIsToDemote.insert(cast<PHINode>(PN));
     if (PHIsToDemote.empty())
Index: lib/CodeGen/SplitKit.cpp
===================================================================
--- lib/CodeGen/SplitKit.cpp
+++ lib/CodeGen/SplitKit.cpp
@@ -801,8 +801,8 @@
     DenseSet<unsigned> &NotToHoistSet, SmallVectorImpl<VNInfo *> &BackCopies) {
   LiveInterval *LI = &LIS.getInterval(Edit->get(0));
   LiveInterval *Parent = &Edit->getParent();
-  SmallVector<SmallPtrSet<VNInfo *, 8>, 8> EqualVNs(Parent->getNumValNums());
-  SmallPtrSet<VNInfo *, 8> DominatedVNIs;
+  SmallVector<SmallSetVector<VNInfo *, 8>, 8> EqualVNs(Parent->getNumValNums());
+  SmallSetVector<VNInfo *, 8> DominatedVNIs;
 
   // Aggregate VNIs having the same value as ParentVNI.
   for (VNInfo *VNI : LI->valnos) {
@@ -818,8 +818,8 @@
     VNInfo *ParentVNI = Parent->getValNumInfo(i);
     if (!NotToHoistSet.count(ParentVNI->id))
       continue;
-    SmallPtrSetIterator<VNInfo *> It1 = EqualVNs[ParentVNI->id].begin();
-    SmallPtrSetIterator<VNInfo *> It2 = It1;
+    SmallSetVector<VNInfo *, 8>::iterator It1 = EqualVNs[ParentVNI->id].begin();
+    SmallSetVector<VNInfo *, 8>::iterator It2 = It1;
     for (; It1 != EqualVNs[ParentVNI->id].end(); ++It1) {
       It2 = It1;
       for (++It2; It2 != EqualVNs[ParentVNI->id].end(); ++It2) {