Index: lldb.xcodeproj/project.pbxproj =================================================================== --- lldb.xcodeproj/project.pbxproj +++ lldb.xcodeproj/project.pbxproj @@ -907,6 +907,8 @@ AF0EBBEC185941360059E52F /* SBQueue.h in Headers */ = {isa = PBXBuildFile; fileRef = AF0EBBEA185941360059E52F /* SBQueue.h */; settings = {ATTRIBUTES = (Public, ); }; }; AF0EBBED185941360059E52F /* SBQueueItem.h in Headers */ = {isa = PBXBuildFile; fileRef = AF0EBBEB185941360059E52F /* SBQueueItem.h */; settings = {ATTRIBUTES = (Public, ); }; }; AF0F6E501739A76D009180FE /* RegisterContextKDP_arm64.cpp in Sources */ = {isa = PBXBuildFile; fileRef = AF0F6E4E1739A76D009180FE /* RegisterContextKDP_arm64.cpp */; }; + AF1083921DB9738D0083E3A1 /* ARM64_LLDB_Registers.cpp in Sources */ = {isa = PBXBuildFile; fileRef = AF1083901DB9738D0083E3A1 /* ARM64_LLDB_Registers.cpp */; }; + AF1083931DB9738D0083E3A1 /* ARM64_LLDB_Registers.h in Headers */ = {isa = PBXBuildFile; fileRef = AF1083911DB9738D0083E3A1 /* ARM64_LLDB_Registers.h */; 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path = RegisterContextKDP_arm64.h; sourceTree = ""; }; + AF1083901DB9738D0083E3A1 /* ARM64_LLDB_Registers.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = ARM64_LLDB_Registers.cpp; path = source/Utility/ARM64_LLDB_Registers.cpp; sourceTree = ""; }; + AF1083911DB9738D0083E3A1 /* ARM64_LLDB_Registers.h */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.c.h; name = ARM64_LLDB_Registers.h; path = source/Utility/ARM64_LLDB_Registers.h; sourceTree = ""; }; AF1729D4182C907200E0AB97 /* HistoryThread.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = HistoryThread.cpp; path = Utility/HistoryThread.cpp; sourceTree = ""; }; AF1729D5182C907200E0AB97 /* HistoryUnwind.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; name = HistoryUnwind.cpp; path = Utility/HistoryUnwind.cpp; sourceTree = ""; }; AF1F7B05189C904B0087DB9C /* AppleGetPendingItemsHandler.cpp */ = {isa = PBXFileReference; fileEncoding = 4; lastKnownFileType = sourcecode.cpp.cpp; path = AppleGetPendingItemsHandler.cpp; sourceTree = ""; }; @@ -4199,6 +4203,8 @@ 26ECA04213665FED008D1F18 /* ARM_DWARF_Registers.cpp */, 264A12FF137252C700875C42 /* ARM64_DWARF_Registers.h */, 264A12FE137252C700875C42 /* ARM64_DWARF_Registers.cpp */, + AF1083901DB9738D0083E3A1 /* ARM64_LLDB_Registers.cpp */, + AF1083911DB9738D0083E3A1 /* ARM64_LLDB_Registers.h */, 264723A511FA076E00DE380C /* CleanUp.h */, 3F81691B1ABA242B001DA9DF /* ConvertEnum.h */, 3F8169171ABA2419001DA9DF /* ConvertEnum.cpp */, @@ -6444,6 +6450,7 @@ 30B38A001CAAA6D7009524E3 /* ClangUtil.h in Headers */, AFD65C821D9B5B2E00D93120 /* RegisterContextMinidump_x86_64.h in Headers */, 238F2BA11D2C835A001FF92A /* StructuredDataPlugin.h in Headers */, + AF1083931DB9738D0083E3A1 /* ARM64_LLDB_Registers.h in Headers */, AF415AE81D949E4400FCE0D4 /* x86AssemblyInspectionEngine.h in Headers */, AF8AD62F1BEC28A400150209 /* PlatformAppleTVSimulator.h in Headers */, 238F2BA91D2C85FA001FF92A /* StructuredDataDarwinLog.h in Headers */, @@ -7614,6 +7621,7 @@ 260CC65015D0440D002BF2E0 /* OptionValueFormat.cpp in Sources */, 260CC65115D0440D002BF2E0 /* OptionValueSInt64.cpp in Sources */, 260CC65215D0440D002BF2E0 /* OptionValueString.cpp in Sources */, + AF1083921DB9738D0083E3A1 /* ARM64_LLDB_Registers.cpp in Sources */, 6D55B2911A8A806200A70529 /* GDBRemoteCommunicationServerLLGS.cpp in Sources */, 260CC65315D0440D002BF2E0 /* OptionValueUInt64.cpp in Sources */, 260CC65415D0440D002BF2E0 /* OptionValueUUID.cpp in Sources */, Index: source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp =================================================================== --- source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp +++ source/Plugins/Instruction/ARM64/EmulateInstructionARM64.cpp @@ -21,7 +21,7 @@ #include "Plugins/Process/Utility/ARMDefines.h" #include "Plugins/Process/Utility/ARMUtils.h" -#include "Utility/ARM64_DWARF_Registers.h" +#include "Utility/ARM64_LLDB_Registers.h" #include "llvm/ADT/STLExtras.h" #include "llvm/Support/MathExtras.h" // for SignExtend32 template function @@ -168,33 +168,25 @@ if (reg_kind == eRegisterKindGeneric) { switch (reg_num) { case LLDB_REGNUM_GENERIC_PC: - reg_kind = eRegisterKindDWARF; - reg_num = arm64_dwarf::pc; + reg_kind = eRegisterKindLLDB; + reg_num = arm64_lldb::gpr_pc; break; case LLDB_REGNUM_GENERIC_SP: - reg_kind = eRegisterKindDWARF; - reg_num = arm64_dwarf::sp; + reg_kind = eRegisterKindLLDB; + reg_num = arm64_lldb::gpr_sp; break; case LLDB_REGNUM_GENERIC_FP: - reg_kind = eRegisterKindDWARF; - reg_num = arm64_dwarf::fp; + reg_kind = eRegisterKindLLDB; + reg_num = arm64_lldb::gpr_fp; break; case LLDB_REGNUM_GENERIC_RA: - reg_kind = eRegisterKindDWARF; - reg_num = arm64_dwarf::lr; + reg_kind = eRegisterKindLLDB; + reg_num = arm64_lldb::gpr_lr; break; case LLDB_REGNUM_GENERIC_FLAGS: - // There is no DWARF register number for the CPSR right now... - reg_info.name = "cpsr"; - reg_info.alt_name = NULL; - reg_info.byte_size = 4; - reg_info.byte_offset = 0; - reg_info.encoding = eEncodingUint; - reg_info.format = eFormatHex; - for (uint32_t i = 0; i < lldb::kNumRegisterKinds; ++i) - reg_info.kinds[reg_kind] = LLDB_INVALID_REGNUM; - reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS; - return true; + reg_kind = eRegisterKindLLDB; + reg_num = arm64_lldb::gpr_cpsr; + break; default: return false; @@ -201,8 +193,8 @@ } } - if (reg_kind == eRegisterKindDWARF) - return arm64_dwarf::GetRegisterInfo(reg_num, reg_info); + if (reg_kind == eRegisterKindLLDB) + return arm64_lldb::GetRegisterInfo(reg_num, reg_info); return false; } @@ -427,17 +419,12 @@ evaluate_options & eEmulateInstructionOptionIgnoreConditions; bool success = false; - // if (m_opcode_cpsr == 0 || m_ignore_conditions == false) - // { - // m_opcode_cpsr = ReadRegisterUnsigned (eRegisterKindGeneric, - // // use eRegisterKindDWARF is we ever get a cpsr DWARF register - // number - // LLDB_REGNUM_GENERIC_FLAGS, - // // use arm64_dwarf::cpsr if we - // ever get one - // 0, - // &success); - // } + // if (m_opcode_cpsr == 0 || m_ignore_conditions == false) + // { + // m_opcode_cpsr = ReadRegisterUnsigned (eRegisterKindLLDB, + // arm64_lldb::gpr_cpsr, 0, + // &success); + // } // Only return false if we are unable to read the CPSR if we care about // conditions @@ -446,8 +433,8 @@ uint32_t orig_pc_value = 0; if (auto_advance_pc) { - orig_pc_value = - ReadRegisterUnsigned(eRegisterKindDWARF, arm64_dwarf::pc, 0, &success); + orig_pc_value = ReadRegisterUnsigned(eRegisterKindLLDB, arm64_lldb::gpr_pc, + 0, &success); if (!success) return false; } @@ -458,8 +445,8 @@ return false; if (auto_advance_pc) { - uint32_t new_pc_value = - ReadRegisterUnsigned(eRegisterKindDWARF, arm64_dwarf::pc, 0, &success); + uint32_t new_pc_value = ReadRegisterUnsigned( + eRegisterKindLLDB, arm64_lldb::gpr_pc, 0, &success); if (!success) return false; @@ -467,7 +454,7 @@ EmulateInstruction::Context context; context.type = eContextAdvancePC; context.SetNoArgs(); - if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, arm64_dwarf::pc, + if (!WriteRegisterUnsigned(context, eRegisterKindLLDB, arm64_lldb::gpr_pc, orig_pc_value + 4)) return false; } @@ -478,18 +465,18 @@ bool EmulateInstructionARM64::CreateFunctionEntryUnwind( UnwindPlan &unwind_plan) { unwind_plan.Clear(); - unwind_plan.SetRegisterKind(eRegisterKindDWARF); + unwind_plan.SetRegisterKind(eRegisterKindLLDB); UnwindPlan::RowSP row(new UnwindPlan::Row); // Our previous Call Frame Address is the stack pointer - row->GetCFAValue().SetIsRegisterPlusOffset(arm64_dwarf::sp, 0); + row->GetCFAValue().SetIsRegisterPlusOffset(arm64_lldb::gpr_sp, 0); unwind_plan.AppendRow(row); unwind_plan.SetSourceName("EmulateInstructionARM64"); unwind_plan.SetSourcedFromCompiler(eLazyBoolNo); unwind_plan.SetUnwindPlanValidAtAllInstructions(eLazyBoolYes); - unwind_plan.SetReturnAddressRegister(arm64_dwarf::lr); + unwind_plan.SetReturnAddressRegister(arm64_lldb::gpr_lr); return true; } @@ -497,7 +484,7 @@ if (m_arch.GetTriple().isAndroid()) return LLDB_INVALID_REGNUM; // Don't use frame pointer on android - return arm64_dwarf::fp; + return arm64_lldb::gpr_fp; } bool EmulateInstructionARM64::UsingAArch32() { @@ -664,8 +651,8 @@ return false; // UNDEFINED; } uint64_t result; - uint64_t operand1 = ReadRegisterUnsigned(eRegisterKindDWARF, - arm64_dwarf::x0 + n, 0, &success); + uint64_t operand1 = ReadRegisterUnsigned(eRegisterKindLLDB, + arm64_lldb::gpr_x0 + n, 0, &success); uint64_t operand2 = imm; bit carry_in; @@ -690,18 +677,19 @@ Context context; RegisterInfo reg_info_Rn; - if (arm64_dwarf::GetRegisterInfo(n, reg_info_Rn)) + if (arm64_lldb::GetRegisterInfo(n, reg_info_Rn)) context.SetRegisterPlusOffset(reg_info_Rn, imm); - if (n == GetFramePointerRegisterNumber() && d == arm64_dwarf::sp && + if (n == GetFramePointerRegisterNumber() && d == arm64_lldb::gpr_sp && !setflags) { // 'mov sp, fp' - common epilogue instruction, CFA is now in terms // of the stack pointer, instead of frame pointer. context.type = EmulateInstruction::eContextRestoreStackPointer; - } else if ((n == arm64_dwarf::sp || n == GetFramePointerRegisterNumber()) && - d == arm64_dwarf::sp && !setflags) { + } else if ((n == arm64_lldb::gpr_sp || + n == GetFramePointerRegisterNumber()) && + d == arm64_lldb::gpr_sp && !setflags) { context.type = EmulateInstruction::eContextAdjustStackPointer; - } else if (d == GetFramePointerRegisterNumber() && n == arm64_dwarf::sp && + } else if (d == GetFramePointerRegisterNumber() && n == arm64_lldb::gpr_sp && !setflags) { context.type = EmulateInstruction::eContextSetFramePointer; } else { @@ -708,9 +696,9 @@ context.type = EmulateInstruction::eContextImmediate; } - // If setflags && d == arm64_dwarf::sp then d = WZR/XZR. See CMN, CMP - if (!setflags || d != arm64_dwarf::sp) - WriteRegisterUnsigned(context, eRegisterKindDWARF, arm64_dwarf::x0 + d, + // If setflags && d == arm64_lldb::gpr_sp then d = WZR/XZR. See CMN, CMP + if (!setflags || d != arm64_lldb::gpr_sp) + WriteRegisterUnsigned(context, eRegisterKindLLDB, arm64_lldb::gpr_x0 + d, result); return false; @@ -804,18 +792,22 @@ RegisterInfo reg_info_base; RegisterInfo reg_info_Rt; RegisterInfo reg_info_Rt2; - if (!GetRegisterInfo(eRegisterKindDWARF, arm64_dwarf::x0 + n, reg_info_base)) + if (!GetRegisterInfo(eRegisterKindLLDB, arm64_lldb::gpr_x0 + n, + reg_info_base)) return false; if (vector) { - if (!GetRegisterInfo(eRegisterKindDWARF, arm64_dwarf::v0 + n, reg_info_Rt)) + if (!GetRegisterInfo(eRegisterKindLLDB, arm64_lldb::fpu_d0 + t, + reg_info_Rt)) return false; - if (!GetRegisterInfo(eRegisterKindDWARF, arm64_dwarf::v0 + n, reg_info_Rt2)) + if (!GetRegisterInfo(eRegisterKindLLDB, arm64_lldb::fpu_d0 + t2, + reg_info_Rt2)) return false; } else { - if (!GetRegisterInfo(eRegisterKindDWARF, arm64_dwarf::x0 + t, reg_info_Rt)) + if (!GetRegisterInfo(eRegisterKindLLDB, arm64_lldb::gpr_x0 + t, + reg_info_Rt)) return false; - if (!GetRegisterInfo(eRegisterKindDWARF, arm64_dwarf::x0 + t2, + if (!GetRegisterInfo(eRegisterKindLLDB, arm64_lldb::gpr_x0 + t2, reg_info_Rt2)) return false; } @@ -823,10 +815,10 @@ bool success = false; if (n == 31) { // CheckSPAlignment(); - address = - ReadRegisterUnsigned(eRegisterKindDWARF, arm64_dwarf::sp, 0, &success); + address = ReadRegisterUnsigned(eRegisterKindLLDB, arm64_lldb::gpr_sp, 0, + &success); } else - address = ReadRegisterUnsigned(eRegisterKindDWARF, arm64_dwarf::x0 + n, 0, + address = ReadRegisterUnsigned(eRegisterKindLLDB, arm64_lldb::gpr_x0 + n, 0, &success); wb_address = address + idx; @@ -990,10 +982,10 @@ RegisterValue data_Rt; if (n == 31) - address = - ReadRegisterUnsigned(eRegisterKindDWARF, arm64_dwarf::sp, 0, &success); + address = ReadRegisterUnsigned(eRegisterKindLLDB, arm64_lldb::gpr_sp, 0, + &success); else - address = ReadRegisterUnsigned(eRegisterKindDWARF, arm64_dwarf::x0 + n, 0, + address = ReadRegisterUnsigned(eRegisterKindLLDB, arm64_lldb::gpr_x0 + n, 0, &success); if (!success) @@ -1003,11 +995,12 @@ address += offset; RegisterInfo reg_info_base; - if (!GetRegisterInfo(eRegisterKindDWARF, arm64_dwarf::x0 + n, reg_info_base)) + if (!GetRegisterInfo(eRegisterKindLLDB, arm64_lldb::gpr_x0 + n, + reg_info_base)) return false; RegisterInfo reg_info_Rt; - if (!GetRegisterInfo(eRegisterKindDWARF, arm64_dwarf::x0 + t, reg_info_Rt)) + if (!GetRegisterInfo(eRegisterKindLLDB, arm64_lldb::gpr_x0 + t, reg_info_Rt)) return false; Context context; @@ -1096,7 +1089,7 @@ switch (branch_type) { case BranchType_CALL: { addr_t x30 = pc + 4; - if (!WriteRegisterUnsigned(context, eRegisterKindDWARF, arm64_dwarf::x30, + if (!WriteRegisterUnsigned(context, eRegisterKindLLDB, arm64_lldb::gpr_lr, x30)) return false; } break; @@ -1159,7 +1152,7 @@ int32_t offset = llvm::SignExtend64<21>(Bits32(opcode, 23, 5) << 2); const uint64_t operand = ReadRegisterUnsigned( - eRegisterKindDWARF, arm64_dwarf::x0 + t, 0, &success); + eRegisterKindLLDB, arm64_lldb::gpr_x0 + t, 0, &success); if (!success) return false; @@ -1195,7 +1188,7 @@ int64_t offset = llvm::SignExtend64<16>(Bits32(opcode, 18, 5) << 2); const uint64_t operand = ReadRegisterUnsigned( - eRegisterKindDWARF, arm64_dwarf::x0 + t, 0, &success); + eRegisterKindLLDB, arm64_lldb::gpr_x0 + t, 0, &success); if (!success) return false; Index: source/Plugins/Process/Utility/RegisterContextDarwin_arm64.cpp =================================================================== --- source/Plugins/Process/Utility/RegisterContextDarwin_arm64.cpp +++ source/Plugins/Process/Utility/RegisterContextDarwin_arm64.cpp @@ -84,23 +84,39 @@ // General purpose registers static uint32_t g_gpr_regnums[] = { - gpr_x0, gpr_x1, gpr_x2, gpr_x3, gpr_x4, gpr_x5, gpr_x6, - gpr_x7, gpr_x8, gpr_x9, gpr_x10, gpr_x11, gpr_x12, gpr_x13, - gpr_x14, gpr_x15, gpr_x16, gpr_x17, gpr_x18, gpr_x19, gpr_x20, - gpr_x21, gpr_x22, gpr_x23, gpr_x24, gpr_x25, gpr_x26, gpr_x27, - gpr_x28, gpr_fp, gpr_lr, gpr_sp, gpr_pc, gpr_cpsr}; + arm64_lldb::gpr_x0, arm64_lldb::gpr_x1, arm64_lldb::gpr_x2, + arm64_lldb::gpr_x3, arm64_lldb::gpr_x4, arm64_lldb::gpr_x5, + arm64_lldb::gpr_x6, arm64_lldb::gpr_x7, arm64_lldb::gpr_x8, + arm64_lldb::gpr_x9, arm64_lldb::gpr_x10, arm64_lldb::gpr_x11, + arm64_lldb::gpr_x12, arm64_lldb::gpr_x13, arm64_lldb::gpr_x14, + arm64_lldb::gpr_x15, arm64_lldb::gpr_x16, arm64_lldb::gpr_x17, + arm64_lldb::gpr_x18, arm64_lldb::gpr_x19, arm64_lldb::gpr_x20, + arm64_lldb::gpr_x21, arm64_lldb::gpr_x22, arm64_lldb::gpr_x23, + arm64_lldb::gpr_x24, arm64_lldb::gpr_x25, arm64_lldb::gpr_x26, + arm64_lldb::gpr_x27, arm64_lldb::gpr_x28, arm64_lldb::gpr_fp, + arm64_lldb::gpr_lr, arm64_lldb::gpr_sp, arm64_lldb::gpr_pc, + arm64_lldb::gpr_cpsr, +}; // Floating point registers static uint32_t g_fpu_regnums[] = { - fpu_v0, fpu_v1, fpu_v2, fpu_v3, fpu_v4, fpu_v5, fpu_v6, - fpu_v7, fpu_v8, fpu_v9, fpu_v10, fpu_v11, fpu_v12, fpu_v13, - fpu_v14, fpu_v15, fpu_v16, fpu_v17, fpu_v18, fpu_v19, fpu_v20, - fpu_v21, fpu_v22, fpu_v23, fpu_v24, fpu_v25, fpu_v26, fpu_v27, - fpu_v28, fpu_v29, fpu_v30, fpu_v31, fpu_fpsr, fpu_fpcr}; + arm64_lldb::fpu_v0, arm64_lldb::fpu_v1, arm64_lldb::fpu_v2, + arm64_lldb::fpu_v3, arm64_lldb::fpu_v4, arm64_lldb::fpu_v5, + arm64_lldb::fpu_v6, arm64_lldb::fpu_v7, arm64_lldb::fpu_v8, + arm64_lldb::fpu_v9, arm64_lldb::fpu_v10, arm64_lldb::fpu_v11, + arm64_lldb::fpu_v12, arm64_lldb::fpu_v13, arm64_lldb::fpu_v14, + arm64_lldb::fpu_v15, arm64_lldb::fpu_v16, arm64_lldb::fpu_v17, + arm64_lldb::fpu_v18, arm64_lldb::fpu_v19, arm64_lldb::fpu_v20, + arm64_lldb::fpu_v21, arm64_lldb::fpu_v22, arm64_lldb::fpu_v23, + arm64_lldb::fpu_v24, arm64_lldb::fpu_v25, arm64_lldb::fpu_v26, + arm64_lldb::fpu_v27, arm64_lldb::fpu_v28, arm64_lldb::fpu_v29, + arm64_lldb::fpu_v30, arm64_lldb::fpu_v31, +}; // Exception registers -static uint32_t g_exc_regnums[] = {exc_far, exc_esr, exc_exception}; +static uint32_t g_exc_regnums[] = {arm64_lldb::exc_far, arm64_lldb::exc_esr, + arm64_lldb::exc_exception}; static size_t k_num_register_infos = llvm::array_lengthof(g_register_infos_arm64_le); @@ -123,14 +139,14 @@ } size_t RegisterContextDarwin_arm64::GetRegisterCount() { - assert(k_num_register_infos == k_num_registers); - return k_num_registers; + assert(k_num_register_infos == arm64_lldb::k_num_registers); + return arm64_lldb::k_num_registers; } const RegisterInfo * RegisterContextDarwin_arm64::GetRegisterInfoAtIndex(size_t reg) { - assert(k_num_register_infos == k_num_registers); - if (reg < k_num_registers) + assert(k_num_register_infos == arm64_lldb::k_num_registers); + if (reg < arm64_lldb::k_num_registers) return &g_register_infos_arm64_le[reg]; return NULL; } @@ -176,11 +192,11 @@ // Register information definitions for arm64 //---------------------------------------------------------------------- int RegisterContextDarwin_arm64::GetSetForNativeRegNum(int reg) { - if (reg < fpu_v0) + if (reg < arm64_lldb::fpu_v0) return GPRRegSet; - else if (reg < exc_far) + else if (reg < arm64_lldb::exc_far) return FPURegSet; - else if (reg < k_num_registers) + else if (reg < arm64_lldb::k_num_registers) return EXCRegSet; return -1; } @@ -317,75 +333,76 @@ return false; switch (reg) { - case gpr_x0: - case gpr_x1: - case gpr_x2: - case gpr_x3: - case gpr_x4: - case gpr_x5: - case gpr_x6: - case gpr_x7: - case gpr_x8: - case gpr_x9: - case gpr_x10: - case gpr_x11: - case gpr_x12: - case gpr_x13: - case gpr_x14: - case gpr_x15: - case gpr_x16: - case gpr_x17: - case gpr_x18: - case gpr_x19: - case gpr_x20: - case gpr_x21: - case gpr_x22: - case gpr_x23: - case gpr_x24: - case gpr_x25: - case gpr_x26: - case gpr_x27: - case gpr_x28: - case gpr_fp: - case gpr_sp: - case gpr_lr: - case gpr_pc: - case gpr_cpsr: - value.SetUInt64(gpr.x[reg - gpr_x0]); + case arm64_lldb::gpr_x0: + case arm64_lldb::gpr_x1: + case arm64_lldb::gpr_x2: + case arm64_lldb::gpr_x3: + case arm64_lldb::gpr_x4: + case arm64_lldb::gpr_x5: + case arm64_lldb::gpr_x6: + case arm64_lldb::gpr_x7: + case arm64_lldb::gpr_x8: + case arm64_lldb::gpr_x9: + case arm64_lldb::gpr_x10: + case arm64_lldb::gpr_x11: + case arm64_lldb::gpr_x12: + case arm64_lldb::gpr_x13: + case arm64_lldb::gpr_x14: + case arm64_lldb::gpr_x15: + case arm64_lldb::gpr_x16: + case arm64_lldb::gpr_x17: + case arm64_lldb::gpr_x18: + case arm64_lldb::gpr_x19: + case arm64_lldb::gpr_x20: + case arm64_lldb::gpr_x21: + case arm64_lldb::gpr_x22: + case arm64_lldb::gpr_x23: + case arm64_lldb::gpr_x24: + case arm64_lldb::gpr_x25: + case arm64_lldb::gpr_x26: + case arm64_lldb::gpr_x27: + case arm64_lldb::gpr_x28: + case arm64_lldb::gpr_fp: + case arm64_lldb::gpr_sp: + case arm64_lldb::gpr_lr: + case arm64_lldb::gpr_pc: + case arm64_lldb::gpr_cpsr: + value.SetUInt64(gpr.x[reg - arm64_lldb::gpr_x0]); break; - case gpr_w0: - case gpr_w1: - case gpr_w2: - case gpr_w3: - case gpr_w4: - case gpr_w5: - case gpr_w6: - case gpr_w7: - case gpr_w8: - case gpr_w9: - case gpr_w10: - case gpr_w11: - case gpr_w12: - case gpr_w13: - case gpr_w14: - case gpr_w15: - case gpr_w16: - case gpr_w17: - case gpr_w18: - case gpr_w19: - case gpr_w20: - case gpr_w21: - case gpr_w22: - case gpr_w23: - case gpr_w24: - case gpr_w25: - case gpr_w26: - case gpr_w27: - case gpr_w28: { + case arm64_lldb::gpr_w0: + case arm64_lldb::gpr_w1: + case arm64_lldb::gpr_w2: + case arm64_lldb::gpr_w3: + case arm64_lldb::gpr_w4: + case arm64_lldb::gpr_w5: + case arm64_lldb::gpr_w6: + case arm64_lldb::gpr_w7: + case arm64_lldb::gpr_w8: + case arm64_lldb::gpr_w9: + case arm64_lldb::gpr_w10: + case arm64_lldb::gpr_w11: + case arm64_lldb::gpr_w12: + case arm64_lldb::gpr_w13: + case arm64_lldb::gpr_w14: + case arm64_lldb::gpr_w15: + case arm64_lldb::gpr_w16: + case arm64_lldb::gpr_w17: + case arm64_lldb::gpr_w18: + case arm64_lldb::gpr_w19: + case arm64_lldb::gpr_w20: + case arm64_lldb::gpr_w21: + case arm64_lldb::gpr_w22: + case arm64_lldb::gpr_w23: + case arm64_lldb::gpr_w24: + case arm64_lldb::gpr_w25: + case arm64_lldb::gpr_w26: + case arm64_lldb::gpr_w27: + case arm64_lldb::gpr_w28: { ProcessSP process_sp(m_thread.GetProcess()); if (process_sp.get()) { - DataExtractor regdata(&gpr.x[reg - gpr_w0], 8, process_sp->GetByteOrder(), + DataExtractor regdata(&gpr.x[reg - arm64_lldb::gpr_w0], 8, + process_sp->GetByteOrder(), process_sp->GetAddressByteSize()); offset_t offset = 0; uint64_t retval = regdata.GetMaxU64(&offset, 8); @@ -394,77 +411,78 @@ } } break; - case fpu_v0: - case fpu_v1: - case fpu_v2: - case fpu_v3: - case fpu_v4: - case fpu_v5: - case fpu_v6: - case fpu_v7: - case fpu_v8: - case fpu_v9: - case fpu_v10: - case fpu_v11: - case fpu_v12: - case fpu_v13: - case fpu_v14: - case fpu_v15: - case fpu_v16: - case fpu_v17: - case fpu_v18: - case fpu_v19: - case fpu_v20: - case fpu_v21: - case fpu_v22: - case fpu_v23: - case fpu_v24: - case fpu_v25: - case fpu_v26: - case fpu_v27: - case fpu_v28: - case fpu_v29: - case fpu_v30: - case fpu_v31: + case arm64_lldb::fpu_v0: + case arm64_lldb::fpu_v1: + case arm64_lldb::fpu_v2: + case arm64_lldb::fpu_v3: + case arm64_lldb::fpu_v4: + case arm64_lldb::fpu_v5: + case arm64_lldb::fpu_v6: + case arm64_lldb::fpu_v7: + case arm64_lldb::fpu_v8: + case arm64_lldb::fpu_v9: + case arm64_lldb::fpu_v10: + case arm64_lldb::fpu_v11: + case arm64_lldb::fpu_v12: + case arm64_lldb::fpu_v13: + case arm64_lldb::fpu_v14: + case arm64_lldb::fpu_v15: + case arm64_lldb::fpu_v16: + case arm64_lldb::fpu_v17: + case arm64_lldb::fpu_v18: + case arm64_lldb::fpu_v19: + case arm64_lldb::fpu_v20: + case arm64_lldb::fpu_v21: + case arm64_lldb::fpu_v22: + case arm64_lldb::fpu_v23: + case arm64_lldb::fpu_v24: + case arm64_lldb::fpu_v25: + case arm64_lldb::fpu_v26: + case arm64_lldb::fpu_v27: + case arm64_lldb::fpu_v28: + case arm64_lldb::fpu_v29: + case arm64_lldb::fpu_v30: + case arm64_lldb::fpu_v31: value.SetBytes(fpu.v[reg].bytes, reg_info->byte_size, endian::InlHostByteOrder()); break; - case fpu_s0: - case fpu_s1: - case fpu_s2: - case fpu_s3: - case fpu_s4: - case fpu_s5: - case fpu_s6: - case fpu_s7: - case fpu_s8: - case fpu_s9: - case fpu_s10: - case fpu_s11: - case fpu_s12: - case fpu_s13: - case fpu_s14: - case fpu_s15: - case fpu_s16: - case fpu_s17: - case fpu_s18: - case fpu_s19: - case fpu_s20: - case fpu_s21: - case fpu_s22: - case fpu_s23: - case fpu_s24: - case fpu_s25: - case fpu_s26: - case fpu_s27: - case fpu_s28: - case fpu_s29: - case fpu_s30: - case fpu_s31: { + case arm64_lldb::fpu_s0: + case arm64_lldb::fpu_s1: + case arm64_lldb::fpu_s2: + case arm64_lldb::fpu_s3: + case arm64_lldb::fpu_s4: + case arm64_lldb::fpu_s5: + case arm64_lldb::fpu_s6: + case arm64_lldb::fpu_s7: + case arm64_lldb::fpu_s8: + case arm64_lldb::fpu_s9: + case arm64_lldb::fpu_s10: + case arm64_lldb::fpu_s11: + case arm64_lldb::fpu_s12: + case arm64_lldb::fpu_s13: + case arm64_lldb::fpu_s14: + case arm64_lldb::fpu_s15: + case arm64_lldb::fpu_s16: + case arm64_lldb::fpu_s17: + case arm64_lldb::fpu_s18: + case arm64_lldb::fpu_s19: + case arm64_lldb::fpu_s20: + case arm64_lldb::fpu_s21: + case arm64_lldb::fpu_s22: + case arm64_lldb::fpu_s23: + case arm64_lldb::fpu_s24: + case arm64_lldb::fpu_s25: + case arm64_lldb::fpu_s26: + case arm64_lldb::fpu_s27: + case arm64_lldb::fpu_s28: + case arm64_lldb::fpu_s29: + case arm64_lldb::fpu_s30: + case arm64_lldb::fpu_s31: { ProcessSP process_sp(m_thread.GetProcess()); if (process_sp.get()) { - DataExtractor regdata(&fpu.v[reg - fpu_s0], 4, process_sp->GetByteOrder(), + DataExtractor regdata(&fpu.v[reg - arm64_lldb::fpu_s0], 4, + process_sp->GetByteOrder(), process_sp->GetAddressByteSize()); offset_t offset = 0; value.SetFloat(regdata.GetFloat(&offset)); @@ -471,41 +489,42 @@ } } break; - case fpu_d0: - case fpu_d1: - case fpu_d2: - case fpu_d3: - case fpu_d4: - case fpu_d5: - case fpu_d6: - case fpu_d7: - case fpu_d8: - case fpu_d9: - case fpu_d10: - case fpu_d11: - case fpu_d12: - case fpu_d13: - case fpu_d14: - case fpu_d15: - case fpu_d16: - case fpu_d17: - case fpu_d18: - case fpu_d19: - case fpu_d20: - case fpu_d21: - case fpu_d22: - case fpu_d23: - case fpu_d24: - case fpu_d25: - case fpu_d26: - case fpu_d27: - case fpu_d28: - case fpu_d29: - case fpu_d30: - case fpu_d31: { + case arm64_lldb::fpu_d0: + case arm64_lldb::fpu_d1: + case arm64_lldb::fpu_d2: + case arm64_lldb::fpu_d3: + case arm64_lldb::fpu_d4: + case arm64_lldb::fpu_d5: + case arm64_lldb::fpu_d6: + case arm64_lldb::fpu_d7: + case arm64_lldb::fpu_d8: + case arm64_lldb::fpu_d9: + case arm64_lldb::fpu_d10: + case arm64_lldb::fpu_d11: + case arm64_lldb::fpu_d12: + case arm64_lldb::fpu_d13: + case arm64_lldb::fpu_d14: + case arm64_lldb::fpu_d15: + case arm64_lldb::fpu_d16: + case arm64_lldb::fpu_d17: + case arm64_lldb::fpu_d18: + case arm64_lldb::fpu_d19: + case arm64_lldb::fpu_d20: + case arm64_lldb::fpu_d21: + case arm64_lldb::fpu_d22: + case arm64_lldb::fpu_d23: + case arm64_lldb::fpu_d24: + case arm64_lldb::fpu_d25: + case arm64_lldb::fpu_d26: + case arm64_lldb::fpu_d27: + case arm64_lldb::fpu_d28: + case arm64_lldb::fpu_d29: + case arm64_lldb::fpu_d30: + case arm64_lldb::fpu_d31: { ProcessSP process_sp(m_thread.GetProcess()); if (process_sp.get()) { - DataExtractor regdata(&fpu.v[reg - fpu_s0], 8, process_sp->GetByteOrder(), + DataExtractor regdata(&fpu.v[reg - arm64_lldb::fpu_s0], 8, + process_sp->GetByteOrder(), process_sp->GetAddressByteSize()); offset_t offset = 0; value.SetDouble(regdata.GetDouble(&offset)); @@ -512,21 +531,21 @@ } } break; - case fpu_fpsr: + case arm64_lldb::fpu_fpsr: value.SetUInt32(fpu.fpsr); break; - case fpu_fpcr: + case arm64_lldb::fpu_fpcr: value.SetUInt32(fpu.fpcr); break; - case exc_exception: + case arm64_lldb::exc_exception: value.SetUInt32(exc.exception); break; - case exc_esr: + case arm64_lldb::exc_esr: value.SetUInt32(exc.esr); break; - case exc_far: + case arm64_lldb::exc_far: value.SetUInt64(exc.far); break; @@ -549,93 +568,93 @@ return false; switch (reg) { - case gpr_x0: - case gpr_x1: - case gpr_x2: - case gpr_x3: - case gpr_x4: - case gpr_x5: - case gpr_x6: - case gpr_x7: - case gpr_x8: - case gpr_x9: - case gpr_x10: - case gpr_x11: - case gpr_x12: - case gpr_x13: - case gpr_x14: - case gpr_x15: - case gpr_x16: - case gpr_x17: - case gpr_x18: - case gpr_x19: - case gpr_x20: - case gpr_x21: - case gpr_x22: - case gpr_x23: - case gpr_x24: - case gpr_x25: - case gpr_x26: - case gpr_x27: - case gpr_x28: - case gpr_fp: - case gpr_sp: - case gpr_lr: - case gpr_pc: - case gpr_cpsr: - gpr.x[reg - gpr_x0] = value.GetAsUInt64(); + case arm64_lldb::gpr_x0: + case arm64_lldb::gpr_x1: + case arm64_lldb::gpr_x2: + case arm64_lldb::gpr_x3: + case arm64_lldb::gpr_x4: + case arm64_lldb::gpr_x5: + case arm64_lldb::gpr_x6: + case arm64_lldb::gpr_x7: + case arm64_lldb::gpr_x8: + case arm64_lldb::gpr_x9: + case arm64_lldb::gpr_x10: + case arm64_lldb::gpr_x11: + case arm64_lldb::gpr_x12: + case arm64_lldb::gpr_x13: + case arm64_lldb::gpr_x14: + case arm64_lldb::gpr_x15: + case arm64_lldb::gpr_x16: + case arm64_lldb::gpr_x17: + case arm64_lldb::gpr_x18: + case arm64_lldb::gpr_x19: + case arm64_lldb::gpr_x20: + case arm64_lldb::gpr_x21: + case arm64_lldb::gpr_x22: + case arm64_lldb::gpr_x23: + case arm64_lldb::gpr_x24: + case arm64_lldb::gpr_x25: + case arm64_lldb::gpr_x26: + case arm64_lldb::gpr_x27: + case arm64_lldb::gpr_x28: + case arm64_lldb::gpr_fp: + case arm64_lldb::gpr_sp: + case arm64_lldb::gpr_lr: + case arm64_lldb::gpr_pc: + case arm64_lldb::gpr_cpsr: + gpr.x[reg - arm64_lldb::gpr_x0] = value.GetAsUInt64(); break; - case fpu_v0: - case fpu_v1: - case fpu_v2: - case fpu_v3: - case fpu_v4: - case fpu_v5: - case fpu_v6: - case fpu_v7: - case fpu_v8: - case fpu_v9: - case fpu_v10: - case fpu_v11: - case fpu_v12: - case fpu_v13: - case fpu_v14: - case fpu_v15: - case fpu_v16: - case fpu_v17: - case fpu_v18: - case fpu_v19: - case fpu_v20: - case fpu_v21: - case fpu_v22: - case fpu_v23: - case fpu_v24: - case fpu_v25: - case fpu_v26: - case fpu_v27: - case fpu_v28: - case fpu_v29: - case fpu_v30: - case fpu_v31: + case arm64_lldb::fpu_v0: + case arm64_lldb::fpu_v1: + case arm64_lldb::fpu_v2: + case arm64_lldb::fpu_v3: + case arm64_lldb::fpu_v4: + case arm64_lldb::fpu_v5: + case arm64_lldb::fpu_v6: + case arm64_lldb::fpu_v7: + case arm64_lldb::fpu_v8: + case arm64_lldb::fpu_v9: + case arm64_lldb::fpu_v10: + case arm64_lldb::fpu_v11: + case arm64_lldb::fpu_v12: + case arm64_lldb::fpu_v13: + case arm64_lldb::fpu_v14: + case arm64_lldb::fpu_v15: + case arm64_lldb::fpu_v16: + case arm64_lldb::fpu_v17: + case arm64_lldb::fpu_v18: + case arm64_lldb::fpu_v19: + case arm64_lldb::fpu_v20: + case arm64_lldb::fpu_v21: + case arm64_lldb::fpu_v22: + case arm64_lldb::fpu_v23: + case arm64_lldb::fpu_v24: + case arm64_lldb::fpu_v25: + case arm64_lldb::fpu_v26: + case arm64_lldb::fpu_v27: + case arm64_lldb::fpu_v28: + case arm64_lldb::fpu_v29: + case arm64_lldb::fpu_v30: + case arm64_lldb::fpu_v31: ::memcpy(fpu.v[reg].bytes, value.GetBytes(), value.GetByteSize()); break; - case fpu_fpsr: + case arm64_lldb::fpu_fpsr: fpu.fpsr = value.GetAsUInt32(); break; - case fpu_fpcr: + case arm64_lldb::fpu_fpcr: fpu.fpcr = value.GetAsUInt32(); break; - case exc_exception: + case arm64_lldb::exc_exception: exc.exception = value.GetAsUInt32(); break; - case exc_esr: + case arm64_lldb::exc_esr: exc.esr = value.GetAsUInt32(); break; - case exc_far: + case arm64_lldb::exc_far: exc.far = value.GetAsUInt64(); break; @@ -691,15 +710,15 @@ if (kind == eRegisterKindGeneric) { switch (reg) { case LLDB_REGNUM_GENERIC_PC: - return gpr_pc; + return arm64_lldb::gpr_pc; case LLDB_REGNUM_GENERIC_SP: - return gpr_sp; + return arm64_lldb::gpr_sp; case LLDB_REGNUM_GENERIC_FP: - return gpr_fp; + return arm64_lldb::gpr_fp; case LLDB_REGNUM_GENERIC_RA: - return gpr_lr; + return arm64_lldb::gpr_lr; case LLDB_REGNUM_GENERIC_FLAGS: - return gpr_cpsr; + return arm64_lldb::gpr_cpsr; default: break; } @@ -706,139 +725,139 @@ } else if (kind == eRegisterKindDWARF) { switch (reg) { case arm64_dwarf::x0: - return gpr_x0; + return arm64_lldb::gpr_x0; case arm64_dwarf::x1: - return gpr_x1; + return arm64_lldb::gpr_x1; case arm64_dwarf::x2: - return gpr_x2; + return arm64_lldb::gpr_x2; case arm64_dwarf::x3: - return gpr_x3; + return arm64_lldb::gpr_x3; case arm64_dwarf::x4: - return gpr_x4; + return arm64_lldb::gpr_x4; case arm64_dwarf::x5: - return gpr_x5; + return arm64_lldb::gpr_x5; case arm64_dwarf::x6: - return gpr_x6; + return arm64_lldb::gpr_x6; case arm64_dwarf::x7: - return gpr_x7; + return arm64_lldb::gpr_x7; case arm64_dwarf::x8: - return gpr_x8; + return arm64_lldb::gpr_x8; case arm64_dwarf::x9: - return gpr_x9; + return arm64_lldb::gpr_x9; case arm64_dwarf::x10: - return gpr_x10; + return arm64_lldb::gpr_x10; case arm64_dwarf::x11: - return gpr_x11; + return arm64_lldb::gpr_x11; case arm64_dwarf::x12: - return gpr_x12; + return arm64_lldb::gpr_x12; case arm64_dwarf::x13: - return gpr_x13; + return arm64_lldb::gpr_x13; case arm64_dwarf::x14: - return gpr_x14; + return arm64_lldb::gpr_x14; case arm64_dwarf::x15: - return gpr_x15; + return arm64_lldb::gpr_x15; case arm64_dwarf::x16: - return gpr_x16; + return arm64_lldb::gpr_x16; case arm64_dwarf::x17: - return gpr_x17; + return arm64_lldb::gpr_x17; case arm64_dwarf::x18: - return gpr_x18; + return arm64_lldb::gpr_x18; case arm64_dwarf::x19: - return gpr_x19; + return arm64_lldb::gpr_x19; case arm64_dwarf::x20: - return gpr_x20; + return arm64_lldb::gpr_x20; case arm64_dwarf::x21: - return gpr_x21; + return arm64_lldb::gpr_x21; case arm64_dwarf::x22: - return gpr_x22; + return arm64_lldb::gpr_x22; case arm64_dwarf::x23: - return gpr_x23; + return arm64_lldb::gpr_x23; case arm64_dwarf::x24: - return gpr_x24; + return arm64_lldb::gpr_x24; case arm64_dwarf::x25: - return gpr_x25; + return arm64_lldb::gpr_x25; case arm64_dwarf::x26: - return gpr_x26; + return arm64_lldb::gpr_x26; case arm64_dwarf::x27: - return gpr_x27; + return arm64_lldb::gpr_x27; case arm64_dwarf::x28: - return gpr_x28; + return arm64_lldb::gpr_x28; case arm64_dwarf::fp: - return gpr_fp; + return arm64_lldb::gpr_fp; case arm64_dwarf::sp: - return gpr_sp; + return arm64_lldb::gpr_sp; case arm64_dwarf::lr: - return gpr_lr; + return arm64_lldb::gpr_lr; case arm64_dwarf::pc: - return gpr_pc; + return arm64_lldb::gpr_pc; case arm64_dwarf::cpsr: - return gpr_cpsr; + return arm64_lldb::gpr_cpsr; case arm64_dwarf::v0: - return fpu_v0; + return arm64_lldb::fpu_v0; case arm64_dwarf::v1: - return fpu_v1; + return arm64_lldb::fpu_v1; case arm64_dwarf::v2: - return fpu_v2; + return arm64_lldb::fpu_v2; case arm64_dwarf::v3: - return fpu_v3; + return arm64_lldb::fpu_v3; case arm64_dwarf::v4: - return fpu_v4; + return arm64_lldb::fpu_v4; case arm64_dwarf::v5: - return fpu_v5; + return arm64_lldb::fpu_v5; case arm64_dwarf::v6: - return fpu_v6; + return arm64_lldb::fpu_v6; case arm64_dwarf::v7: - return fpu_v7; + return arm64_lldb::fpu_v7; case arm64_dwarf::v8: - return fpu_v8; + return arm64_lldb::fpu_v8; case arm64_dwarf::v9: - return fpu_v9; + return arm64_lldb::fpu_v9; case arm64_dwarf::v10: - return fpu_v10; + return arm64_lldb::fpu_v10; case arm64_dwarf::v11: - return fpu_v11; + return arm64_lldb::fpu_v11; case arm64_dwarf::v12: - return fpu_v12; + return arm64_lldb::fpu_v12; case arm64_dwarf::v13: - return fpu_v13; + return arm64_lldb::fpu_v13; case arm64_dwarf::v14: - return fpu_v14; + return arm64_lldb::fpu_v14; case arm64_dwarf::v15: - return fpu_v15; + return arm64_lldb::fpu_v15; case arm64_dwarf::v16: - return fpu_v16; + return arm64_lldb::fpu_v16; case arm64_dwarf::v17: - return fpu_v17; + return arm64_lldb::fpu_v17; case arm64_dwarf::v18: - return fpu_v18; + return arm64_lldb::fpu_v18; case arm64_dwarf::v19: - return fpu_v19; + return arm64_lldb::fpu_v19; case arm64_dwarf::v20: - return fpu_v20; + return arm64_lldb::fpu_v20; case arm64_dwarf::v21: - return fpu_v21; + return arm64_lldb::fpu_v21; case arm64_dwarf::v22: - return fpu_v22; + return arm64_lldb::fpu_v22; case arm64_dwarf::v23: - return fpu_v23; + return arm64_lldb::fpu_v23; case arm64_dwarf::v24: - return fpu_v24; + return arm64_lldb::fpu_v24; case arm64_dwarf::v25: - return fpu_v25; + return arm64_lldb::fpu_v25; case arm64_dwarf::v26: - return fpu_v26; + return arm64_lldb::fpu_v26; case arm64_dwarf::v27: - return fpu_v27; + return arm64_lldb::fpu_v27; case arm64_dwarf::v28: - return fpu_v28; + return arm64_lldb::fpu_v28; case arm64_dwarf::v29: - return fpu_v29; + return arm64_lldb::fpu_v29; case arm64_dwarf::v30: - return fpu_v30; + return arm64_lldb::fpu_v30; case arm64_dwarf::v31: - return fpu_v31; + return arm64_lldb::fpu_v31; default: break; @@ -846,73 +865,73 @@ } else if (kind == eRegisterKindEHFrame) { switch (reg) { case arm64_ehframe::x0: - return gpr_x0; + return arm64_lldb::gpr_x0; case arm64_ehframe::x1: - return gpr_x1; + return arm64_lldb::gpr_x1; case arm64_ehframe::x2: - return gpr_x2; + return arm64_lldb::gpr_x2; case arm64_ehframe::x3: - return gpr_x3; + return arm64_lldb::gpr_x3; case arm64_ehframe::x4: - return gpr_x4; + return arm64_lldb::gpr_x4; case arm64_ehframe::x5: - return gpr_x5; + return arm64_lldb::gpr_x5; case arm64_ehframe::x6: - return gpr_x6; + return arm64_lldb::gpr_x6; case arm64_ehframe::x7: - return gpr_x7; + return arm64_lldb::gpr_x7; case arm64_ehframe::x8: - return gpr_x8; + return arm64_lldb::gpr_x8; case arm64_ehframe::x9: - return gpr_x9; + return arm64_lldb::gpr_x9; case arm64_ehframe::x10: - return gpr_x10; + return arm64_lldb::gpr_x10; case arm64_ehframe::x11: - return gpr_x11; + return arm64_lldb::gpr_x11; case arm64_ehframe::x12: - return gpr_x12; + return arm64_lldb::gpr_x12; case arm64_ehframe::x13: - return gpr_x13; + return arm64_lldb::gpr_x13; case arm64_ehframe::x14: - return gpr_x14; + return arm64_lldb::gpr_x14; case arm64_ehframe::x15: - return gpr_x15; + return arm64_lldb::gpr_x15; case arm64_ehframe::x16: - return gpr_x16; + return arm64_lldb::gpr_x16; case arm64_ehframe::x17: - return gpr_x17; + return arm64_lldb::gpr_x17; case arm64_ehframe::x18: - return gpr_x18; + return arm64_lldb::gpr_x18; case arm64_ehframe::x19: - return gpr_x19; + return arm64_lldb::gpr_x19; case arm64_ehframe::x20: - return gpr_x20; + return arm64_lldb::gpr_x20; case arm64_ehframe::x21: - return gpr_x21; + return arm64_lldb::gpr_x21; case arm64_ehframe::x22: - return gpr_x22; + return arm64_lldb::gpr_x22; case arm64_ehframe::x23: - return gpr_x23; + return arm64_lldb::gpr_x23; case arm64_ehframe::x24: - return gpr_x24; + return arm64_lldb::gpr_x24; case arm64_ehframe::x25: - return gpr_x25; + return arm64_lldb::gpr_x25; case arm64_ehframe::x26: - return gpr_x26; + return arm64_lldb::gpr_x26; case arm64_ehframe::x27: - return gpr_x27; + return arm64_lldb::gpr_x27; case arm64_ehframe::x28: - return gpr_x28; + return arm64_lldb::gpr_x28; case arm64_ehframe::fp: - return gpr_fp; + return arm64_lldb::gpr_fp; case arm64_ehframe::sp: - return gpr_sp; + return arm64_lldb::gpr_sp; case arm64_ehframe::lr: - return gpr_lr; + return arm64_lldb::gpr_lr; case arm64_ehframe::pc: - return gpr_pc; + return arm64_lldb::gpr_pc; case arm64_ehframe::cpsr: - return gpr_cpsr; + return arm64_lldb::gpr_cpsr; } } else if (kind == eRegisterKindLLDB) { return reg; Index: source/Plugins/Process/Utility/RegisterContextFreeBSD_arm64.cpp =================================================================== --- source/Plugins/Process/Utility/RegisterContextFreeBSD_arm64.cpp +++ source/Plugins/Process/Utility/RegisterContextFreeBSD_arm64.cpp @@ -38,7 +38,7 @@ DBG_OFFSET_NAME(reg[i]), lldb::eEncodingUint, lldb::eFormatHex, \ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ - dbg_##reg##i }, \ + arm64_lldb::dbg_##reg##i }, \ NULL, NULL, NULL, 0 #define REG_CONTEXT_SIZE \ (sizeof(RegisterContextFreeBSD_arm64::GPR) + \ Index: source/Plugins/Process/Utility/RegisterContextLinux_arm64.cpp =================================================================== --- source/Plugins/Process/Utility/RegisterContextLinux_arm64.cpp +++ source/Plugins/Process/Utility/RegisterContextLinux_arm64.cpp @@ -42,7 +42,7 @@ DBG_OFFSET_NAME(reg[i]), lldb::eEncodingUint, lldb::eFormatHex, \ {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, \ - dbg_##reg##i }, \ + arm64_lldb::dbg_##reg##i }, \ NULL, NULL, NULL, 0 #define REG_CONTEXT_SIZE \ (sizeof(RegisterContextLinux_arm64::GPR) + \ Index: source/Plugins/Process/Utility/RegisterInfos_arm64.h =================================================================== --- source/Plugins/Process/Utility/RegisterInfos_arm64.h +++ source/Plugins/Process/Utility/RegisterInfos_arm64.h @@ -7,8 +7,6 @@ // //===----------------------------------------------------------------------===// -#ifdef DECLARE_REGISTER_INFOS_ARM64_STRUCT - // C Includes #include @@ -17,11 +15,15 @@ // Project includes #include "lldb/lldb-defines.h" #include "lldb/lldb-enumerations.h" +#include "lldb/lldb-private-types.h" #include "lldb/lldb-private.h" #include "Utility/ARM64_DWARF_Registers.h" +#include "Utility/ARM64_LLDB_Registers.h" #include "Utility/ARM64_ehframe_Registers.h" +#ifdef DECLARE_REGISTER_INFOS_ARM64_STRUCT + #ifndef GPR_OFFSET #error GPR_OFFSET must be defined before including this header file #endif @@ -55,412 +57,280 @@ #define FPU_S_PSEUDO_REG_ENDIAN_OFFSET 0 #define FPU_D_PSEUDO_REG_ENDIAN_OFFSET 0 -enum { - gpr_x0 = 0, - gpr_x1, - gpr_x2, - gpr_x3, - gpr_x4, - gpr_x5, - gpr_x6, - gpr_x7, - gpr_x8, - gpr_x9, - gpr_x10, - gpr_x11, - gpr_x12, - gpr_x13, - gpr_x14, - gpr_x15, - gpr_x16, - gpr_x17, - gpr_x18, - gpr_x19, - gpr_x20, - gpr_x21, - gpr_x22, - gpr_x23, - gpr_x24, - gpr_x25, - gpr_x26, - gpr_x27, - gpr_x28, - gpr_x29 = 29, - gpr_fp = gpr_x29, - gpr_x30 = 30, - gpr_lr = gpr_x30, - gpr_ra = gpr_x30, - gpr_x31 = 31, - gpr_sp = gpr_x31, - gpr_pc = 32, - gpr_cpsr, +static uint32_t g_x0_contains[] = {arm64_lldb::gpr_w0, LLDB_INVALID_REGNUM}; +static uint32_t g_x1_contains[] = {arm64_lldb::gpr_w1, LLDB_INVALID_REGNUM}; +static uint32_t g_x2_contains[] = {arm64_lldb::gpr_w2, LLDB_INVALID_REGNUM}; +static uint32_t g_x3_contains[] = {arm64_lldb::gpr_w3, LLDB_INVALID_REGNUM}; +static uint32_t g_x4_contains[] = {arm64_lldb::gpr_w4, LLDB_INVALID_REGNUM}; +static uint32_t g_x5_contains[] = {arm64_lldb::gpr_w5, LLDB_INVALID_REGNUM}; +static uint32_t g_x6_contains[] = {arm64_lldb::gpr_w6, LLDB_INVALID_REGNUM}; +static uint32_t g_x7_contains[] = {arm64_lldb::gpr_w7, LLDB_INVALID_REGNUM}; +static uint32_t g_x8_contains[] = {arm64_lldb::gpr_w8, LLDB_INVALID_REGNUM}; +static uint32_t g_x9_contains[] = {arm64_lldb::gpr_w9, LLDB_INVALID_REGNUM}; +static uint32_t g_x10_contains[] = {arm64_lldb::gpr_w10, LLDB_INVALID_REGNUM}; +static uint32_t g_x11_contains[] = {arm64_lldb::gpr_w11, LLDB_INVALID_REGNUM}; +static uint32_t g_x12_contains[] = {arm64_lldb::gpr_w12, LLDB_INVALID_REGNUM}; +static uint32_t g_x13_contains[] = {arm64_lldb::gpr_w13, LLDB_INVALID_REGNUM}; +static uint32_t g_x14_contains[] = {arm64_lldb::gpr_w14, LLDB_INVALID_REGNUM}; +static uint32_t g_x15_contains[] = {arm64_lldb::gpr_w15, LLDB_INVALID_REGNUM}; +static uint32_t g_x16_contains[] = {arm64_lldb::gpr_w16, LLDB_INVALID_REGNUM}; +static uint32_t g_x17_contains[] = {arm64_lldb::gpr_w17, LLDB_INVALID_REGNUM}; +static uint32_t g_x18_contains[] = {arm64_lldb::gpr_w18, LLDB_INVALID_REGNUM}; +static uint32_t g_x19_contains[] = {arm64_lldb::gpr_w19, LLDB_INVALID_REGNUM}; +static uint32_t g_x20_contains[] = {arm64_lldb::gpr_w20, LLDB_INVALID_REGNUM}; +static uint32_t g_x21_contains[] = {arm64_lldb::gpr_w21, LLDB_INVALID_REGNUM}; +static uint32_t g_x22_contains[] = {arm64_lldb::gpr_w22, LLDB_INVALID_REGNUM}; +static uint32_t g_x23_contains[] = {arm64_lldb::gpr_w23, LLDB_INVALID_REGNUM}; +static uint32_t g_x24_contains[] = {arm64_lldb::gpr_w24, LLDB_INVALID_REGNUM}; +static uint32_t g_x25_contains[] = {arm64_lldb::gpr_w25, LLDB_INVALID_REGNUM}; +static uint32_t g_x26_contains[] = {arm64_lldb::gpr_w26, LLDB_INVALID_REGNUM}; +static uint32_t g_x27_contains[] = {arm64_lldb::gpr_w27, LLDB_INVALID_REGNUM}; +static uint32_t g_x28_contains[] = {arm64_lldb::gpr_w28, LLDB_INVALID_REGNUM}; - gpr_w0, - gpr_w1, - gpr_w2, - gpr_w3, - gpr_w4, - gpr_w5, - gpr_w6, - gpr_w7, - gpr_w8, - gpr_w9, - gpr_w10, - gpr_w11, - gpr_w12, - gpr_w13, - gpr_w14, - gpr_w15, - gpr_w16, - gpr_w17, - gpr_w18, - gpr_w19, - gpr_w20, - gpr_w21, - gpr_w22, - gpr_w23, - gpr_w24, - gpr_w25, - gpr_w26, - gpr_w27, - gpr_w28, +static uint32_t g_w0_invalidates[] = {arm64_lldb::gpr_x0, LLDB_INVALID_REGNUM}; +static uint32_t g_w1_invalidates[] = {arm64_lldb::gpr_x1, LLDB_INVALID_REGNUM}; +static uint32_t g_w2_invalidates[] = {arm64_lldb::gpr_x2, LLDB_INVALID_REGNUM}; +static uint32_t g_w3_invalidates[] = {arm64_lldb::gpr_x3, LLDB_INVALID_REGNUM}; +static uint32_t g_w4_invalidates[] = {arm64_lldb::gpr_x4, LLDB_INVALID_REGNUM}; +static uint32_t g_w5_invalidates[] = {arm64_lldb::gpr_x5, LLDB_INVALID_REGNUM}; +static uint32_t g_w6_invalidates[] = {arm64_lldb::gpr_x6, LLDB_INVALID_REGNUM}; +static uint32_t g_w7_invalidates[] = {arm64_lldb::gpr_x7, LLDB_INVALID_REGNUM}; +static uint32_t g_w8_invalidates[] = {arm64_lldb::gpr_x8, LLDB_INVALID_REGNUM}; +static uint32_t g_w9_invalidates[] = {arm64_lldb::gpr_x9, LLDB_INVALID_REGNUM}; +static uint32_t g_w10_invalidates[] = {arm64_lldb::gpr_x10, + LLDB_INVALID_REGNUM}; +static uint32_t g_w11_invalidates[] = {arm64_lldb::gpr_x11, + LLDB_INVALID_REGNUM}; +static uint32_t g_w12_invalidates[] = {arm64_lldb::gpr_x12, + LLDB_INVALID_REGNUM}; +static uint32_t g_w13_invalidates[] = {arm64_lldb::gpr_x13, + LLDB_INVALID_REGNUM}; +static uint32_t g_w14_invalidates[] = {arm64_lldb::gpr_x14, + LLDB_INVALID_REGNUM}; +static uint32_t g_w15_invalidates[] = {arm64_lldb::gpr_x15, + LLDB_INVALID_REGNUM}; +static uint32_t g_w16_invalidates[] = {arm64_lldb::gpr_x16, + LLDB_INVALID_REGNUM}; +static uint32_t g_w17_invalidates[] = {arm64_lldb::gpr_x17, + LLDB_INVALID_REGNUM}; +static uint32_t g_w18_invalidates[] = {arm64_lldb::gpr_x18, + LLDB_INVALID_REGNUM}; +static uint32_t g_w19_invalidates[] = {arm64_lldb::gpr_x19, + LLDB_INVALID_REGNUM}; +static uint32_t g_w20_invalidates[] = {arm64_lldb::gpr_x20, + LLDB_INVALID_REGNUM}; +static uint32_t g_w21_invalidates[] = {arm64_lldb::gpr_x21, + LLDB_INVALID_REGNUM}; +static uint32_t g_w22_invalidates[] = {arm64_lldb::gpr_x22, + LLDB_INVALID_REGNUM}; +static uint32_t g_w23_invalidates[] = {arm64_lldb::gpr_x23, + LLDB_INVALID_REGNUM}; +static uint32_t g_w24_invalidates[] = {arm64_lldb::gpr_x24, + LLDB_INVALID_REGNUM}; +static uint32_t g_w25_invalidates[] = {arm64_lldb::gpr_x25, + LLDB_INVALID_REGNUM}; +static uint32_t g_w26_invalidates[] = {arm64_lldb::gpr_x26, + LLDB_INVALID_REGNUM}; +static uint32_t g_w27_invalidates[] = {arm64_lldb::gpr_x27, + LLDB_INVALID_REGNUM}; +static uint32_t g_w28_invalidates[] = {arm64_lldb::gpr_x28, + LLDB_INVALID_REGNUM}; - fpu_v0, - fpu_v1, - fpu_v2, - fpu_v3, - fpu_v4, - fpu_v5, - fpu_v6, - fpu_v7, - fpu_v8, - fpu_v9, - fpu_v10, - fpu_v11, - fpu_v12, - fpu_v13, - fpu_v14, - fpu_v15, - fpu_v16, - fpu_v17, - fpu_v18, - fpu_v19, - fpu_v20, - fpu_v21, - fpu_v22, - fpu_v23, - fpu_v24, - fpu_v25, - fpu_v26, - fpu_v27, - fpu_v28, - fpu_v29, - fpu_v30, - fpu_v31, +static uint32_t g_v0_contains[] = {arm64_lldb::fpu_s0, arm64_lldb::fpu_d0, + LLDB_INVALID_REGNUM}; +static uint32_t g_v1_contains[] = {arm64_lldb::fpu_s1, arm64_lldb::fpu_d1, + LLDB_INVALID_REGNUM}; +static uint32_t g_v2_contains[] = {arm64_lldb::fpu_s2, arm64_lldb::fpu_d2, + LLDB_INVALID_REGNUM}; +static uint32_t g_v3_contains[] = {arm64_lldb::fpu_s3, arm64_lldb::fpu_d3, + LLDB_INVALID_REGNUM}; +static uint32_t g_v4_contains[] = {arm64_lldb::fpu_s4, arm64_lldb::fpu_d4, + LLDB_INVALID_REGNUM}; +static uint32_t g_v5_contains[] = {arm64_lldb::fpu_s5, arm64_lldb::fpu_d5, + LLDB_INVALID_REGNUM}; +static uint32_t g_v6_contains[] = {arm64_lldb::fpu_s6, arm64_lldb::fpu_d6, + LLDB_INVALID_REGNUM}; +static uint32_t g_v7_contains[] = {arm64_lldb::fpu_s7, arm64_lldb::fpu_d7, + LLDB_INVALID_REGNUM}; +static uint32_t g_v8_contains[] = {arm64_lldb::fpu_s8, arm64_lldb::fpu_d8, + LLDB_INVALID_REGNUM}; +static uint32_t g_v9_contains[] = {arm64_lldb::fpu_s9, arm64_lldb::fpu_d9, + LLDB_INVALID_REGNUM}; +static uint32_t g_v10_contains[] = {arm64_lldb::fpu_s10, arm64_lldb::fpu_d10, + LLDB_INVALID_REGNUM}; +static uint32_t g_v11_contains[] = {arm64_lldb::fpu_s11, arm64_lldb::fpu_d11, + LLDB_INVALID_REGNUM}; +static uint32_t g_v12_contains[] = {arm64_lldb::fpu_s12, arm64_lldb::fpu_d12, + LLDB_INVALID_REGNUM}; +static uint32_t g_v13_contains[] = {arm64_lldb::fpu_s13, arm64_lldb::fpu_d13, + LLDB_INVALID_REGNUM}; +static uint32_t g_v14_contains[] = {arm64_lldb::fpu_s14, arm64_lldb::fpu_d14, + LLDB_INVALID_REGNUM}; +static uint32_t g_v15_contains[] = {arm64_lldb::fpu_s15, arm64_lldb::fpu_d15, + LLDB_INVALID_REGNUM}; +static uint32_t g_v16_contains[] = {arm64_lldb::fpu_s16, arm64_lldb::fpu_d16, + LLDB_INVALID_REGNUM}; +static uint32_t g_v17_contains[] = {arm64_lldb::fpu_s17, arm64_lldb::fpu_d17, + LLDB_INVALID_REGNUM}; +static uint32_t g_v18_contains[] = {arm64_lldb::fpu_s18, arm64_lldb::fpu_d18, + LLDB_INVALID_REGNUM}; +static uint32_t g_v19_contains[] = {arm64_lldb::fpu_s19, arm64_lldb::fpu_d19, + LLDB_INVALID_REGNUM}; +static uint32_t g_v20_contains[] = {arm64_lldb::fpu_s20, arm64_lldb::fpu_d20, + LLDB_INVALID_REGNUM}; +static uint32_t g_v21_contains[] = {arm64_lldb::fpu_s21, arm64_lldb::fpu_d21, + LLDB_INVALID_REGNUM}; +static uint32_t g_v22_contains[] = {arm64_lldb::fpu_s22, arm64_lldb::fpu_d22, + LLDB_INVALID_REGNUM}; +static uint32_t g_v23_contains[] = {arm64_lldb::fpu_s23, arm64_lldb::fpu_d23, + LLDB_INVALID_REGNUM}; +static uint32_t g_v24_contains[] = {arm64_lldb::fpu_s24, arm64_lldb::fpu_d24, + LLDB_INVALID_REGNUM}; +static uint32_t g_v25_contains[] = {arm64_lldb::fpu_s25, arm64_lldb::fpu_d25, + LLDB_INVALID_REGNUM}; +static uint32_t g_v26_contains[] = {arm64_lldb::fpu_s26, arm64_lldb::fpu_d26, + LLDB_INVALID_REGNUM}; +static uint32_t g_v27_contains[] = {arm64_lldb::fpu_s27, arm64_lldb::fpu_d27, + LLDB_INVALID_REGNUM}; +static uint32_t g_v28_contains[] = {arm64_lldb::fpu_s28, arm64_lldb::fpu_d28, + LLDB_INVALID_REGNUM}; +static uint32_t g_v29_contains[] = {arm64_lldb::fpu_s29, arm64_lldb::fpu_d29, + LLDB_INVALID_REGNUM}; +static uint32_t g_v30_contains[] = {arm64_lldb::fpu_s30, arm64_lldb::fpu_d30, + LLDB_INVALID_REGNUM}; +static uint32_t g_v31_contains[] = {arm64_lldb::fpu_s31, arm64_lldb::fpu_d31, + LLDB_INVALID_REGNUM}; - fpu_s0, - fpu_s1, - fpu_s2, - fpu_s3, - fpu_s4, - fpu_s5, - fpu_s6, - fpu_s7, - fpu_s8, - fpu_s9, - fpu_s10, - fpu_s11, - fpu_s12, - fpu_s13, - fpu_s14, - fpu_s15, - fpu_s16, - fpu_s17, - fpu_s18, - fpu_s19, - fpu_s20, - fpu_s21, - fpu_s22, - fpu_s23, - fpu_s24, - fpu_s25, - fpu_s26, - fpu_s27, - fpu_s28, - fpu_s29, - fpu_s30, - fpu_s31, +static uint32_t g_s0_invalidates[] = {arm64_lldb::fpu_v0, arm64_lldb::fpu_d0, + LLDB_INVALID_REGNUM}; +static uint32_t g_s1_invalidates[] = {arm64_lldb::fpu_v1, arm64_lldb::fpu_d1, + LLDB_INVALID_REGNUM}; +static uint32_t g_s2_invalidates[] = {arm64_lldb::fpu_v2, arm64_lldb::fpu_d2, + LLDB_INVALID_REGNUM}; +static uint32_t g_s3_invalidates[] = {arm64_lldb::fpu_v3, arm64_lldb::fpu_d3, + LLDB_INVALID_REGNUM}; +static uint32_t g_s4_invalidates[] = {arm64_lldb::fpu_v4, arm64_lldb::fpu_d4, + LLDB_INVALID_REGNUM}; +static uint32_t g_s5_invalidates[] = {arm64_lldb::fpu_v5, arm64_lldb::fpu_d5, + LLDB_INVALID_REGNUM}; +static uint32_t g_s6_invalidates[] = {arm64_lldb::fpu_v6, arm64_lldb::fpu_d6, + LLDB_INVALID_REGNUM}; +static uint32_t g_s7_invalidates[] = {arm64_lldb::fpu_v7, arm64_lldb::fpu_d7, + LLDB_INVALID_REGNUM}; +static uint32_t g_s8_invalidates[] = {arm64_lldb::fpu_v8, arm64_lldb::fpu_d8, + LLDB_INVALID_REGNUM}; +static uint32_t g_s9_invalidates[] = {arm64_lldb::fpu_v9, arm64_lldb::fpu_d9, + LLDB_INVALID_REGNUM}; +static uint32_t g_s10_invalidates[] = {arm64_lldb::fpu_v10, arm64_lldb::fpu_d10, + LLDB_INVALID_REGNUM}; +static uint32_t g_s11_invalidates[] = {arm64_lldb::fpu_v11, arm64_lldb::fpu_d11, + LLDB_INVALID_REGNUM}; +static uint32_t g_s12_invalidates[] = {arm64_lldb::fpu_v12, arm64_lldb::fpu_d12, + LLDB_INVALID_REGNUM}; +static uint32_t g_s13_invalidates[] = {arm64_lldb::fpu_v13, arm64_lldb::fpu_d13, + LLDB_INVALID_REGNUM}; +static uint32_t g_s14_invalidates[] = {arm64_lldb::fpu_v14, arm64_lldb::fpu_d14, + LLDB_INVALID_REGNUM}; +static uint32_t g_s15_invalidates[] = {arm64_lldb::fpu_v15, arm64_lldb::fpu_d15, + LLDB_INVALID_REGNUM}; +static uint32_t g_s16_invalidates[] = {arm64_lldb::fpu_v16, arm64_lldb::fpu_d16, + LLDB_INVALID_REGNUM}; +static uint32_t g_s17_invalidates[] = {arm64_lldb::fpu_v17, arm64_lldb::fpu_d17, + LLDB_INVALID_REGNUM}; +static uint32_t g_s18_invalidates[] = {arm64_lldb::fpu_v18, arm64_lldb::fpu_d18, + LLDB_INVALID_REGNUM}; +static uint32_t g_s19_invalidates[] = {arm64_lldb::fpu_v19, arm64_lldb::fpu_d19, + LLDB_INVALID_REGNUM}; +static uint32_t g_s20_invalidates[] = {arm64_lldb::fpu_v20, arm64_lldb::fpu_d20, + LLDB_INVALID_REGNUM}; +static uint32_t g_s21_invalidates[] = {arm64_lldb::fpu_v21, arm64_lldb::fpu_d21, + LLDB_INVALID_REGNUM}; +static uint32_t g_s22_invalidates[] = {arm64_lldb::fpu_v22, arm64_lldb::fpu_d22, + LLDB_INVALID_REGNUM}; +static uint32_t g_s23_invalidates[] = {arm64_lldb::fpu_v23, arm64_lldb::fpu_d23, + LLDB_INVALID_REGNUM}; +static uint32_t g_s24_invalidates[] = {arm64_lldb::fpu_v24, arm64_lldb::fpu_d24, + LLDB_INVALID_REGNUM}; +static uint32_t g_s25_invalidates[] = {arm64_lldb::fpu_v25, arm64_lldb::fpu_d25, + LLDB_INVALID_REGNUM}; +static uint32_t g_s26_invalidates[] = {arm64_lldb::fpu_v26, arm64_lldb::fpu_d26, + LLDB_INVALID_REGNUM}; +static uint32_t g_s27_invalidates[] = {arm64_lldb::fpu_v27, arm64_lldb::fpu_d27, + LLDB_INVALID_REGNUM}; +static uint32_t g_s28_invalidates[] = {arm64_lldb::fpu_v28, arm64_lldb::fpu_d28, + LLDB_INVALID_REGNUM}; +static uint32_t g_s29_invalidates[] = {arm64_lldb::fpu_v29, arm64_lldb::fpu_d29, + LLDB_INVALID_REGNUM}; +static uint32_t g_s30_invalidates[] = {arm64_lldb::fpu_v30, arm64_lldb::fpu_d30, + LLDB_INVALID_REGNUM}; +static uint32_t g_s31_invalidates[] = {arm64_lldb::fpu_v31, arm64_lldb::fpu_d31, + LLDB_INVALID_REGNUM}; - fpu_d0, - fpu_d1, - fpu_d2, - fpu_d3, - fpu_d4, - fpu_d5, - fpu_d6, - fpu_d7, - fpu_d8, - fpu_d9, - fpu_d10, - fpu_d11, - fpu_d12, - fpu_d13, - fpu_d14, - fpu_d15, - fpu_d16, - fpu_d17, - fpu_d18, - fpu_d19, - fpu_d20, - fpu_d21, - fpu_d22, - fpu_d23, - fpu_d24, - fpu_d25, - fpu_d26, - fpu_d27, - fpu_d28, - fpu_d29, - fpu_d30, - fpu_d31, +static uint32_t g_d0_invalidates[] = {arm64_lldb::fpu_v0, arm64_lldb::fpu_s0, + LLDB_INVALID_REGNUM}; +static uint32_t g_d1_invalidates[] = {arm64_lldb::fpu_v1, arm64_lldb::fpu_s1, + LLDB_INVALID_REGNUM}; +static uint32_t g_d2_invalidates[] = {arm64_lldb::fpu_v2, arm64_lldb::fpu_s2, + LLDB_INVALID_REGNUM}; +static uint32_t g_d3_invalidates[] = {arm64_lldb::fpu_v3, arm64_lldb::fpu_s3, + LLDB_INVALID_REGNUM}; +static uint32_t g_d4_invalidates[] = {arm64_lldb::fpu_v4, arm64_lldb::fpu_s4, + LLDB_INVALID_REGNUM}; +static uint32_t g_d5_invalidates[] = {arm64_lldb::fpu_v5, arm64_lldb::fpu_s5, + LLDB_INVALID_REGNUM}; +static uint32_t g_d6_invalidates[] = {arm64_lldb::fpu_v6, arm64_lldb::fpu_s6, + LLDB_INVALID_REGNUM}; +static uint32_t g_d7_invalidates[] = {arm64_lldb::fpu_v7, arm64_lldb::fpu_s7, + LLDB_INVALID_REGNUM}; +static uint32_t g_d8_invalidates[] = {arm64_lldb::fpu_v8, arm64_lldb::fpu_s8, + LLDB_INVALID_REGNUM}; +static uint32_t g_d9_invalidates[] = {arm64_lldb::fpu_v9, arm64_lldb::fpu_s9, + LLDB_INVALID_REGNUM}; +static uint32_t g_d10_invalidates[] = {arm64_lldb::fpu_v10, arm64_lldb::fpu_s10, + LLDB_INVALID_REGNUM}; +static uint32_t g_d11_invalidates[] = {arm64_lldb::fpu_v11, arm64_lldb::fpu_s11, + LLDB_INVALID_REGNUM}; +static uint32_t g_d12_invalidates[] = {arm64_lldb::fpu_v12, arm64_lldb::fpu_s12, + LLDB_INVALID_REGNUM}; +static uint32_t g_d13_invalidates[] = {arm64_lldb::fpu_v13, arm64_lldb::fpu_s13, + LLDB_INVALID_REGNUM}; +static uint32_t g_d14_invalidates[] = {arm64_lldb::fpu_v14, arm64_lldb::fpu_s14, + LLDB_INVALID_REGNUM}; +static uint32_t g_d15_invalidates[] = {arm64_lldb::fpu_v15, arm64_lldb::fpu_s15, + LLDB_INVALID_REGNUM}; +static uint32_t g_d16_invalidates[] = {arm64_lldb::fpu_v16, arm64_lldb::fpu_s16, + LLDB_INVALID_REGNUM}; +static uint32_t g_d17_invalidates[] = {arm64_lldb::fpu_v17, arm64_lldb::fpu_s17, + LLDB_INVALID_REGNUM}; +static uint32_t g_d18_invalidates[] = {arm64_lldb::fpu_v18, arm64_lldb::fpu_s18, + LLDB_INVALID_REGNUM}; +static uint32_t g_d19_invalidates[] = {arm64_lldb::fpu_v19, arm64_lldb::fpu_s19, + LLDB_INVALID_REGNUM}; +static uint32_t g_d20_invalidates[] = {arm64_lldb::fpu_v20, arm64_lldb::fpu_s20, + LLDB_INVALID_REGNUM}; +static uint32_t g_d21_invalidates[] = {arm64_lldb::fpu_v21, arm64_lldb::fpu_s21, + LLDB_INVALID_REGNUM}; +static uint32_t g_d22_invalidates[] = {arm64_lldb::fpu_v22, arm64_lldb::fpu_s22, + LLDB_INVALID_REGNUM}; +static uint32_t g_d23_invalidates[] = {arm64_lldb::fpu_v23, arm64_lldb::fpu_s23, + LLDB_INVALID_REGNUM}; +static uint32_t g_d24_invalidates[] = {arm64_lldb::fpu_v24, arm64_lldb::fpu_s24, + LLDB_INVALID_REGNUM}; +static uint32_t g_d25_invalidates[] = {arm64_lldb::fpu_v25, arm64_lldb::fpu_s25, + LLDB_INVALID_REGNUM}; +static uint32_t g_d26_invalidates[] = {arm64_lldb::fpu_v26, arm64_lldb::fpu_s26, + LLDB_INVALID_REGNUM}; +static uint32_t g_d27_invalidates[] = {arm64_lldb::fpu_v27, arm64_lldb::fpu_s27, + LLDB_INVALID_REGNUM}; +static uint32_t g_d28_invalidates[] = {arm64_lldb::fpu_v28, arm64_lldb::fpu_s28, + LLDB_INVALID_REGNUM}; +static uint32_t g_d29_invalidates[] = {arm64_lldb::fpu_v29, arm64_lldb::fpu_s29, + LLDB_INVALID_REGNUM}; +static uint32_t g_d30_invalidates[] = {arm64_lldb::fpu_v30, arm64_lldb::fpu_s30, + LLDB_INVALID_REGNUM}; +static uint32_t g_d31_invalidates[] = {arm64_lldb::fpu_v31, arm64_lldb::fpu_s31, + LLDB_INVALID_REGNUM}; - fpu_fpsr, - fpu_fpcr, - - exc_far, - exc_esr, - exc_exception, - - dbg_bvr0, - dbg_bvr1, - dbg_bvr2, - dbg_bvr3, - dbg_bvr4, - dbg_bvr5, - dbg_bvr6, - dbg_bvr7, - dbg_bvr8, - dbg_bvr9, - dbg_bvr10, - dbg_bvr11, - dbg_bvr12, - dbg_bvr13, - dbg_bvr14, - dbg_bvr15, - - dbg_bcr0, - dbg_bcr1, - dbg_bcr2, - dbg_bcr3, - dbg_bcr4, - dbg_bcr5, - dbg_bcr6, - dbg_bcr7, - dbg_bcr8, - dbg_bcr9, - dbg_bcr10, - dbg_bcr11, - dbg_bcr12, - dbg_bcr13, - dbg_bcr14, - dbg_bcr15, - - dbg_wvr0, - dbg_wvr1, - dbg_wvr2, - dbg_wvr3, - dbg_wvr4, - dbg_wvr5, - dbg_wvr6, - dbg_wvr7, - dbg_wvr8, - dbg_wvr9, - dbg_wvr10, - dbg_wvr11, - dbg_wvr12, - dbg_wvr13, - dbg_wvr14, - dbg_wvr15, - - dbg_wcr0, - dbg_wcr1, - dbg_wcr2, - dbg_wcr3, - dbg_wcr4, - dbg_wcr5, - dbg_wcr6, - dbg_wcr7, - dbg_wcr8, - dbg_wcr9, - dbg_wcr10, - dbg_wcr11, - dbg_wcr12, - dbg_wcr13, - dbg_wcr14, - dbg_wcr15, - - k_num_registers -}; - -static uint32_t g_x0_contains[] = {gpr_w0, LLDB_INVALID_REGNUM}; -static uint32_t g_x1_contains[] = {gpr_w1, LLDB_INVALID_REGNUM}; -static uint32_t g_x2_contains[] = {gpr_w2, LLDB_INVALID_REGNUM}; -static uint32_t g_x3_contains[] = {gpr_w3, LLDB_INVALID_REGNUM}; -static uint32_t g_x4_contains[] = {gpr_w4, LLDB_INVALID_REGNUM}; -static uint32_t g_x5_contains[] = {gpr_w5, LLDB_INVALID_REGNUM}; -static uint32_t g_x6_contains[] = {gpr_w6, LLDB_INVALID_REGNUM}; -static uint32_t g_x7_contains[] = {gpr_w7, LLDB_INVALID_REGNUM}; -static uint32_t g_x8_contains[] = {gpr_w8, LLDB_INVALID_REGNUM}; -static uint32_t g_x9_contains[] = {gpr_w9, LLDB_INVALID_REGNUM}; -static uint32_t g_x10_contains[] = {gpr_w10, LLDB_INVALID_REGNUM}; -static uint32_t g_x11_contains[] = {gpr_w11, LLDB_INVALID_REGNUM}; -static uint32_t g_x12_contains[] = {gpr_w12, LLDB_INVALID_REGNUM}; -static uint32_t g_x13_contains[] = {gpr_w13, LLDB_INVALID_REGNUM}; -static uint32_t g_x14_contains[] = {gpr_w14, LLDB_INVALID_REGNUM}; -static uint32_t g_x15_contains[] = {gpr_w15, LLDB_INVALID_REGNUM}; -static uint32_t g_x16_contains[] = {gpr_w16, LLDB_INVALID_REGNUM}; -static uint32_t g_x17_contains[] = {gpr_w17, LLDB_INVALID_REGNUM}; -static uint32_t g_x18_contains[] = {gpr_w18, LLDB_INVALID_REGNUM}; -static uint32_t g_x19_contains[] = {gpr_w19, LLDB_INVALID_REGNUM}; -static uint32_t g_x20_contains[] = {gpr_w20, LLDB_INVALID_REGNUM}; -static uint32_t g_x21_contains[] = {gpr_w21, LLDB_INVALID_REGNUM}; -static uint32_t g_x22_contains[] = {gpr_w22, LLDB_INVALID_REGNUM}; -static uint32_t g_x23_contains[] = {gpr_w23, LLDB_INVALID_REGNUM}; -static uint32_t g_x24_contains[] = {gpr_w24, LLDB_INVALID_REGNUM}; -static uint32_t g_x25_contains[] = {gpr_w25, LLDB_INVALID_REGNUM}; -static uint32_t g_x26_contains[] = {gpr_w26, LLDB_INVALID_REGNUM}; -static uint32_t g_x27_contains[] = {gpr_w27, LLDB_INVALID_REGNUM}; -static uint32_t g_x28_contains[] = {gpr_w28, LLDB_INVALID_REGNUM}; - -static uint32_t g_w0_invalidates[] = {gpr_x0, LLDB_INVALID_REGNUM}; -static uint32_t g_w1_invalidates[] = {gpr_x1, LLDB_INVALID_REGNUM}; -static uint32_t g_w2_invalidates[] = {gpr_x2, LLDB_INVALID_REGNUM}; -static uint32_t g_w3_invalidates[] = {gpr_x3, LLDB_INVALID_REGNUM}; -static uint32_t g_w4_invalidates[] = {gpr_x4, LLDB_INVALID_REGNUM}; -static uint32_t g_w5_invalidates[] = {gpr_x5, LLDB_INVALID_REGNUM}; -static uint32_t g_w6_invalidates[] = {gpr_x6, LLDB_INVALID_REGNUM}; -static uint32_t g_w7_invalidates[] = {gpr_x7, LLDB_INVALID_REGNUM}; -static uint32_t g_w8_invalidates[] = {gpr_x8, LLDB_INVALID_REGNUM}; -static uint32_t g_w9_invalidates[] = {gpr_x9, LLDB_INVALID_REGNUM}; -static uint32_t g_w10_invalidates[] = {gpr_x10, LLDB_INVALID_REGNUM}; -static uint32_t g_w11_invalidates[] = {gpr_x11, LLDB_INVALID_REGNUM}; -static uint32_t g_w12_invalidates[] = {gpr_x12, LLDB_INVALID_REGNUM}; -static uint32_t g_w13_invalidates[] = {gpr_x13, LLDB_INVALID_REGNUM}; -static uint32_t g_w14_invalidates[] = {gpr_x14, LLDB_INVALID_REGNUM}; -static uint32_t g_w15_invalidates[] = {gpr_x15, LLDB_INVALID_REGNUM}; -static uint32_t g_w16_invalidates[] = {gpr_x16, LLDB_INVALID_REGNUM}; -static uint32_t g_w17_invalidates[] = {gpr_x17, LLDB_INVALID_REGNUM}; -static uint32_t g_w18_invalidates[] = {gpr_x18, LLDB_INVALID_REGNUM}; -static uint32_t g_w19_invalidates[] = {gpr_x19, LLDB_INVALID_REGNUM}; -static uint32_t g_w20_invalidates[] = {gpr_x20, LLDB_INVALID_REGNUM}; -static uint32_t g_w21_invalidates[] = {gpr_x21, LLDB_INVALID_REGNUM}; -static uint32_t g_w22_invalidates[] = {gpr_x22, LLDB_INVALID_REGNUM}; -static uint32_t g_w23_invalidates[] = {gpr_x23, LLDB_INVALID_REGNUM}; -static uint32_t g_w24_invalidates[] = {gpr_x24, LLDB_INVALID_REGNUM}; -static uint32_t g_w25_invalidates[] = {gpr_x25, LLDB_INVALID_REGNUM}; -static uint32_t g_w26_invalidates[] = {gpr_x26, LLDB_INVALID_REGNUM}; -static uint32_t g_w27_invalidates[] = {gpr_x27, LLDB_INVALID_REGNUM}; -static uint32_t g_w28_invalidates[] = {gpr_x28, LLDB_INVALID_REGNUM}; - -static uint32_t g_v0_contains[] = {fpu_s0, fpu_d0, LLDB_INVALID_REGNUM}; -static uint32_t g_v1_contains[] = {fpu_s1, fpu_d1, LLDB_INVALID_REGNUM}; -static uint32_t g_v2_contains[] = {fpu_s2, fpu_d2, LLDB_INVALID_REGNUM}; -static uint32_t g_v3_contains[] = {fpu_s3, fpu_d3, LLDB_INVALID_REGNUM}; -static uint32_t g_v4_contains[] = {fpu_s4, fpu_d4, LLDB_INVALID_REGNUM}; -static uint32_t g_v5_contains[] = {fpu_s5, fpu_d5, LLDB_INVALID_REGNUM}; -static uint32_t g_v6_contains[] = {fpu_s6, fpu_d6, LLDB_INVALID_REGNUM}; -static uint32_t g_v7_contains[] = {fpu_s7, fpu_d7, LLDB_INVALID_REGNUM}; -static uint32_t g_v8_contains[] = {fpu_s8, fpu_d8, LLDB_INVALID_REGNUM}; -static uint32_t g_v9_contains[] = {fpu_s9, fpu_d9, LLDB_INVALID_REGNUM}; -static uint32_t g_v10_contains[] = {fpu_s10, fpu_d10, LLDB_INVALID_REGNUM}; -static uint32_t g_v11_contains[] = {fpu_s11, fpu_d11, LLDB_INVALID_REGNUM}; -static uint32_t g_v12_contains[] = {fpu_s12, fpu_d12, LLDB_INVALID_REGNUM}; -static uint32_t g_v13_contains[] = {fpu_s13, fpu_d13, LLDB_INVALID_REGNUM}; -static uint32_t g_v14_contains[] = {fpu_s14, fpu_d14, LLDB_INVALID_REGNUM}; -static uint32_t g_v15_contains[] = {fpu_s15, fpu_d15, LLDB_INVALID_REGNUM}; -static uint32_t g_v16_contains[] = {fpu_s16, fpu_d16, LLDB_INVALID_REGNUM}; -static uint32_t g_v17_contains[] = {fpu_s17, fpu_d17, LLDB_INVALID_REGNUM}; -static uint32_t g_v18_contains[] = {fpu_s18, fpu_d18, LLDB_INVALID_REGNUM}; -static uint32_t g_v19_contains[] = {fpu_s19, fpu_d19, LLDB_INVALID_REGNUM}; -static uint32_t g_v20_contains[] = {fpu_s20, fpu_d20, LLDB_INVALID_REGNUM}; -static uint32_t g_v21_contains[] = {fpu_s21, fpu_d21, LLDB_INVALID_REGNUM}; -static uint32_t g_v22_contains[] = {fpu_s22, fpu_d22, LLDB_INVALID_REGNUM}; -static uint32_t g_v23_contains[] = {fpu_s23, fpu_d23, LLDB_INVALID_REGNUM}; -static uint32_t g_v24_contains[] = {fpu_s24, fpu_d24, LLDB_INVALID_REGNUM}; -static uint32_t g_v25_contains[] = {fpu_s25, fpu_d25, LLDB_INVALID_REGNUM}; -static uint32_t g_v26_contains[] = {fpu_s26, fpu_d26, LLDB_INVALID_REGNUM}; -static uint32_t g_v27_contains[] = {fpu_s27, fpu_d27, LLDB_INVALID_REGNUM}; -static uint32_t g_v28_contains[] = {fpu_s28, fpu_d28, LLDB_INVALID_REGNUM}; -static uint32_t g_v29_contains[] = {fpu_s29, fpu_d29, LLDB_INVALID_REGNUM}; -static uint32_t g_v30_contains[] = {fpu_s30, fpu_d30, LLDB_INVALID_REGNUM}; -static uint32_t g_v31_contains[] = {fpu_s31, fpu_d31, LLDB_INVALID_REGNUM}; - -static uint32_t g_s0_invalidates[] = {fpu_v0, fpu_d0, LLDB_INVALID_REGNUM}; -static uint32_t g_s1_invalidates[] = {fpu_v1, fpu_d1, LLDB_INVALID_REGNUM}; -static uint32_t g_s2_invalidates[] = {fpu_v2, fpu_d2, LLDB_INVALID_REGNUM}; -static uint32_t g_s3_invalidates[] = {fpu_v3, fpu_d3, LLDB_INVALID_REGNUM}; -static uint32_t g_s4_invalidates[] = {fpu_v4, fpu_d4, LLDB_INVALID_REGNUM}; -static uint32_t g_s5_invalidates[] = {fpu_v5, fpu_d5, LLDB_INVALID_REGNUM}; -static uint32_t g_s6_invalidates[] = {fpu_v6, fpu_d6, LLDB_INVALID_REGNUM}; -static uint32_t g_s7_invalidates[] = {fpu_v7, fpu_d7, LLDB_INVALID_REGNUM}; -static uint32_t g_s8_invalidates[] = {fpu_v8, fpu_d8, LLDB_INVALID_REGNUM}; -static uint32_t g_s9_invalidates[] = {fpu_v9, fpu_d9, LLDB_INVALID_REGNUM}; -static uint32_t g_s10_invalidates[] = {fpu_v10, fpu_d10, LLDB_INVALID_REGNUM}; -static uint32_t g_s11_invalidates[] = {fpu_v11, fpu_d11, LLDB_INVALID_REGNUM}; -static uint32_t g_s12_invalidates[] = {fpu_v12, fpu_d12, LLDB_INVALID_REGNUM}; -static uint32_t g_s13_invalidates[] = {fpu_v13, fpu_d13, LLDB_INVALID_REGNUM}; -static uint32_t g_s14_invalidates[] = {fpu_v14, fpu_d14, LLDB_INVALID_REGNUM}; -static uint32_t g_s15_invalidates[] = {fpu_v15, fpu_d15, LLDB_INVALID_REGNUM}; -static uint32_t g_s16_invalidates[] = {fpu_v16, fpu_d16, LLDB_INVALID_REGNUM}; -static uint32_t g_s17_invalidates[] = {fpu_v17, fpu_d17, LLDB_INVALID_REGNUM}; -static uint32_t g_s18_invalidates[] = {fpu_v18, fpu_d18, LLDB_INVALID_REGNUM}; -static uint32_t g_s19_invalidates[] = {fpu_v19, fpu_d19, LLDB_INVALID_REGNUM}; -static uint32_t g_s20_invalidates[] = {fpu_v20, fpu_d20, LLDB_INVALID_REGNUM}; -static uint32_t g_s21_invalidates[] = {fpu_v21, fpu_d21, LLDB_INVALID_REGNUM}; -static uint32_t g_s22_invalidates[] = {fpu_v22, fpu_d22, LLDB_INVALID_REGNUM}; -static uint32_t g_s23_invalidates[] = {fpu_v23, fpu_d23, LLDB_INVALID_REGNUM}; -static uint32_t g_s24_invalidates[] = {fpu_v24, fpu_d24, LLDB_INVALID_REGNUM}; -static uint32_t g_s25_invalidates[] = {fpu_v25, fpu_d25, LLDB_INVALID_REGNUM}; -static uint32_t g_s26_invalidates[] = {fpu_v26, fpu_d26, LLDB_INVALID_REGNUM}; -static uint32_t g_s27_invalidates[] = {fpu_v27, fpu_d27, LLDB_INVALID_REGNUM}; -static uint32_t g_s28_invalidates[] = {fpu_v28, fpu_d28, LLDB_INVALID_REGNUM}; -static uint32_t g_s29_invalidates[] = {fpu_v29, fpu_d29, LLDB_INVALID_REGNUM}; -static uint32_t g_s30_invalidates[] = {fpu_v30, fpu_d30, LLDB_INVALID_REGNUM}; -static uint32_t g_s31_invalidates[] = {fpu_v31, fpu_d31, LLDB_INVALID_REGNUM}; - -static uint32_t g_d0_invalidates[] = {fpu_v0, fpu_s0, LLDB_INVALID_REGNUM}; -static uint32_t g_d1_invalidates[] = {fpu_v1, fpu_s1, LLDB_INVALID_REGNUM}; -static uint32_t g_d2_invalidates[] = {fpu_v2, fpu_s2, LLDB_INVALID_REGNUM}; -static uint32_t g_d3_invalidates[] = {fpu_v3, fpu_s3, LLDB_INVALID_REGNUM}; -static uint32_t g_d4_invalidates[] = {fpu_v4, fpu_s4, LLDB_INVALID_REGNUM}; -static uint32_t g_d5_invalidates[] = {fpu_v5, fpu_s5, LLDB_INVALID_REGNUM}; -static uint32_t g_d6_invalidates[] = {fpu_v6, fpu_s6, LLDB_INVALID_REGNUM}; -static uint32_t g_d7_invalidates[] = {fpu_v7, fpu_s7, LLDB_INVALID_REGNUM}; -static uint32_t g_d8_invalidates[] = {fpu_v8, fpu_s8, LLDB_INVALID_REGNUM}; -static uint32_t g_d9_invalidates[] = {fpu_v9, fpu_s9, LLDB_INVALID_REGNUM}; -static uint32_t g_d10_invalidates[] = {fpu_v10, fpu_s10, LLDB_INVALID_REGNUM}; -static uint32_t g_d11_invalidates[] = {fpu_v11, fpu_s11, LLDB_INVALID_REGNUM}; -static uint32_t g_d12_invalidates[] = {fpu_v12, fpu_s12, LLDB_INVALID_REGNUM}; -static uint32_t g_d13_invalidates[] = {fpu_v13, fpu_s13, LLDB_INVALID_REGNUM}; -static uint32_t g_d14_invalidates[] = {fpu_v14, fpu_s14, LLDB_INVALID_REGNUM}; -static uint32_t g_d15_invalidates[] = {fpu_v15, fpu_s15, LLDB_INVALID_REGNUM}; -static uint32_t g_d16_invalidates[] = {fpu_v16, fpu_s16, LLDB_INVALID_REGNUM}; -static uint32_t g_d17_invalidates[] = {fpu_v17, fpu_s17, LLDB_INVALID_REGNUM}; -static uint32_t g_d18_invalidates[] = {fpu_v18, fpu_s18, LLDB_INVALID_REGNUM}; -static uint32_t g_d19_invalidates[] = {fpu_v19, fpu_s19, LLDB_INVALID_REGNUM}; -static uint32_t g_d20_invalidates[] = {fpu_v20, fpu_s20, LLDB_INVALID_REGNUM}; -static uint32_t g_d21_invalidates[] = {fpu_v21, fpu_s21, LLDB_INVALID_REGNUM}; -static uint32_t g_d22_invalidates[] = {fpu_v22, fpu_s22, LLDB_INVALID_REGNUM}; -static uint32_t g_d23_invalidates[] = {fpu_v23, fpu_s23, LLDB_INVALID_REGNUM}; -static uint32_t g_d24_invalidates[] = {fpu_v24, fpu_s24, LLDB_INVALID_REGNUM}; -static uint32_t g_d25_invalidates[] = {fpu_v25, fpu_s25, LLDB_INVALID_REGNUM}; -static uint32_t g_d26_invalidates[] = {fpu_v26, fpu_s26, LLDB_INVALID_REGNUM}; -static uint32_t g_d27_invalidates[] = {fpu_v27, fpu_s27, LLDB_INVALID_REGNUM}; -static uint32_t g_d28_invalidates[] = {fpu_v28, fpu_s28, LLDB_INVALID_REGNUM}; -static uint32_t g_d29_invalidates[] = {fpu_v29, fpu_s29, LLDB_INVALID_REGNUM}; -static uint32_t g_d30_invalidates[] = {fpu_v30, fpu_s30, LLDB_INVALID_REGNUM}; -static uint32_t g_d31_invalidates[] = {fpu_v31, fpu_s31, LLDB_INVALID_REGNUM}; - static lldb_private::RegisterInfo g_register_infos_arm64_le[] = { // General purpose registers // NAME ALT SZ OFFSET ENCODING @@ -478,7 +348,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x0, arm64_dwarf::x0, LLDB_REGNUM_GENERIC_ARG1, - LLDB_INVALID_REGNUM, gpr_x0}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x0}, g_x0_contains, nullptr, nullptr, @@ -490,7 +360,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x1, arm64_dwarf::x1, LLDB_REGNUM_GENERIC_ARG2, - LLDB_INVALID_REGNUM, gpr_x1}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x1}, g_x1_contains, nullptr, nullptr, @@ -502,7 +372,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x2, arm64_dwarf::x2, LLDB_REGNUM_GENERIC_ARG3, - LLDB_INVALID_REGNUM, gpr_x2}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x2}, g_x2_contains, nullptr, nullptr, @@ -514,7 +384,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x3, arm64_dwarf::x3, LLDB_REGNUM_GENERIC_ARG4, - LLDB_INVALID_REGNUM, gpr_x3}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x3}, g_x3_contains, nullptr, nullptr, @@ -526,7 +396,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x4, arm64_dwarf::x4, LLDB_REGNUM_GENERIC_ARG5, - LLDB_INVALID_REGNUM, gpr_x4}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x4}, g_x4_contains, nullptr, nullptr, @@ -538,7 +408,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x5, arm64_dwarf::x5, LLDB_REGNUM_GENERIC_ARG6, - LLDB_INVALID_REGNUM, gpr_x5}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x5}, g_x5_contains, nullptr, nullptr, @@ -550,7 +420,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x6, arm64_dwarf::x6, LLDB_REGNUM_GENERIC_ARG7, - LLDB_INVALID_REGNUM, gpr_x6}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x6}, g_x6_contains, nullptr, nullptr, @@ -562,7 +432,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x7, arm64_dwarf::x7, LLDB_REGNUM_GENERIC_ARG8, - LLDB_INVALID_REGNUM, gpr_x7}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x7}, g_x7_contains, nullptr, nullptr, @@ -574,7 +444,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x8, arm64_dwarf::x8, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_x8}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x8}, g_x8_contains, nullptr, nullptr, @@ -586,7 +456,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x9, arm64_dwarf::x9, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_x9}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x9}, g_x9_contains, nullptr, nullptr, @@ -598,7 +468,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x10, arm64_dwarf::x10, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_x10}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x10}, g_x10_contains, nullptr, nullptr, @@ -610,7 +480,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x11, arm64_dwarf::x11, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_x11}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x11}, g_x11_contains, nullptr, nullptr, @@ -622,7 +492,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x12, arm64_dwarf::x12, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_x12}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x12}, g_x12_contains, nullptr, nullptr, @@ -634,7 +504,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x13, arm64_dwarf::x13, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_x13}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x13}, g_x13_contains, nullptr, nullptr, @@ -646,7 +516,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x14, arm64_dwarf::x14, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_x14}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x14}, g_x14_contains, nullptr, nullptr, @@ -658,7 +528,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x15, arm64_dwarf::x15, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_x15}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x15}, g_x15_contains, nullptr, nullptr, @@ -670,7 +540,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x16, arm64_dwarf::x16, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_x16}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x16}, g_x16_contains, nullptr, nullptr, @@ -682,7 +552,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x17, arm64_dwarf::x17, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_x17}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x17}, g_x17_contains, nullptr, nullptr, @@ -694,7 +564,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x18, arm64_dwarf::x18, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_x18}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x18}, g_x18_contains, nullptr, nullptr, @@ -706,7 +576,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x19, arm64_dwarf::x19, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_x19}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x19}, g_x19_contains, nullptr, nullptr, @@ -718,7 +588,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x20, arm64_dwarf::x20, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_x20}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x20}, g_x20_contains, nullptr, nullptr, @@ -730,7 +600,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x21, arm64_dwarf::x21, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_x21}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x21}, g_x21_contains, nullptr, nullptr, @@ -742,7 +612,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x22, arm64_dwarf::x22, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_x22}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x22}, g_x22_contains, nullptr, nullptr, @@ -754,7 +624,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x23, arm64_dwarf::x23, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_x23}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x23}, g_x23_contains, nullptr, nullptr, @@ -766,7 +636,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x24, arm64_dwarf::x24, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_x24}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x24}, g_x24_contains, nullptr, nullptr, @@ -778,7 +648,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x25, arm64_dwarf::x25, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_x25}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x25}, g_x25_contains, nullptr, nullptr, @@ -790,7 +660,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x26, arm64_dwarf::x26, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_x26}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x26}, g_x26_contains, nullptr, nullptr, @@ -802,7 +672,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x27, arm64_dwarf::x27, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_x27}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x27}, g_x27_contains, nullptr, nullptr, @@ -814,7 +684,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::x28, arm64_dwarf::x28, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_x28}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_x28}, g_x28_contains, nullptr, nullptr, @@ -827,7 +697,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::fp, arm64_dwarf::fp, LLDB_REGNUM_GENERIC_FP, - LLDB_INVALID_REGNUM, gpr_fp}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_fp}, nullptr, nullptr, nullptr, @@ -839,7 +709,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::lr, arm64_dwarf::lr, LLDB_REGNUM_GENERIC_RA, - LLDB_INVALID_REGNUM, gpr_lr}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_lr}, nullptr, nullptr, nullptr, @@ -851,7 +721,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::sp, arm64_dwarf::sp, LLDB_REGNUM_GENERIC_SP, - LLDB_INVALID_REGNUM, gpr_sp}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_sp}, nullptr, nullptr, nullptr, @@ -863,7 +733,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::pc, arm64_dwarf::pc, LLDB_REGNUM_GENERIC_PC, - LLDB_INVALID_REGNUM, gpr_pc}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_pc}, nullptr, nullptr, nullptr, @@ -876,7 +746,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {arm64_ehframe::cpsr, arm64_dwarf::cpsr, LLDB_REGNUM_GENERIC_FLAGS, - LLDB_INVALID_REGNUM, gpr_cpsr}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_cpsr}, nullptr, nullptr, nullptr, @@ -889,7 +759,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w0}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w0}, nullptr, g_w0_invalidates, nullptr, @@ -901,7 +771,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w1}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w1}, nullptr, g_w1_invalidates, nullptr, @@ -913,7 +783,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w2}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w2}, nullptr, g_w2_invalidates, nullptr, @@ -925,7 +795,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w3}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w3}, nullptr, g_w3_invalidates, nullptr, @@ -937,7 +807,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w4}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w4}, nullptr, g_w4_invalidates, nullptr, @@ -949,7 +819,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w5}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w5}, nullptr, g_w5_invalidates, nullptr, @@ -961,7 +831,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w6}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w6}, nullptr, g_w6_invalidates, nullptr, @@ -973,7 +843,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w7}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w7}, nullptr, g_w7_invalidates, nullptr, @@ -985,7 +855,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w8}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w8}, nullptr, g_w8_invalidates, nullptr, @@ -997,7 +867,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w9}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w9}, nullptr, g_w9_invalidates, nullptr, @@ -1009,7 +879,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w10}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w10}, nullptr, g_w10_invalidates, nullptr, @@ -1021,7 +891,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w11}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w11}, nullptr, g_w11_invalidates, nullptr, @@ -1033,7 +903,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w12}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w12}, nullptr, g_w12_invalidates, nullptr, @@ -1045,7 +915,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w13}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w13}, nullptr, g_w13_invalidates, nullptr, @@ -1057,7 +927,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w14}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w14}, nullptr, g_w14_invalidates, nullptr, @@ -1069,7 +939,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w15}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w15}, nullptr, g_w15_invalidates, nullptr, @@ -1081,7 +951,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w16}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w16}, nullptr, g_w16_invalidates, nullptr, @@ -1093,7 +963,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w17}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w17}, nullptr, g_w17_invalidates, nullptr, @@ -1105,7 +975,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w18}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w18}, nullptr, g_w18_invalidates, nullptr, @@ -1117,7 +987,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w19}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w19}, nullptr, g_w19_invalidates, nullptr, @@ -1129,7 +999,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w20}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w20}, nullptr, g_w20_invalidates, nullptr, @@ -1141,7 +1011,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w21}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w21}, nullptr, g_w21_invalidates, nullptr, @@ -1153,7 +1023,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w22}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w22}, nullptr, g_w22_invalidates, nullptr, @@ -1165,7 +1035,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w23}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w23}, nullptr, g_w23_invalidates, nullptr, @@ -1177,7 +1047,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w24}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w24}, nullptr, g_w24_invalidates, nullptr, @@ -1189,7 +1059,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w25}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w25}, nullptr, g_w25_invalidates, nullptr, @@ -1201,7 +1071,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w26}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w26}, nullptr, g_w26_invalidates, nullptr, @@ -1213,7 +1083,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w27}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w27}, nullptr, g_w27_invalidates, nullptr, @@ -1225,7 +1095,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, gpr_w28}, + LLDB_INVALID_REGNUM, arm64_lldb::gpr_w28}, nullptr, g_w28_invalidates, nullptr, @@ -1238,7 +1108,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v0, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v0}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v0}, g_v0_contains, nullptr, nullptr, @@ -1250,7 +1120,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v1, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v1}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v1}, g_v1_contains, nullptr, nullptr, @@ -1262,7 +1132,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v2, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v2}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v2}, g_v2_contains, nullptr, nullptr, @@ -1274,7 +1144,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v3, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v3}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v3}, g_v3_contains, nullptr, nullptr, @@ -1286,7 +1156,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v4, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v4}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v4}, g_v4_contains, nullptr, nullptr, @@ -1298,7 +1168,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v5, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v5}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v5}, g_v5_contains, nullptr, nullptr, @@ -1310,7 +1180,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v6, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v6}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v6}, g_v6_contains, nullptr, nullptr, @@ -1322,7 +1192,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v7, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v7}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v7}, g_v7_contains, nullptr, nullptr, @@ -1334,7 +1204,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v8, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v8}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v8}, g_v8_contains, nullptr, nullptr, @@ -1346,7 +1216,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v9, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v9}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v9}, g_v9_contains, nullptr, nullptr, @@ -1358,7 +1228,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v10, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v10}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v10}, g_v10_contains, nullptr, nullptr, @@ -1370,7 +1240,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v11, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v11}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v11}, g_v11_contains, nullptr, nullptr, @@ -1382,7 +1252,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v12, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v12}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v12}, g_v12_contains, nullptr, nullptr, @@ -1394,7 +1264,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v13, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v13}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v13}, g_v13_contains, nullptr, nullptr, @@ -1406,7 +1276,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v14, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v14}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v14}, g_v14_contains, nullptr, nullptr, @@ -1418,7 +1288,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v15, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v15}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v15}, g_v15_contains, nullptr, nullptr, @@ -1430,7 +1300,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v16, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v16}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v16}, g_v16_contains, nullptr, nullptr, @@ -1442,7 +1312,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v17, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v17}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v17}, g_v17_contains, nullptr, nullptr, @@ -1454,7 +1324,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v18, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v18}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v18}, g_v18_contains, nullptr, nullptr, @@ -1466,7 +1336,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v19, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v19}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v19}, g_v19_contains, nullptr, nullptr, @@ -1478,7 +1348,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v20, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v20}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v20}, g_v20_contains, nullptr, nullptr, @@ -1490,7 +1360,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v21, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v21}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v21}, g_v21_contains, nullptr, nullptr, @@ -1502,7 +1372,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v22, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v22}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v22}, g_v22_contains, nullptr, nullptr, @@ -1514,7 +1384,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v23, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v23}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v23}, g_v23_contains, nullptr, nullptr, @@ -1526,7 +1396,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v24, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v24}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v24}, g_v24_contains, nullptr, nullptr, @@ -1538,7 +1408,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v25, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v25}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v25}, g_v25_contains, nullptr, nullptr, @@ -1550,7 +1420,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v26, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v26}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v26}, g_v26_contains, nullptr, nullptr, @@ -1562,7 +1432,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v27, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v27}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v27}, g_v27_contains, nullptr, nullptr, @@ -1574,7 +1444,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v28, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v28}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v28}, g_v28_contains, nullptr, nullptr, @@ -1586,7 +1456,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v29, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v29}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v29}, g_v29_contains, nullptr, nullptr, @@ -1598,7 +1468,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v30, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v30}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v30}, g_v30_contains, nullptr, nullptr, @@ -1610,7 +1480,7 @@ lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, {LLDB_INVALID_REGNUM, arm64_dwarf::v31, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_v31}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_v31}, g_v31_contains, nullptr, nullptr, @@ -1623,7 +1493,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s0}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s0}, nullptr, g_s0_invalidates, nullptr, @@ -1635,7 +1505,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s1}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s1}, nullptr, g_s1_invalidates, nullptr, @@ -1647,7 +1517,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s2}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s2}, nullptr, g_s2_invalidates, nullptr, @@ -1659,7 +1529,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s3}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s3}, nullptr, g_s3_invalidates, nullptr, @@ -1671,7 +1541,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s4}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s4}, nullptr, g_s4_invalidates, nullptr, @@ -1683,7 +1553,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s5}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s5}, nullptr, g_s5_invalidates, nullptr, @@ -1695,7 +1565,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s6}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s6}, nullptr, g_s6_invalidates, nullptr, @@ -1707,7 +1577,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s7}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s7}, nullptr, g_s7_invalidates, nullptr, @@ -1719,7 +1589,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s8}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s8}, nullptr, g_s8_invalidates, nullptr, @@ -1731,7 +1601,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s9}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s9}, nullptr, g_s9_invalidates, nullptr, @@ -1743,7 +1613,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s10}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s10}, nullptr, g_s10_invalidates, nullptr, @@ -1755,7 +1625,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s11}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s11}, nullptr, g_s11_invalidates, nullptr, @@ -1767,7 +1637,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s12}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s12}, nullptr, g_s12_invalidates, nullptr, @@ -1779,7 +1649,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s13}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s13}, nullptr, g_s13_invalidates, nullptr, @@ -1791,7 +1661,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s14}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s14}, nullptr, g_s14_invalidates, nullptr, @@ -1803,7 +1673,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s15}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s15}, nullptr, g_s15_invalidates, nullptr, @@ -1815,7 +1685,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s16}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s16}, nullptr, g_s16_invalidates, nullptr, @@ -1827,7 +1697,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s17}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s17}, nullptr, g_s17_invalidates, nullptr, @@ -1839,7 +1709,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s18}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s18}, nullptr, g_s18_invalidates, nullptr, @@ -1851,7 +1721,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s19}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s19}, nullptr, g_s19_invalidates, nullptr, @@ -1863,7 +1733,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s20}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s20}, nullptr, g_s20_invalidates, nullptr, @@ -1875,7 +1745,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s21}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s21}, nullptr, g_s21_invalidates, nullptr, @@ -1887,7 +1757,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s22}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s22}, nullptr, g_s22_invalidates, nullptr, @@ -1899,7 +1769,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s23}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s23}, nullptr, g_s23_invalidates, nullptr, @@ -1911,7 +1781,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s24}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s24}, nullptr, g_s24_invalidates, nullptr, @@ -1923,7 +1793,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s25}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s25}, nullptr, g_s25_invalidates, nullptr, @@ -1935,7 +1805,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s26}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s26}, nullptr, g_s26_invalidates, nullptr, @@ -1947,7 +1817,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s27}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s27}, nullptr, g_s27_invalidates, nullptr, @@ -1959,7 +1829,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s28}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s28}, nullptr, g_s28_invalidates, nullptr, @@ -1971,7 +1841,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s29}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s29}, nullptr, g_s29_invalidates, nullptr, @@ -1983,7 +1853,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s30}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s30}, nullptr, g_s30_invalidates, nullptr, @@ -1995,7 +1865,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_s31}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_s31}, nullptr, g_s31_invalidates, nullptr, @@ -2008,7 +1878,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d0}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d0}, nullptr, g_d0_invalidates, nullptr, @@ -2020,7 +1890,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d1}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d1}, nullptr, g_d1_invalidates, nullptr, @@ -2032,7 +1902,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d2}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d2}, nullptr, g_d2_invalidates, nullptr, @@ -2044,7 +1914,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d3}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d3}, nullptr, g_d3_invalidates, nullptr, @@ -2056,7 +1926,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d4}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d4}, nullptr, g_d4_invalidates, nullptr, @@ -2068,7 +1938,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d5}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d5}, nullptr, g_d5_invalidates, nullptr, @@ -2080,7 +1950,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d6}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d6}, nullptr, g_d6_invalidates, nullptr, @@ -2092,7 +1962,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d7}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d7}, nullptr, g_d7_invalidates, nullptr, @@ -2104,7 +1974,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d8}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d8}, nullptr, g_d8_invalidates, nullptr, @@ -2116,7 +1986,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d9}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d9}, nullptr, g_d9_invalidates, nullptr, @@ -2128,7 +1998,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d10}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d10}, nullptr, g_d10_invalidates, nullptr, @@ -2140,7 +2010,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d11}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d11}, nullptr, g_d11_invalidates, nullptr, @@ -2152,7 +2022,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d12}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d12}, nullptr, g_d12_invalidates, nullptr, @@ -2164,7 +2034,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d13}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d13}, nullptr, g_d13_invalidates, nullptr, @@ -2176,7 +2046,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d14}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d14}, nullptr, g_d14_invalidates, nullptr, @@ -2188,7 +2058,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d15}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d15}, nullptr, g_d15_invalidates, nullptr, @@ -2200,7 +2070,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d16}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d16}, nullptr, g_d16_invalidates, nullptr, @@ -2212,7 +2082,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d17}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d17}, nullptr, g_d17_invalidates, nullptr, @@ -2224,7 +2094,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d18}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d18}, nullptr, g_d18_invalidates, nullptr, @@ -2236,7 +2106,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d19}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d19}, nullptr, g_d19_invalidates, nullptr, @@ -2248,7 +2118,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d20}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d20}, nullptr, g_d20_invalidates, nullptr, @@ -2260,7 +2130,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d21}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d21}, nullptr, g_d21_invalidates, nullptr, @@ -2272,7 +2142,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d22}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d22}, nullptr, g_d22_invalidates, nullptr, @@ -2284,7 +2154,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d23}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d23}, nullptr, g_d23_invalidates, nullptr, @@ -2296,7 +2166,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d24}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d24}, nullptr, g_d24_invalidates, nullptr, @@ -2308,7 +2178,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d25}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d25}, nullptr, g_d25_invalidates, nullptr, @@ -2320,7 +2190,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d26}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d26}, nullptr, g_d26_invalidates, nullptr, @@ -2332,7 +2202,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d27}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d27}, nullptr, g_d27_invalidates, nullptr, @@ -2344,7 +2214,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d28}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d28}, nullptr, g_d28_invalidates, nullptr, @@ -2356,7 +2226,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d29}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d29}, nullptr, g_d29_invalidates, nullptr, @@ -2368,7 +2238,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d30}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d30}, nullptr, g_d30_invalidates, nullptr, @@ -2380,7 +2250,7 @@ lldb::eEncodingIEEE754, lldb::eFormatFloat, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_d31}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_d31}, nullptr, g_d31_invalidates, nullptr, @@ -2393,7 +2263,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_fpsr}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_fpsr}, nullptr, nullptr, nullptr, @@ -2405,7 +2275,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, fpu_fpcr}, + LLDB_INVALID_REGNUM, arm64_lldb::fpu_fpcr}, nullptr, nullptr, nullptr, @@ -2418,7 +2288,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, exc_far}, + LLDB_INVALID_REGNUM, arm64_lldb::exc_far}, nullptr, nullptr, nullptr, @@ -2430,7 +2300,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, exc_esr}, + LLDB_INVALID_REGNUM, arm64_lldb::exc_esr}, nullptr, nullptr, nullptr, @@ -2442,7 +2312,7 @@ lldb::eEncodingUint, lldb::eFormatHex, {LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, LLDB_INVALID_REGNUM, - LLDB_INVALID_REGNUM, exc_exception}, + LLDB_INVALID_REGNUM, arm64_lldb::exc_exception}, nullptr, nullptr, nullptr, Index: source/Utility/ARM64_LLDB_Registers.h =================================================================== --- source/Utility/ARM64_LLDB_Registers.h +++ source/Utility/ARM64_LLDB_Registers.h @@ -0,0 +1,280 @@ +//===-- ARM64_LLDB_Registers.h ----------------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +// The enum values for all of the arm64 registers for the lldb register +// numbering space (eRegisterKindLLDB). + +#ifndef utility_ARM64_LLDB_Registers_h_ +#define utility_ARM64_LLDB_Registers_h_ + +#include "lldb/lldb-private-types.h" + +// It may not work long-term to have a single "lldb register definitions +// file" for arm64 - for instance if lldb were targetting an arm64 +// device that did not have the vector registers, it wouldn't be correct +// to include those in the register set that we show the user. Currently, +// the aarch64 family is small enough that these registers are available +// on all platforms. + +namespace arm64_lldb { + +enum { + gpr_x0 = 0, + gpr_x1, + gpr_x2, + gpr_x3, + gpr_x4, + gpr_x5, + gpr_x6, + gpr_x7, + gpr_x8, + gpr_x9, + gpr_x10, + gpr_x11, + gpr_x12, + gpr_x13, + gpr_x14, + gpr_x15, + gpr_x16, + gpr_x17, + gpr_x18, + gpr_x19, + gpr_x20, + gpr_x21, + gpr_x22, + gpr_x23, + gpr_x24, + gpr_x25, + gpr_x26, + gpr_x27, + gpr_x28, + gpr_x29 = 29, + gpr_fp = gpr_x29, + gpr_x30 = 30, + gpr_lr = gpr_x30, + gpr_ra = gpr_x30, + gpr_x31 = 31, + gpr_sp = gpr_x31, + gpr_pc = 32, + gpr_cpsr, + + gpr_w0, + gpr_w1, + gpr_w2, + gpr_w3, + gpr_w4, + gpr_w5, + gpr_w6, + gpr_w7, + gpr_w8, + gpr_w9, + gpr_w10, + gpr_w11, + gpr_w12, + gpr_w13, + gpr_w14, + gpr_w15, + gpr_w16, + gpr_w17, + gpr_w18, + gpr_w19, + gpr_w20, + gpr_w21, + gpr_w22, + gpr_w23, + gpr_w24, + gpr_w25, + gpr_w26, + gpr_w27, + gpr_w28, + + fpu_v0, + fpu_v1, + fpu_v2, + fpu_v3, + fpu_v4, + fpu_v5, + fpu_v6, + fpu_v7, + fpu_v8, + fpu_v9, + fpu_v10, + fpu_v11, + fpu_v12, + fpu_v13, + fpu_v14, + fpu_v15, + fpu_v16, + fpu_v17, + fpu_v18, + fpu_v19, + fpu_v20, + fpu_v21, + fpu_v22, + fpu_v23, + fpu_v24, + fpu_v25, + fpu_v26, + fpu_v27, + fpu_v28, + fpu_v29, + fpu_v30, + fpu_v31, + + fpu_s0, + fpu_s1, + fpu_s2, + fpu_s3, + fpu_s4, + fpu_s5, + fpu_s6, + fpu_s7, + fpu_s8, + fpu_s9, + fpu_s10, + fpu_s11, + fpu_s12, + fpu_s13, + fpu_s14, + fpu_s15, + fpu_s16, + fpu_s17, + fpu_s18, + fpu_s19, + fpu_s20, + fpu_s21, + fpu_s22, + fpu_s23, + fpu_s24, + fpu_s25, + fpu_s26, + fpu_s27, + fpu_s28, + fpu_s29, + fpu_s30, + fpu_s31, + + fpu_d0, + fpu_d1, + fpu_d2, + fpu_d3, + fpu_d4, + fpu_d5, + fpu_d6, + fpu_d7, + fpu_d8, + fpu_d9, + fpu_d10, + fpu_d11, + fpu_d12, + fpu_d13, + fpu_d14, + fpu_d15, + fpu_d16, + fpu_d17, + fpu_d18, + fpu_d19, + fpu_d20, + fpu_d21, + fpu_d22, + fpu_d23, + fpu_d24, + fpu_d25, + fpu_d26, + fpu_d27, + fpu_d28, + fpu_d29, + fpu_d30, + fpu_d31, + + fpu_fpsr, + fpu_fpcr, + + exc_far, + exc_esr, + exc_exception, + + dbg_bvr0, + dbg_bvr1, + dbg_bvr2, + dbg_bvr3, + dbg_bvr4, + dbg_bvr5, + dbg_bvr6, + dbg_bvr7, + dbg_bvr8, + dbg_bvr9, + dbg_bvr10, + dbg_bvr11, + dbg_bvr12, + dbg_bvr13, + dbg_bvr14, + dbg_bvr15, + + dbg_bcr0, + dbg_bcr1, + dbg_bcr2, + dbg_bcr3, + dbg_bcr4, + dbg_bcr5, + dbg_bcr6, + dbg_bcr7, + dbg_bcr8, + dbg_bcr9, + dbg_bcr10, + dbg_bcr11, + dbg_bcr12, + dbg_bcr13, + dbg_bcr14, + dbg_bcr15, + + dbg_wvr0, + dbg_wvr1, + dbg_wvr2, + dbg_wvr3, + dbg_wvr4, + dbg_wvr5, + dbg_wvr6, + dbg_wvr7, + dbg_wvr8, + dbg_wvr9, + dbg_wvr10, + dbg_wvr11, + dbg_wvr12, + dbg_wvr13, + dbg_wvr14, + dbg_wvr15, + + dbg_wcr0, + dbg_wcr1, + dbg_wcr2, + dbg_wcr3, + dbg_wcr4, + dbg_wcr5, + dbg_wcr6, + dbg_wcr7, + dbg_wcr8, + dbg_wcr9, + dbg_wcr10, + dbg_wcr11, + dbg_wcr12, + dbg_wcr13, + dbg_wcr14, + dbg_wcr15, + + k_num_registers +}; + +const char *GetRegisterName(unsigned reg_num, bool altnernate_name); + +bool GetRegisterInfo(unsigned reg_num, lldb_private::RegisterInfo ®_info); + +}; // namespace arm64_lldb + +#endif // utility_ARM64_LLDB_Registers_h_ Index: source/Utility/ARM64_LLDB_Registers.cpp =================================================================== --- source/Utility/ARM64_LLDB_Registers.cpp +++ source/Utility/ARM64_LLDB_Registers.cpp @@ -0,0 +1,413 @@ +//===-- ARM64_LLDB_Registers.cpp ---------------------------*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "lldb/lldb-enumerations.h" + +#include "ARM64_LLDB_Registers.h" + +using namespace lldb; +using namespace lldb_private; +using namespace arm64_lldb; + +const char *arm64_lldb::GetRegisterName(unsigned reg_num, + bool altnernate_name) { + if (altnernate_name) { + switch (reg_num) { + case gpr_fp: + return "x29"; + case gpr_lr: + return "x30"; + case gpr_sp: + return "x31"; + default: + break; + } + return nullptr; + } + switch (reg_num) { + case gpr_x0: + return "x0"; + case gpr_x1: + return "x1"; + case gpr_x2: + return "x2"; + case gpr_x3: + return "x3"; + case gpr_x4: + return "x4"; + case gpr_x5: + return "x5"; + case gpr_x6: + return "x6"; + case gpr_x7: + return "x7"; + case gpr_x8: + return "x8"; + case gpr_x9: + return "x9"; + case gpr_x10: + return "x10"; + case gpr_x11: + return "x11"; + case gpr_x12: + return "x12"; + case gpr_x13: + return "x13"; + case gpr_x14: + return "x14"; + case gpr_x15: + return "x15"; + case gpr_x16: + return "x16"; + case gpr_x17: + return "x17"; + case gpr_x18: + return "x18"; + case gpr_x19: + return "x19"; + case gpr_x20: + return "x20"; + case gpr_x21: + return "x21"; + case gpr_x22: + return "x22"; + case gpr_x23: + return "x23"; + case gpr_x24: + return "x24"; + case gpr_x25: + return "x25"; + case gpr_x26: + return "x26"; + case gpr_x27: + return "x27"; + case gpr_x28: + return "x28"; + case gpr_fp: + return "fp"; + case gpr_pc: + return "pc"; + case gpr_sp: + return "sp"; + case gpr_lr: + return "lr"; + case gpr_cpsr: + return "cpsr"; + case gpr_w0: + return "w0"; + case gpr_w1: + return "w1"; + case gpr_w2: + return "w2"; + case gpr_w3: + return "w3"; + case gpr_w4: + return "w4"; + case gpr_w5: + return "w5"; + case gpr_w6: + return "w6"; + case gpr_w7: + return "w7"; + case gpr_w8: + return "w8"; + case gpr_w9: + return "w9"; + case gpr_w10: + return "w10"; + case gpr_w11: + return "w11"; + case gpr_w12: + return "w12"; + case gpr_w13: + return "w13"; + case gpr_w14: + return "w14"; + case gpr_w15: + return "w15"; + case gpr_w16: + return "w16"; + case gpr_w17: + return "w17"; + case gpr_w18: + return "w18"; + case gpr_w19: + return "w19"; + case gpr_w20: + return "w20"; + case gpr_w21: + return "w21"; + case gpr_w22: + return "w22"; + case gpr_w23: + return "w23"; + case gpr_w24: + return "w24"; + case gpr_w25: + return "w25"; + case gpr_w26: + return "w26"; + case gpr_w27: + return "w27"; + case gpr_w28: + return "w28"; + case fpu_v0: + return "v0"; + case fpu_v1: + return "v1"; + case fpu_v2: + return "v2"; + case fpu_v3: + return "v3"; + case fpu_v4: + return "v4"; + case fpu_v5: + return "v5"; + case fpu_v6: + return "v6"; + case fpu_v7: + return "v7"; + case fpu_v8: + return "v8"; + case fpu_v9: + return "v9"; + case fpu_v10: + return "v10"; + case fpu_v11: + return "v11"; + case fpu_v12: + return "v12"; + case fpu_v13: + return "v13"; + case fpu_v14: + return "v14"; + case fpu_v15: + return "v15"; + case fpu_v16: + return "v16"; + case fpu_v17: + return "v17"; + case fpu_v18: + return "v18"; + case fpu_v19: + return "v19"; + case fpu_v20: + return "v20"; + case fpu_v21: + return "v21"; + case fpu_v22: + return "v22"; + case fpu_v23: + return "v23"; + case fpu_v24: + return "v24"; + case fpu_v25: + return "v25"; + case fpu_v26: + return "v26"; + case fpu_v27: + return "v27"; + case fpu_v28: + return "v28"; + case fpu_v29: + return "v29"; + case fpu_v30: + return "v30"; + case fpu_v31: + return "v31"; + case fpu_s0: + return "s0"; + case fpu_s1: + return "s1"; + case fpu_s2: + return "s2"; + case fpu_s3: + return "s3"; + case fpu_s4: + return "s4"; + case fpu_s5: + return "s5"; + case fpu_s6: + return "s6"; + case fpu_s7: + return "s7"; + case fpu_s8: + return "s8"; + case fpu_s9: + return "s9"; + case fpu_s10: + return "s10"; + case fpu_s11: + return "s11"; + case fpu_s12: + return "s12"; + case fpu_s13: + return "s13"; + case fpu_s14: + return "s14"; + case fpu_s15: + return "s15"; + case fpu_s16: + return "s16"; + case fpu_s17: + return "s17"; + case fpu_s18: + return "s18"; + case fpu_s19: + return "s19"; + case fpu_s20: + return "s20"; + case fpu_s21: + return "s21"; + case fpu_s22: + return "s22"; + case fpu_s23: + return "s23"; + case fpu_s24: + return "s24"; + case fpu_s25: + return "s25"; + case fpu_s26: + return "s26"; + case fpu_s27: + return "s27"; + case fpu_s28: + return "s28"; + case fpu_s29: + return "s29"; + case fpu_s30: + return "s30"; + case fpu_s31: + return "s31"; + case fpu_d0: + return "d0"; + case fpu_d1: + return "d1"; + case fpu_d2: + return "d2"; + case fpu_d3: + return "d3"; + case fpu_d4: + return "d4"; + case fpu_d5: + return "d5"; + case fpu_d6: + return "d6"; + case fpu_d7: + return "d7"; + case fpu_d8: + return "d8"; + case fpu_d9: + return "d9"; + case fpu_d10: + return "d10"; + case fpu_d11: + return "d11"; + case fpu_d12: + return "d12"; + case fpu_d13: + return "d13"; + case fpu_d14: + return "d14"; + case fpu_d15: + return "d15"; + case fpu_d16: + return "d16"; + case fpu_d17: + return "d17"; + case fpu_d18: + return "d18"; + case fpu_d19: + return "d19"; + case fpu_d20: + return "d20"; + case fpu_d21: + return "d21"; + case fpu_d22: + return "d22"; + case fpu_d23: + return "d23"; + case fpu_d24: + return "d24"; + case fpu_d25: + return "d25"; + case fpu_d26: + return "d26"; + case fpu_d27: + return "d27"; + case fpu_d28: + return "d28"; + case fpu_d29: + return "d29"; + case fpu_d30: + return "d30"; + case fpu_d31: + return "d31"; + } + return nullptr; +} + +bool arm64_lldb::GetRegisterInfo(unsigned reg_num, + lldb_private::RegisterInfo ®_info) { + ::memset(®_info, 0, sizeof(lldb_private::RegisterInfo)); + ::memset(reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds)); + + if (reg_num >= gpr_x0 && reg_num <= gpr_pc) { + reg_info.byte_size = 8; + reg_info.format = lldb::eFormatHex; + reg_info.encoding = lldb::eEncodingUint; + } else if (reg_num >= gpr_w0 && reg_num <= gpr_w28) { + reg_info.byte_size = 4; + reg_info.format = lldb::eFormatHex; + reg_info.encoding = lldb::eEncodingUint; + } else if (reg_num >= fpu_v0 && reg_num <= fpu_v31) { + reg_info.byte_size = 16; + reg_info.format = lldb::eFormatVectorOfUInt8; + reg_info.encoding = lldb::eEncodingVector; + } else if (reg_num >= fpu_s0 && reg_num <= fpu_s31) { + reg_info.byte_size = 4; + reg_info.format = lldb::eFormatFloat; + reg_info.encoding = lldb::eEncodingIEEE754; + } else if (reg_num >= fpu_d0 && reg_num <= fpu_d31) { + reg_info.byte_size = 8; + reg_info.format = lldb::eFormatFloat; + reg_info.encoding = lldb::eEncodingIEEE754; + } else if (reg_num == gpr_cpsr) { + reg_info.byte_size = 4; + reg_info.format = lldb::eFormatHex; + reg_info.encoding = lldb::eEncodingUint; + } else { + return false; + } + + reg_info.name = GetRegisterName(reg_num, false); + reg_info.alt_name = GetRegisterName(reg_num, true); + reg_info.kinds[lldb::eRegisterKindLLDB] = reg_num; + + switch (reg_num) { + case gpr_fp: + reg_info.kinds[lldb::eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FP; + break; + case gpr_lr: + reg_info.kinds[lldb::eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_RA; + break; + case gpr_sp: + reg_info.kinds[lldb::eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_SP; + break; + case gpr_pc: + reg_info.kinds[lldb::eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_PC; + break; + case gpr_cpsr: + reg_info.kinds[lldb::eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS; + break; + default: + break; + } + return true; +} Index: source/Utility/CMakeLists.txt =================================================================== --- source/Utility/CMakeLists.txt +++ source/Utility/CMakeLists.txt @@ -1,6 +1,7 @@ add_lldb_library(lldbUtility ARM_DWARF_Registers.cpp ARM64_DWARF_Registers.cpp + ARM64_LLDB_Registers.cpp ConvertEnum.cpp JSON.cpp KQueue.cpp Index: unittests/UnwindAssembly/InstEmulation/TestArm64InstEmulation.cpp =================================================================== --- unittests/UnwindAssembly/InstEmulation/TestArm64InstEmulation.cpp +++ unittests/UnwindAssembly/InstEmulation/TestArm64InstEmulation.cpp @@ -14,7 +14,7 @@ #include #include "Plugins/UnwindAssembly/InstEmulation/UnwindAssemblyInstEmulation.h" -#include "Utility/ARM64_DWARF_Registers.h" +#include "Utility/arm64_lldb_Registers.h" #include "lldb/Core/Address.h" #include "lldb/Core/AddressRange.h" @@ -24,6 +24,7 @@ #include "Plugins/Disassembler/llvm/DisassemblerLLVMC.h" #include "Plugins/Instruction/ARM64/EmulateInstructionARM64.h" +#include "Utility/ARM64_LLDB_Registers.h" #include "llvm/Support/TargetSelect.h" using namespace lldb; @@ -93,7 +94,7 @@ // CFA=sp +0 row_sp = unwind_plan.GetRowForFunctionOffset(0); EXPECT_EQ(0ull, row_sp->GetOffset()); - EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp); + EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_lldb::gpr_sp); EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true); EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset()); @@ -100,15 +101,15 @@ // CFA=sp+16 => fp=[CFA-16] lr=[CFA-8] row_sp = unwind_plan.GetRowForFunctionOffset(4); EXPECT_EQ(4ull, row_sp->GetOffset()); - EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp); + EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_lldb::gpr_sp); EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true); EXPECT_EQ(16, row_sp->GetCFAValue().GetOffset()); - EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::fp, regloc)); + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::gpr_fp, regloc)); EXPECT_TRUE(regloc.IsAtCFAPlusOffset()); EXPECT_EQ(-16, regloc.GetOffset()); - EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::lr, regloc)); + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::gpr_lr, regloc)); EXPECT_TRUE(regloc.IsAtCFAPlusOffset()); EXPECT_EQ(-8, regloc.GetOffset()); @@ -115,15 +116,15 @@ // CFA=fp+16 => fp=[CFA-16] lr=[CFA-8] row_sp = unwind_plan.GetRowForFunctionOffset(8); EXPECT_EQ(8ull, row_sp->GetOffset()); - EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::fp); + EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_lldb::gpr_fp); EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true); EXPECT_EQ(16, row_sp->GetCFAValue().GetOffset()); - EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::fp, regloc)); + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::gpr_fp, regloc)); EXPECT_TRUE(regloc.IsAtCFAPlusOffset()); EXPECT_EQ(-16, regloc.GetOffset()); - EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::lr, regloc)); + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::gpr_lr, regloc)); EXPECT_TRUE(regloc.IsAtCFAPlusOffset()); EXPECT_EQ(-8, regloc.GetOffset()); @@ -130,15 +131,15 @@ // CFA=sp+16 => fp=[CFA-16] lr=[CFA-8] row_sp = unwind_plan.GetRowForFunctionOffset(16); EXPECT_EQ(16ull, row_sp->GetOffset()); - EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp); + EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_lldb::gpr_sp); EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true); EXPECT_EQ(16, row_sp->GetCFAValue().GetOffset()); - EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::fp, regloc)); + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::gpr_fp, regloc)); EXPECT_TRUE(regloc.IsAtCFAPlusOffset()); EXPECT_EQ(-16, regloc.GetOffset()); - EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::lr, regloc)); + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::gpr_lr, regloc)); EXPECT_TRUE(regloc.IsAtCFAPlusOffset()); EXPECT_EQ(-8, regloc.GetOffset()); @@ -145,7 +146,7 @@ // CFA=sp +0 => fp= lr= row_sp = unwind_plan.GetRowForFunctionOffset(20); EXPECT_EQ(20ull, row_sp->GetOffset()); - EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp); + EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_lldb::gpr_sp); EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true); EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset()); } @@ -210,7 +211,7 @@ // 0: CFA=sp +0 => row_sp = unwind_plan.GetRowForFunctionOffset(0); EXPECT_EQ(0ull, row_sp->GetOffset()); - EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp); + EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_lldb::gpr_sp); EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true); EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset()); @@ -217,14 +218,14 @@ // 4: CFA=sp+48 => x21=[CFA-40] x22=[CFA-48] row_sp = unwind_plan.GetRowForFunctionOffset(4); EXPECT_EQ(4ull, row_sp->GetOffset()); - EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp); + EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_lldb::gpr_sp); EXPECT_EQ(48, row_sp->GetCFAValue().GetOffset()); - EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::x21, regloc)); + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::gpr_x21, regloc)); EXPECT_TRUE(regloc.IsAtCFAPlusOffset()); EXPECT_EQ(-40, regloc.GetOffset()); - EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::x22, regloc)); + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::gpr_x22, regloc)); EXPECT_TRUE(regloc.IsAtCFAPlusOffset()); EXPECT_EQ(-48, regloc.GetOffset()); @@ -231,14 +232,14 @@ // 8: CFA=sp+48 => x19=[CFA-24] x20=[CFA-32] x21=[CFA-40] x22=[CFA-48] row_sp = unwind_plan.GetRowForFunctionOffset(8); EXPECT_EQ(8ull, row_sp->GetOffset()); - EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp); + EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_lldb::gpr_sp); EXPECT_EQ(48, row_sp->GetCFAValue().GetOffset()); - EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::x19, regloc)); + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::gpr_x19, regloc)); EXPECT_TRUE(regloc.IsAtCFAPlusOffset()); EXPECT_EQ(-24, regloc.GetOffset()); - EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::x20, regloc)); + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::gpr_x20, regloc)); EXPECT_TRUE(regloc.IsAtCFAPlusOffset()); EXPECT_EQ(-32, regloc.GetOffset()); @@ -246,14 +247,14 @@ // fp=[CFA-16] lr=[CFA-8] row_sp = unwind_plan.GetRowForFunctionOffset(12); EXPECT_EQ(12ull, row_sp->GetOffset()); - EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp); + EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_lldb::gpr_sp); EXPECT_EQ(48, row_sp->GetCFAValue().GetOffset()); - EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::fp, regloc)); + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::gpr_fp, regloc)); EXPECT_TRUE(regloc.IsAtCFAPlusOffset()); EXPECT_EQ(-16, regloc.GetOffset()); - EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::lr, regloc)); + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::gpr_lr, regloc)); EXPECT_TRUE(regloc.IsAtCFAPlusOffset()); EXPECT_EQ(-8, regloc.GetOffset()); @@ -261,7 +262,7 @@ // fp=[CFA-16] lr=[CFA-8] row_sp = unwind_plan.GetRowForFunctionOffset(16); EXPECT_EQ(16ull, row_sp->GetOffset()); - EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::fp); + EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_lldb::gpr_fp); EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true); EXPECT_EQ(16, row_sp->GetCFAValue().GetOffset()); @@ -269,7 +270,7 @@ // fp=[CFA-16] lr=[CFA-8] row_sp = unwind_plan.GetRowForFunctionOffset(28); EXPECT_EQ(28ull, row_sp->GetOffset()); - EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp); + EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_lldb::gpr_sp); EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true); EXPECT_EQ(48, row_sp->GetCFAValue().GetOffset()); @@ -280,10 +281,10 @@ // I'd prefer if these restored registers were cleared entirely instead of set // to IsSame... - EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::fp, regloc)); + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::gpr_fp, regloc)); EXPECT_TRUE(regloc.IsSame()); - EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::lr, regloc)); + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::gpr_lr, regloc)); EXPECT_TRUE(regloc.IsSame()); // 36: CFA=sp+48 => x19= x20= x21=[CFA-40] x22=[CFA-48] fp= @@ -291,10 +292,10 @@ row_sp = unwind_plan.GetRowForFunctionOffset(36); EXPECT_EQ(36ull, row_sp->GetOffset()); - EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::x19, regloc)); + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::gpr_x19, regloc)); EXPECT_TRUE(regloc.IsSame()); - EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::x20, regloc)); + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::gpr_x20, regloc)); EXPECT_TRUE(regloc.IsSame()); // 40: CFA=sp +0 => x19= x20= x21= x22= fp= @@ -301,14 +302,14 @@ // lr= row_sp = unwind_plan.GetRowForFunctionOffset(40); EXPECT_EQ(40ull, row_sp->GetOffset()); - EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp); + EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_lldb::gpr_sp); EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true); EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset()); - EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::x21, regloc)); + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::gpr_x21, regloc)); EXPECT_TRUE(regloc.IsSame()); - EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::x22, regloc)); + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::gpr_x22, regloc)); EXPECT_TRUE(regloc.IsSame()); } @@ -364,45 +365,45 @@ // 0: CFA=sp +0 => row_sp = unwind_plan.GetRowForFunctionOffset(0); EXPECT_EQ(0ull, row_sp->GetOffset()); - EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp); + EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_lldb::gpr_sp); EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true); EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset()); row_sp = unwind_plan.GetRowForFunctionOffset(32); - EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp); + EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_lldb::gpr_sp); EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true); EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset()); - EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_dwarf::x19, regloc)); - EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_dwarf::x20, regloc)); - EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_dwarf::x21, regloc)); - EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_dwarf::x22, regloc)); - EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_dwarf::x23, regloc)); - EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_dwarf::x24, regloc)); - EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_dwarf::x25, regloc)); - EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_dwarf::x26, regloc)); - EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_dwarf::x27, regloc)); - EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_dwarf::x28, regloc)); - EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_dwarf::fp, regloc)); - EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_dwarf::lr, regloc)); + EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_lldb::gpr_x19, regloc)); + EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_lldb::gpr_x20, regloc)); + EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_lldb::gpr_x21, regloc)); + EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_lldb::gpr_x22, regloc)); + EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_lldb::gpr_x23, regloc)); + EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_lldb::gpr_x24, regloc)); + EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_lldb::gpr_x25, regloc)); + EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_lldb::gpr_x26, regloc)); + EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_lldb::gpr_x27, regloc)); + EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_lldb::gpr_x28, regloc)); + EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_lldb::gpr_fp, regloc)); + EXPECT_FALSE(row_sp->GetRegisterInfo(arm64_lldb::gpr_lr, regloc)); row_sp = unwind_plan.GetRowForFunctionOffset(36); - EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp); + EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_lldb::gpr_sp); EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true); EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset()); row_sp = unwind_plan.GetRowForFunctionOffset(52); - EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp); + EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_lldb::gpr_sp); EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true); EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset()); row_sp = unwind_plan.GetRowForFunctionOffset(56); - EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp); + EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_lldb::gpr_sp); EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true); EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset()); row_sp = unwind_plan.GetRowForFunctionOffset(60); - EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::sp); + EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_lldb::gpr_sp); EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true); EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset()); } @@ -490,21 +491,183 @@ row_sp = unwind_plan.GetRowForFunctionOffset(36); EXPECT_EQ(28ull, row_sp->GetOffset()); - EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::fp); + EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_lldb::gpr_fp); EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true); EXPECT_EQ(16, row_sp->GetCFAValue().GetOffset()); - EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::x20, regloc)); + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::gpr_x20, regloc)); EXPECT_TRUE(regloc.IsAtCFAPlusOffset()); EXPECT_EQ(-32, regloc.GetOffset()); row_sp = unwind_plan.GetRowForFunctionOffset(40); EXPECT_EQ(28ull, row_sp->GetOffset()); - EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_dwarf::fp); + EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_lldb::gpr_fp); EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true); EXPECT_EQ(16, row_sp->GetCFAValue().GetOffset()); - EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_dwarf::x20, regloc)); + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::gpr_x20, regloc)); EXPECT_TRUE(regloc.IsAtCFAPlusOffset()); EXPECT_EQ(-32, regloc.GetOffset()); } + +TEST_F(TestArm64InstEmulation, TestRegisterDoubleSpills) { + ArchSpec arch("arm64-apple-ios10", nullptr); + UnwindAssemblyInstEmulation *engine = + static_cast( + UnwindAssemblyInstEmulation::CreateInstance(arch)); + ASSERT_NE(nullptr, engine); + + UnwindPlan::RowSP row_sp; + AddressRange sample_range; + UnwindPlan unwind_plan(eRegisterKindLLDB); + UnwindPlan::Row::RegisterLocation regloc; + + // this file built with clang for iOS arch arm64 optimization -Os + // #include + // double foo(double in) { + // double arr[32]; + // for (int i = 0; i < 32; i++) + // arr[i] = in + i; + // for (int i = 2; i < 30; i++) + // arr[i] = ((((arr[i - 1] * arr[i - 2] * 0.2) + (0.7 * arr[i])) / + // ((((arr[i] * 0.73) + 0.65) * (arr[i - 1] + 0.2)) - ((arr[i + 1] + (arr[i] + // * 0.32) + 0.52) / 0.3) + (0.531 * arr[i - 2]))) + ((arr[i - 1] + 5) / + // ((arr[i + 2] + 0.4) / arr[i])) + (arr[5] * (0.17 + arr[7] * arr[i])) + + // ((i > 5 ? (arr[i - 3]) : arr[i - 1]) * 0.263) + (((arr[i - 2] + arr[i - + // 1]) * 0.3252) + 3.56) - (arr[i + 1] * 0.852311)) * ((arr[i] * 85234.1345) + // + (77342.451324 / (arr[i - 2] + arr[i - 1] - 73425341.33455))) + (arr[i] + // * 875712013.55) - (arr[i - 1] * 0.5555) - ((arr[i] * (arr[i + 1] + + // 17342834.44) / 8688200123.555)) + (arr[i - 2] + 8888.888); + // return arr[16]; + //} + // int main(int argc, char **argv) { printf("%g\n", foo(argc)); } + + // so function foo() uses enough registers that it spills the callee-saved + // floating point registers. + uint8_t data[] = { + // prologue + 0xef, 0x3b, 0xba, 0x6d, // 0: 0x6dba3bef stp d15, d14, [sp, #-0x60]! + 0xed, 0x33, 0x01, 0x6d, // 4: 0x6d0133ed stp d13, d12, [sp, #0x10] + 0xeb, 0x2b, 0x02, 0x6d, // 8: 0x6d022beb stp d11, d10, [sp, #0x20] + 0xe9, 0x23, 0x03, 0x6d, // 12: 0x6d0323e9 stp d9, d8, [sp, #0x30] + 0xfc, 0x6f, 0x04, 0xa9, // 16: 0xa9046ffc stp x28, x27, [sp, #0x40] + 0xfd, 0x7b, 0x05, 0xa9, // 20: 0xa9057bfd stp x29, x30, [sp, #0x50] + 0xfd, 0x43, 0x01, 0x91, // 24: 0x910143fd add x29, sp, #0x50 + 0xff, 0x43, 0x04, 0xd1, // 28: 0xd10443ff sub sp, sp, #0x110 + + // epilogue + 0xbf, 0x43, 0x01, 0xd1, // 32: 0xd10143bf sub sp, x29, #0x50 + 0xfd, 0x7b, 0x45, 0xa9, // 36: 0xa9457bfd ldp x29, x30, [sp, #0x50] + 0xfc, 0x6f, 0x44, 0xa9, // 40: 0xa9446ffc ldp x28, x27, [sp, #0x40] + 0xe9, 0x23, 0x43, 0x6d, // 44: 0x6d4323e9 ldp d9, d8, [sp, #0x30] + 0xeb, 0x2b, 0x42, 0x6d, // 48: 0x6d422beb ldp d11, d10, [sp, #0x20] + 0xed, 0x33, 0x41, 0x6d, // 52: 0x6d4133ed ldp d13, d12, [sp, #0x10] + 0xef, 0x3b, 0xc6, 0x6c, // 56: 0x6cc63bef ldp d15, d14, [sp], #0x60 + 0xc0, 0x03, 0x5f, 0xd6, // 60: 0xd65f03c0 ret + }; + + // UnwindPlan we expect: + // 0: CFA=sp +0 => + // 4: CFA=sp+96 => d14=[CFA-88] d15=[CFA-96] + // 8: CFA=sp+96 => d12=[CFA-72] d13=[CFA-80] d14=[CFA-88] d15=[CFA-96] + // 12: CFA=sp+96 => d10=[CFA-56] d11=[CFA-64] d12=[CFA-72] d13=[CFA-80] + // d14=[CFA-88] d15=[CFA-96] + // 16: CFA=sp+96 => d8=[CFA-40] d9=[CFA-48] d10=[CFA-56] d11=[CFA-64] + // d12=[CFA-72] d13=[CFA-80] d14=[CFA-88] d15=[CFA-96] + // 20: CFA=sp+96 => x27=[CFA-24] x28=[CFA-32] d8=[CFA-40] d9=[CFA-48] + // d10=[CFA-56] d11=[CFA-64] d12=[CFA-72] d13=[CFA-80] d14=[CFA-88] + // d15=[CFA-96] + // 24: CFA=sp+96 => x27=[CFA-24] x28=[CFA-32] fp=[CFA-16] lr=[CFA-8] + // d8=[CFA-40] d9=[CFA-48] d10=[CFA-56] d11=[CFA-64] d12=[CFA-72] + // d13=[CFA-80] d14=[CFA-88] d15=[CFA-96] + // 28: CFA=fp+16 => x27=[CFA-24] x28=[CFA-32] fp=[CFA-16] lr=[CFA-8] + // d8=[CFA-40] d9=[CFA-48] d10=[CFA-56] d11=[CFA-64] d12=[CFA-72] + // d13=[CFA-80] d14=[CFA-88] d15=[CFA-96] + // 36: CFA=sp+96 => x27=[CFA-24] x28=[CFA-32] fp=[CFA-16] lr=[CFA-8] + // d8=[CFA-40] d9=[CFA-48] d10=[CFA-56] d11=[CFA-64] d12=[CFA-72] + // d13=[CFA-80] d14=[CFA-88] d15=[CFA-96] + // 40: CFA=sp+96 => x27=[CFA-24] x28=[CFA-32] d8=[CFA-40] d9=[CFA-48] + // d10=[CFA-56] d11=[CFA-64] d12=[CFA-72] d13=[CFA-80] d14=[CFA-88] + // d15=[CFA-96] + // 44: CFA=sp+96 => d8=[CFA-40] d9=[CFA-48] d10=[CFA-56] d11=[CFA-64] + // d12=[CFA-72] d13=[CFA-80] d14=[CFA-88] d15=[CFA-96] + // 48: CFA=sp+96 => d10=[CFA-56] d11=[CFA-64] d12=[CFA-72] d13=[CFA-80] + // d14=[CFA-88] d15=[CFA-96] + // 52: CFA=sp+96 => d12=[CFA-72] d13=[CFA-80] d14=[CFA-88] d15=[CFA-96] + // 56: CFA=sp+96 => d14=[CFA-88] d15=[CFA-96] + // 60: CFA=sp +0 => + + sample_range = AddressRange(0x1000, sizeof(data)); + + EXPECT_TRUE(engine->GetNonCallSiteUnwindPlanFromAssembly( + sample_range, data, sizeof(data), unwind_plan)); + + // 28: CFA=fp+16 => x27=[CFA-24] x28=[CFA-32] fp=[CFA-16] lr=[CFA-8] + // d8=[CFA-40] d9=[CFA-48] d10=[CFA-56] d11=[CFA-64] d12=[CFA-72] + // d13=[CFA-80] d14=[CFA-88] d15=[CFA-96] + row_sp = unwind_plan.GetRowForFunctionOffset(28); + EXPECT_EQ(28ull, row_sp->GetOffset()); + EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_lldb::gpr_fp); + EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true); + EXPECT_EQ(16, row_sp->GetCFAValue().GetOffset()); + + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::fpu_d15, regloc)); + EXPECT_TRUE(regloc.IsAtCFAPlusOffset()); + EXPECT_EQ(-96, regloc.GetOffset()); + + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::fpu_d14, regloc)); + EXPECT_TRUE(regloc.IsAtCFAPlusOffset()); + EXPECT_EQ(-88, regloc.GetOffset()); + + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::fpu_d13, regloc)); + EXPECT_TRUE(regloc.IsAtCFAPlusOffset()); + EXPECT_EQ(-80, regloc.GetOffset()); + + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::fpu_d12, regloc)); + EXPECT_TRUE(regloc.IsAtCFAPlusOffset()); + EXPECT_EQ(-72, regloc.GetOffset()); + + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::fpu_d11, regloc)); + EXPECT_TRUE(regloc.IsAtCFAPlusOffset()); + EXPECT_EQ(-64, regloc.GetOffset()); + + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::fpu_d10, regloc)); + EXPECT_TRUE(regloc.IsAtCFAPlusOffset()); + EXPECT_EQ(-56, regloc.GetOffset()); + + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::fpu_d9, regloc)); + EXPECT_TRUE(regloc.IsAtCFAPlusOffset()); + EXPECT_EQ(-48, regloc.GetOffset()); + + EXPECT_TRUE(row_sp->GetRegisterInfo(arm64_lldb::fpu_d8, regloc)); + EXPECT_TRUE(regloc.IsAtCFAPlusOffset()); + EXPECT_EQ(-40, regloc.GetOffset()); + + // 60: CFA=sp +0 => + row_sp = unwind_plan.GetRowForFunctionOffset(60); + EXPECT_EQ(60ull, row_sp->GetOffset()); + EXPECT_TRUE(row_sp->GetCFAValue().GetRegisterNumber() == arm64_lldb::gpr_sp); + EXPECT_TRUE(row_sp->GetCFAValue().IsRegisterPlusOffset() == true); + EXPECT_EQ(0, row_sp->GetCFAValue().GetOffset()); + + if (row_sp->GetRegisterInfo(arm64_lldb::fpu_d8, regloc)) + EXPECT_TRUE(regloc.IsSame()); + if (row_sp->GetRegisterInfo(arm64_lldb::fpu_d9, regloc)) + EXPECT_TRUE(regloc.IsSame()); + if (row_sp->GetRegisterInfo(arm64_lldb::fpu_d10, regloc)) + EXPECT_TRUE(regloc.IsSame()); + if (row_sp->GetRegisterInfo(arm64_lldb::fpu_d11, regloc)) + EXPECT_TRUE(regloc.IsSame()); + if (row_sp->GetRegisterInfo(arm64_lldb::fpu_d12, regloc)) + EXPECT_TRUE(regloc.IsSame()); + if (row_sp->GetRegisterInfo(arm64_lldb::fpu_d13, regloc)) + EXPECT_TRUE(regloc.IsSame()); + if (row_sp->GetRegisterInfo(arm64_lldb::fpu_d14, regloc)) + EXPECT_TRUE(regloc.IsSame()); + if (row_sp->GetRegisterInfo(arm64_lldb::fpu_d15, regloc)) + EXPECT_TRUE(regloc.IsSame()); + if (row_sp->GetRegisterInfo(arm64_lldb::gpr_x27, regloc)) + EXPECT_TRUE(regloc.IsSame()); + if (row_sp->GetRegisterInfo(arm64_lldb::gpr_x28, regloc)) + EXPECT_TRUE(regloc.IsSame()); +}