Index: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
===================================================================
--- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
+++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp
@@ -404,6 +404,7 @@
     Match_RequiresDifferentOperands,
     Match_RequiresNoZeroRegister,
     Match_RequiresSameSrcAndDst,
+    Match_NonZeroOperandForSync,
 #define GET_OPERAND_DIAGNOSTIC_TYPES
 #include "MipsGenAsmMatcher.inc"
 #undef GET_OPERAND_DIAGNOSTIC_TYPES
@@ -3955,6 +3956,10 @@
     if (Inst.getOperand(0).getReg() == Inst.getOperand(2).getReg())
       return Match_RequiresDifferentSrcAndDst;
     return Match_Success;
+  case Mips::SYNC:
+    if (Inst.getOperand(0).getImm() != 0 && !hasMips32())
+      return Match_NonZeroOperandForSync;
+    return Match_Success;
   // As described the MIPSR6 spec, the compact branches that compare registers
   // must:
   // a) Not use the zero register.
@@ -4052,6 +4057,8 @@
 
     return Error(ErrorLoc, "invalid operand for instruction");
   }
+  case Match_NonZeroOperandForSync:
+    return Error(IDLoc, "s-type must be zero or unspecified for pre-MIPS32 ISAs");
   case Match_MnemonicFail:
     return Error(IDLoc, "invalid instruction");
   case Match_RequiresDifferentSrcAndDst:
Index: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
@@ -1876,8 +1876,7 @@
 }
 }
 
-def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM,
-           ISA_MIPS32;
+def SYNC : MMRel, StdMMR6Rel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS2;
 def SYNCI : MMRel, StdMMR6Rel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
 
 let AdditionalPredicates = [NotInMicroMips] in {
Index: llvm/trunk/test/MC/Mips/mips2/invalid-mips32.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips2/invalid-mips32.s
+++ llvm/trunk/test/MC/Mips/mips2/invalid-mips32.s
@@ -40,5 +40,4 @@
         msubu     $15,$a1         # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         mtc0      $9,$29,3        # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
         mul       $s0,$s4,$at     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
-        sync      0               # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
-        sync      1               # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        sync      1               # CHECK: :[[@LINE]]:{{[0-9]+}}: error: s-type must be zero or unspecified for pre-MIPS32 ISAs
Index: llvm/trunk/test/MC/Mips/mips2/valid.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips2/valid.s
+++ llvm/trunk/test/MC/Mips/mips2/valid.s
@@ -159,6 +159,7 @@
         swl       $15,13694($s3)
         swr       $s1,-26590($14)
         sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
+        sync 0                         # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
         syscall                        # CHECK: syscall                # encoding: [0x00,0x00,0x00,0x0c]
         syscall   256                  # CHECK: syscall 256            # encoding: [0x00,0x00,0x40,0x0c]
         teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
Index: llvm/trunk/test/MC/Mips/mips3/invalid-mips32.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips3/invalid-mips32.s
+++ llvm/trunk/test/MC/Mips/mips3/invalid-mips32.s
@@ -6,5 +6,4 @@
 
         .set noat
 
-        sync 0                    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
-        sync 1                    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        sync 1                    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: s-type must be zero or unspecified for pre-MIPS32 ISAs
Index: llvm/trunk/test/MC/Mips/mips3/valid.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips3/valid.s
+++ llvm/trunk/test/MC/Mips/mips3/valid.s
@@ -223,6 +223,7 @@
         swl       $15,13694($s3)
         swr       $s1,-26590($14)
         sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
+        sync 0                         # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
         syscall                        # CHECK: syscall                # encoding: [0x00,0x00,0x00,0x0c]
         syscall   256                  # CHECK: syscall 256            # encoding: [0x00,0x00,0x40,0x0c]
         teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
Index: llvm/trunk/test/MC/Mips/mips4/invalid-mips32.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips4/invalid-mips32.s
+++ llvm/trunk/test/MC/Mips/mips4/invalid-mips32.s
@@ -6,5 +6,4 @@
 
         .set noat
 
-        sync 0                    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
-        sync 1                    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        sync 1                    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: s-type must be zero or unspecified for pre-MIPS32 ISAs
Index: llvm/trunk/test/MC/Mips/mips4/valid.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips4/valid.s
+++ llvm/trunk/test/MC/Mips/mips4/valid.s
@@ -256,6 +256,7 @@
         swr       $s1,-26590($14)
         swxc1     $f19,$12($k0)
         sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
+        sync 0                         # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
         syscall                        # CHECK: syscall                # encoding: [0x00,0x00,0x00,0x0c]
         syscall   256                  # CHECK: syscall 256            # encoding: [0x00,0x00,0x40,0x0c]
         teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]
Index: llvm/trunk/test/MC/Mips/mips5/invalid-mips32.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips5/invalid-mips32.s
+++ llvm/trunk/test/MC/Mips/mips5/invalid-mips32.s
@@ -6,5 +6,4 @@
 
         .set noat
 
-        sync 0                    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
-        sync 1                    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
+        sync 1                    # CHECK: :[[@LINE]]:{{[0-9]+}}: error: s-type must be zero or unspecified for pre-MIPS32 ISAs
Index: llvm/trunk/test/MC/Mips/mips5/valid.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips5/valid.s
+++ llvm/trunk/test/MC/Mips/mips5/valid.s
@@ -258,6 +258,7 @@
         swr       $s1,-26590($14)
         swxc1     $f19,$12($k0)
         sync                           # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
+        sync 0                         # CHECK: sync                   # encoding: [0x00,0x00,0x00,0x0f]
         syscall                        # CHECK: syscall                # encoding: [0x00,0x00,0x00,0x0c]
         syscall   256                  # CHECK: syscall 256            # encoding: [0x00,0x00,0x40,0x0c]
         teq       $0,$3                # CHECK: teq $zero, $3          # encoding: [0x00,0x03,0x00,0x34]