Index: lib/Target/ARM/ARM.td
===================================================================
--- lib/Target/ARM/ARM.td
+++ lib/Target/ARM/ARM.td
@@ -823,7 +823,8 @@
                                                          FeatureCrypto,
                                                          FeatureCRC]>;
 
-def : ProcNoItin<"cortex-r52",                          [ARMv8r, ProcR52]>;
+def : ProcNoItin<"cortex-r52",                          [ARMv8r, ProcR52,
+                                                         FeatureFPAO]>;
 
 //===----------------------------------------------------------------------===//
 // Register File Description
Index: test/CodeGen/ARM/lsr-scale-addr-mode.ll
===================================================================
--- test/CodeGen/ARM/lsr-scale-addr-mode.ll
+++ test/CodeGen/ARM/lsr-scale-addr-mode.ll
@@ -3,6 +3,7 @@
 
 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a53 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF-A53
 ; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a57 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF-A57
+; RUN: llc -mtriple=arm-eabi -mcpu=cortex-r52 %s -o - | FileCheck %s -check-prefix CHECK-NONEGOFF-R52
 ; Should not generate negated register offset
 
 define void @sintzero(i32* %a) nounwind {
@@ -25,4 +26,5 @@
 ; CHECK: lsl{{.*}}#2]
 ; CHECK-NONEGOFF-A53: [{{r[0-9]+}}, {{r[0-9]+}}, lsl{{.*}}#2]
 ; CHECK-NONEGOFF-A57: [{{r[0-9]+}}, {{r[0-9]+}}, lsl{{.*}}#2]
+; CHECK-NONEGOFF-R52: [{{r[0-9]+}}, {{r[0-9]+}}, lsl{{.*}}#2]