Index: llvm/include/llvm/CodeGen/ISDOpcodes.h
===================================================================
--- llvm/include/llvm/CodeGen/ISDOpcodes.h
+++ llvm/include/llvm/CodeGen/ISDOpcodes.h
@@ -591,8 +591,8 @@
     ///   Operand #2  : a MDNodeSDNode with the !srcloc metadata.
     ///   Operand #3  : HasSideEffect, IsAlignStack bits.
     ///   After this, it is followed by a list of operands with this format:
-    ///     ConstantSDNode: Flags that encode whether it is a mem or not, the
-    ///                     of operands that follow, etc.  See InlineAsm.h.
+    ///     ConstantIntSDNode: Flags that encode whether it is a mem or not, the
+    ///                        of operands that follow, etc.  See InlineAsm.h.
     ///     ... however many operands ...
     ///   Operand #last: Optional, an incoming flag.
     ///
Index: llvm/include/llvm/CodeGen/SelectionDAG.h
===================================================================
--- llvm/include/llvm/CodeGen/SelectionDAG.h
+++ llvm/include/llvm/CodeGen/SelectionDAG.h
@@ -470,7 +470,7 @@
   // Node creation methods.
   //
 
-  /// \brief Create a ConstantSDNode wrapping a constant value.
+  /// \brief Create a ConstantIntSDNode wrapping a constant value.
   /// If VT is a vector type, the constant is splatted into a BUILD_VECTOR.
   ///
   /// If only legal types can be produced, this does the necessary
@@ -1245,8 +1245,8 @@
                                  SDNode *Cst1, SDNode *Cst2);
 
   SDValue FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL, EVT VT,
-                                 const ConstantSDNode *Cst1,
-                                 const ConstantSDNode *Cst2);
+                                 const ConstantIntSDNode *Cst1,
+                                 const ConstantIntSDNode *Cst2);
 
   SDValue FoldConstantVectorArithmetic(unsigned Opcode, const SDLoc &DL, EVT VT,
                                        ArrayRef<SDValue> Ops,
@@ -1287,10 +1287,10 @@
   /// target nodes to be understood.
   unsigned ComputeNumSignBits(SDValue Op, unsigned Depth = 0) const;
 
-  /// Return true if the specified operand is an ISD::ADD with a ConstantSDNode
-  /// on the right-hand side, or if it is an ISD::OR with a ConstantSDNode that
-  /// is guaranteed to have the same semantics as an ADD. This handles the
-  /// equivalence:
+  /// Return true if the specified operand is an ISD::ADD with a
+  /// ConstantIntSDNode on the right-hand side, or if it is an ISD::OR with a
+  /// ConstantIntSDNode that is guaranteed to have the same semantics as an ADD.
+  /// This handles the equivalence:
   ///     X|Cst == X+Cst iff X&Cst = 0.
   bool isBaseWithConstantOffset(SDValue Op) const;
 
Index: llvm/include/llvm/CodeGen/SelectionDAGISel.h
===================================================================
--- llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -215,11 +215,10 @@
 
 public:
   // Calls to these predicates are generated by tblgen.
-  bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
+  bool CheckAndMask(SDValue LHS, ConstantIntSDNode *RHS,
                     int64_t DesiredMaskS) const;
-  bool CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
-                    int64_t DesiredMaskS) const;
-
+  bool CheckOrMask(SDValue LHS, ConstantIntSDNode *RHS,
+                   int64_t DesiredMaskS) const;
 
   /// CheckPatternPredicate - This function is generated by tblgen in the
   /// target.  It runs the specified pattern predicate and returns true if it
Index: llvm/include/llvm/CodeGen/SelectionDAGNodes.h
===================================================================
--- llvm/include/llvm/CodeGen/SelectionDAGNodes.h
+++ llvm/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -78,8 +78,8 @@
   bool isBuildVectorAllZeros(const SDNode *N);
 
   /// Return true if the specified node is a BUILD_VECTOR node of all
-  /// ConstantSDNode or undef.
-  bool isBuildVectorOfConstantSDNodes(const SDNode *N);
+  /// ConstantIntSDNode or undef.
+  bool isBuildVectorOfConstantIntSDNodes(const SDNode *N);
 
   /// Return true if the specified node is a BUILD_VECTOR node of all
   /// ConstantFPSDNode or undef.
@@ -407,6 +407,7 @@
 
   class ConstantSDNodeBitfields {
     friend class ConstantSDNode;
+    friend class ConstantIntSDNode;
 
     uint16_t : NumSDNodeBits;
 
@@ -723,7 +724,7 @@
   /// Return the number of values used by this operation.
   unsigned getNumOperands() const { return NumOperands; }
 
-  /// Helper method returns the integer value of a ConstantSDNode operand.
+  /// Helper method returns the integer value of a ConstantIntSDNode operand.
   uint64_t getConstantOperandVal(unsigned Num) const;
 
   const SDValue &getOperand(unsigned Num) const {
@@ -1331,12 +1332,26 @@
 };
 
 class ConstantSDNode : public SDNode {
+protected:
+  ConstantSDNode(unsigned Opc, unsigned Order, DebugLoc dl, SDVTList VTs)
+      : SDNode(Opc, Order, dl, VTs) {}
+
+public:
+  static bool classof(const SDNode *N) {
+    return N->getOpcode() == ISD::Constant ||
+           N->getOpcode() == ISD::TargetConstant;
+  }
+
+  bool isOpaque() const { return ConstantSDNodeBits.IsOpaque; }
+};
+
+class ConstantIntSDNode : public ConstantSDNode {
   const ConstantInt *Value;
   friend class SelectionDAG;
-  ConstantSDNode(bool isTarget, bool isOpaque, const ConstantInt *val,
-                 const DebugLoc &DL, EVT VT)
-      : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, 0, DL,
-               getSDVTList(VT)),
+  ConstantIntSDNode(bool isTarget, bool isOpaque, const ConstantInt *val,
+                    const DebugLoc &DL, EVT VT)
+      : ConstantSDNode(isTarget ? ISD::TargetConstant : ISD::Constant, 0, DL,
+                       getSDVTList(VT)),
         Value(val) {
     ConstantSDNodeBits.IsOpaque = isOpaque;
   }
@@ -1350,13 +1365,6 @@
   bool isOne() const { return Value->isOne(); }
   bool isNullValue() const { return Value->isNullValue(); }
   bool isAllOnesValue() const { return Value->isAllOnesValue(); }
-
-  bool isOpaque() const { return ConstantSDNodeBits.IsOpaque; }
-
-  static bool classof(const SDNode *N) {
-    return N->getOpcode() == ISD::Constant ||
-           N->getOpcode() == ISD::TargetConstant;
-  }
 };
 
 class ConstantFPSDNode : public SDNode {
@@ -1612,7 +1620,7 @@
   ///
   /// If passed a non-null UndefElements bitvector, it will resize it to match
   /// the vector width and set the bits where elements are undef.
-  ConstantSDNode *
+  ConstantIntSDNode *
   getConstantSplatNode(BitVector *UndefElements = nullptr) const;
 
   /// \brief Returns the splatted constant FP or null if this is not a constant
Index: llvm/include/llvm/Target/TargetLowering.h
===================================================================
--- llvm/include/llvm/Target/TargetLowering.h
+++ llvm/include/llvm/Target/TargetLowering.h
@@ -2345,7 +2345,7 @@
   SDValue getConstTrueVal(SelectionDAG &DAG, EVT VT, const SDLoc &DL) const;
 
   /// Return if \p N is a True value when extended to \p VT.
-  bool isExtendedTrueVal(const ConstantSDNode *N, EVT VT, bool Signed) const;
+  bool isExtendedTrueVal(const ConstantIntSDNode *N, EVT VT, bool Signed) const;
 
   /// Try to simplify a setcc built with the specified operands and cc. If it is
   /// unable to simplify it, return a null SDValue.
Index: llvm/include/llvm/Target/TargetSelectionDAG.td
===================================================================
--- llvm/include/llvm/Target/TargetSelectionDAG.td
+++ llvm/include/llvm/Target/TargetSelectionDAG.td
@@ -608,10 +608,16 @@
 class SDNodeXForm<SDNode opc, code xformFunction> {
   SDNode Opcode = opc;
   code XFormFunction = xformFunction;
+  bit ConstantInt = 0;
 }
 
 def NOOP_SDNodeXForm : SDNodeXForm<imm, [{}]>;
 
+class ConstIntSDNodeXForm<code xformFunction>
+  : SDNodeXForm<imm, xformFunction> {
+  let ConstantInt = 1;
+}
+
 //===----------------------------------------------------------------------===//
 // PatPred Subclasses.
 //
Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -332,7 +332,7 @@
     SDValue ReassociateOps(unsigned Opc, const SDLoc &DL, SDValue LHS,
                            SDValue RHS);
 
-    SDValue visitShiftByConstant(SDNode *N, ConstantSDNode *Amt);
+    SDValue visitShiftByConstant(SDNode *N, ConstantIntSDNode *Amt);
 
     SDValue foldSelectOfConstants(SDNode *N);
     bool SimplifySelectOps(SDNode *SELECT, SDValue LHS, SDValue RHS);
@@ -443,7 +443,7 @@
     /// the type of the loaded value to be extended.  LoadedVT returns the type
     /// of the original loaded value.  NarrowLoad returns whether the load would
     /// need to be narrowed in order to match.
-    bool isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
+    bool isAndLoadExtLoad(ConstantIntSDNode *AndC, LoadSDNode *LoadN,
                           EVT LoadResultTy, EVT &ExtVT, EVT &LoadedVT,
                           bool &NarrowLoad);
 
@@ -788,13 +788,13 @@
 
 // \brief Returns the SDNode if it is a constant splat BuildVector or constant
 // int.
-static ConstantSDNode *isConstOrConstSplat(SDValue N) {
-  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N))
+static ConstantIntSDNode *isConstOrConstSplat(SDValue N) {
+  if (auto *CN = dyn_cast<ConstantIntSDNode>(N))
     return CN;
 
   if (BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N)) {
     BitVector UndefElements;
-    ConstantSDNode *CN = BV->getConstantSplatNode(&UndefElements);
+    ConstantIntSDNode *CN = BV->getConstantSplatNode(&UndefElements);
 
     // BuildVectors can truncate their operands. Ignore that case here.
     // FIXME: We blindly ignore splats which include undef which is overly
@@ -1512,7 +1512,7 @@
     SDValue N1 = N->getOperand(1);
 
     // Constant operands are canonicalized to RHS.
-    if (isa<ConstantSDNode>(N0) || !isa<ConstantSDNode>(N1)) {
+    if (isa<ConstantIntSDNode>(N0) || !isa<ConstantIntSDNode>(N1)) {
       SDValue Ops[] = {N1, N0};
       SDNode *CSENode = DAG.getNodeIfExists(N->getOpcode(), N->getVTList(), Ops,
                                             N->getFlags());
@@ -1633,10 +1633,10 @@
   return SDValue(N, 0);   // Return N so it doesn't get rechecked!
 }
 
-/// If \p N is a ConstantSDNode with isOpaque() == false return it casted to a
-/// ConstantSDNode pointer else nullptr.
-static ConstantSDNode *getAsNonOpaqueConstant(SDValue N) {
-  ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N);
+/// If \p N is a ConstantIntSDNode with isOpaque() == false return it casted to
+/// a ConstantIntSDNode pointer else nullptr.
+static ConstantIntSDNode *getAsNonOpaqueConstant(SDValue N) {
+  auto *Const = dyn_cast<ConstantIntSDNode>(N);
   return Const != nullptr && !Const->isOpaque() ? Const : nullptr;
 }
 
@@ -1674,9 +1674,9 @@
   if (isNullConstant(N1))
     return N0;
   // fold ((c1-A)+c2) -> (c1+c2)-A
-  if (ConstantSDNode *N1C = getAsNonOpaqueConstant(N1)) {
+  if (ConstantIntSDNode *N1C = getAsNonOpaqueConstant(N1)) {
     if (N0.getOpcode() == ISD::SUB)
-      if (ConstantSDNode *N0C = getAsNonOpaqueConstant(N0.getOperand(0))) {
+      if (ConstantIntSDNode *N0C = getAsNonOpaqueConstant(N0.getOperand(0))) {
         SDLoc DL(N);
         return DAG.getNode(ISD::SUB, DL, VT,
                            DAG.getConstant(N1C->getAPIntValue()+
@@ -1723,7 +1723,7 @@
     SDValue N10 = N1.getOperand(0);
     SDValue N11 = N1.getOperand(1);
 
-    if (isa<ConstantSDNode>(N00) || isa<ConstantSDNode>(N10))
+    if (isa<ConstantIntSDNode>(N00) || isa<ConstantIntSDNode>(N10))
       return DAG.getNode(ISD::SUB, SDLoc(N), VT,
                          DAG.getNode(ISD::ADD, SDLoc(N0), VT, N00, N10),
                          DAG.getNode(ISD::ADD, SDLoc(N1), VT, N01, N11));
@@ -1799,8 +1799,8 @@
                                  SDLoc(N), MVT::Glue));
 
   // canonicalize constant to RHS.
-  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
-  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
+  auto *N0C = dyn_cast<ConstantIntSDNode>(N0);
+  auto *N1C = dyn_cast<ConstantIntSDNode>(N1);
   if (N0C && !N1C)
     return DAG.getNode(ISD::ADDC, SDLoc(N), N->getVTList(), N1, N0);
 
@@ -1834,8 +1834,8 @@
   SDValue CarryIn = N->getOperand(2);
 
   // canonicalize constant to RHS
-  ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
-  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
+  auto *N0C = dyn_cast<ConstantIntSDNode>(N0);
+  auto *N1C = dyn_cast<ConstantIntSDNode>(N1);
   if (N0C && !N1C)
     return DAG.getNode(ISD::ADDE, SDLoc(N), N->getVTList(),
                        N1, N0, CarryIn);
@@ -1886,8 +1886,8 @@
                                       N1.getNode());
   }
 
-  ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
-  ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
+  ConstantIntSDNode *N0C = getAsNonOpaqueConstant(N0);
+  ConstantIntSDNode *N1C = getAsNonOpaqueConstant(N1);
 
   // fold (sub x, c) -> (add x, -c)
   if (N1C) {
@@ -1913,7 +1913,7 @@
 
   // fold C2-(A+C1) -> (C2-C1)-A
   if (N1.getOpcode() == ISD::ADD && N0C) {
-    if (auto *N1C1 = dyn_cast<ConstantSDNode>(N1.getOperand(1).getNode())) {
+    if (auto *N1C1 = dyn_cast<ConstantIntSDNode>(N1.getOperand(1).getNode())) {
       SDValue NewC =
           DAG.getConstant(N0C->getAPIntValue() - N1C1->getAPIntValue(), DL, VT);
       return DAG.getNode(ISD::SUB, DL, VT, NewC, N1.getOperand(0));
@@ -2036,15 +2036,15 @@
     N0IsConst = ISD::isConstantSplatVector(N0.getNode(), ConstValue0);
     N1IsConst = ISD::isConstantSplatVector(N1.getNode(), ConstValue1);
   } else {
-    N0IsConst = isa<ConstantSDNode>(N0);
+    N0IsConst = isa<ConstantIntSDNode>(N0);
     if (N0IsConst) {
-      ConstValue0 = cast<ConstantSDNode>(N0)->getAPIntValue();
-      N0IsOpaqueConst = cast<ConstantSDNode>(N0)->isOpaque();
+      ConstValue0 = cast<ConstantIntSDNode>(N0)->getAPIntValue();
+      N0IsOpaqueConst = cast<ConstantIntSDNode>(N0)->isOpaque();
     }
-    N1IsConst = isa<ConstantSDNode>(N1);
+    N1IsConst = isa<ConstantIntSDNode>(N1);
     if (N1IsConst) {
-      ConstValue1 = cast<ConstantSDNode>(N1)->getAPIntValue();
-      N1IsOpaqueConst = cast<ConstantSDNode>(N1)->isOpaque();
+      ConstValue1 = cast<ConstantIntSDNode>(N1)->getAPIntValue();
+      N1IsOpaqueConst = cast<ConstantIntSDNode>(N1)->isOpaque();
     }
   }
 
@@ -2099,7 +2099,7 @@
   // (mul (shl X, c1), c2) -> (mul X, c2 << c1)
   if (N1IsConst && N0.getOpcode() == ISD::SHL &&
       (ISD::isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
-       isa<ConstantSDNode>(N0.getOperand(1)))) {
+       isa<ConstantIntSDNode>(N0.getOperand(1)))) {
     SDValue C3 = DAG.getNode(ISD::SHL, SDLoc(N), VT, N1, N0.getOperand(1));
     AddToWorklist(C3.getNode());
     return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), C3);
@@ -2112,11 +2112,11 @@
     // Check for both (mul (shl X, C), Y)  and  (mul Y, (shl X, C)).
     if (N0.getOpcode() == ISD::SHL &&
         (ISD::isConstantSplatVector(N0.getOperand(1).getNode(), Val) ||
-         isa<ConstantSDNode>(N0.getOperand(1))) &&
+         isa<ConstantIntSDNode>(N0.getOperand(1))) &&
         N0.getNode()->hasOneUse()) {
       Sh = N0; Y = N1;
     } else if (N1.getOpcode() == ISD::SHL &&
-               isa<ConstantSDNode>(N1.getOperand(1)) &&
+               isa<ConstantIntSDNode>(N1.getOperand(1)) &&
                N1.getNode()->hasOneUse()) {
       Sh = N1; Y = N0;
     }
@@ -2247,8 +2247,8 @@
   SDLoc DL(N);
 
   // fold (sdiv c1, c2) -> c1/c2
-  ConstantSDNode *N0C = isConstOrConstSplat(N0);
-  ConstantSDNode *N1C = isConstOrConstSplat(N1);
+  ConstantIntSDNode *N0C = isConstOrConstSplat(N0);
+  ConstantIntSDNode *N1C = isConstOrConstSplat(N1);
   if (N0C && N1C && !N0C->isOpaque() && !N1C->isOpaque())
     return DAG.FoldConstantArithmetic(ISD::SDIV, DL, VT, N0C, N1C);
   // fold (sdiv X, 1) -> X
@@ -2346,8 +2346,8 @@
   SDLoc DL(N);
 
   // fold (udiv c1, c2) -> c1/c2
-  ConstantSDNode *N0C = isConstOrConstSplat(N0);
-  ConstantSDNode *N1C = isConstOrConstSplat(N1);
+  ConstantIntSDNode *N0C = isConstOrConstSplat(N0);
+  ConstantIntSDNode *N1C = isConstOrConstSplat(N1);
   if (N0C && N1C)
     if (SDValue Folded = DAG.FoldConstantArithmetic(ISD::UDIV, DL, VT,
                                                     N0C, N1C))
@@ -2360,7 +2360,7 @@
 
   // fold (udiv x, (shl c, y)) -> x >>u (log2(c)+y) iff c is power of 2
   if (N1.getOpcode() == ISD::SHL) {
-    if (ConstantSDNode *SHC = getAsNonOpaqueConstant(N1.getOperand(0))) {
+    if (ConstantIntSDNode *SHC = getAsNonOpaqueConstant(N1.getOperand(0))) {
       if (SHC->getAPIntValue().isPowerOf2()) {
         EVT ADDVT = N1.getOperand(1).getValueType();
         SDValue Add = DAG.getNode(ISD::ADD, DL, ADDVT,
@@ -2407,8 +2407,8 @@
   SDLoc DL(N);
 
   // fold (rem c1, c2) -> c1%c2
-  ConstantSDNode *N0C = isConstOrConstSplat(N0);
-  ConstantSDNode *N1C = isConstOrConstSplat(N1);
+  ConstantIntSDNode *N0C = isConstOrConstSplat(N0);
+  ConstantIntSDNode *N1C = isConstOrConstSplat(N1);
   if (N0C && N1C)
     if (SDValue Folded = DAG.FoldConstantArithmetic(Opcode, DL, VT, N0C, N1C))
       return Folded;
@@ -2429,7 +2429,7 @@
     }
     // fold (urem x, (shl pow2, y)) -> (and x, (add (shl pow2, y), -1))
     if (N1.getOpcode() == ISD::SHL) {
-      ConstantSDNode *SHC = getAsNonOpaqueConstant(N1.getOperand(0));
+      ConstantIntSDNode *SHC = getAsNonOpaqueConstant(N1.getOperand(0));
       if (SHC && SHC->getAPIntValue().isPowerOf2()) {
         APInt NegOne = APInt::getAllOnesValue(VT.getSizeInBits());
         SDValue Add =
@@ -2670,7 +2670,7 @@
 
 SDValue DAGCombiner::visitSMULO(SDNode *N) {
   // (smulo x, 2) -> (saddo x, x)
-  if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
+  if (auto *C2 = dyn_cast<ConstantIntSDNode>(N->getOperand(1)))
     if (C2->getAPIntValue() == 2)
       return DAG.getNode(ISD::SADDO, SDLoc(N), N->getVTList(),
                          N->getOperand(0), N->getOperand(0));
@@ -2680,7 +2680,7 @@
 
 SDValue DAGCombiner::visitUMULO(SDNode *N) {
   // (umulo x, 2) -> (uaddo x, x)
-  if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(N->getOperand(1)))
+  if (auto *C2 = dyn_cast<ConstantIntSDNode>(N->getOperand(1)))
     if (C2->getAPIntValue() == 2)
       return DAG.getNode(ISD::UADDO, SDLoc(N), N->getVTList(),
                          N->getOperand(0), N->getOperand(0));
@@ -2699,8 +2699,8 @@
       return FoldedVOp;
 
   // fold (add c1, c2) -> c1+c2
-  ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
-  ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
+  ConstantIntSDNode *N0C = getAsNonOpaqueConstant(N0);
+  ConstantIntSDNode *N1C = getAsNonOpaqueConstant(N1);
   if (N0C && N1C)
     return DAG.FoldConstantArithmetic(N->getOpcode(), SDLoc(N), VT, N0C, N1C);
 
@@ -2882,7 +2882,7 @@
     ISD::CondCode Op0 = cast<CondCodeSDNode>(CC0)->get();
     ISD::CondCode Op1 = cast<CondCodeSDNode>(CC1)->get();
 
-    if (LR == RR && isa<ConstantSDNode>(LR) && Op0 == Op1 &&
+    if (LR == RR && isa<ConstantIntSDNode>(LR) && Op0 == Op1 &&
         LL.getValueType().isInteger()) {
       // fold (and (seteq X, 0), (seteq Y, 0)) -> (seteq (or X, Y), 0)
       if (isNullConstant(LR) && Op1 == ISD::SETEQ) {
@@ -2918,10 +2918,10 @@
       }
     }
     // Simplify (and (setne X, 0), (setne X, -1)) -> (setuge (add X, 1), 2)
-    if (LL == RL && isa<ConstantSDNode>(LR) && isa<ConstantSDNode>(RR) &&
-        Op0 == Op1 && LL.getValueType().isInteger() &&
-      Op0 == ISD::SETNE && ((isNullConstant(LR) && isAllOnesConstant(RR)) ||
-                            (isAllOnesConstant(LR) && isNullConstant(RR)))) {
+    if (LL == RL && isa<ConstantIntSDNode>(LR) && isa<ConstantIntSDNode>(RR) &&
+        Op0 == Op1 && LL.getValueType().isInteger() && Op0 == ISD::SETNE &&
+        ((isNullConstant(LR) && isAllOnesConstant(RR)) ||
+         (isAllOnesConstant(LR) && isNullConstant(RR)))) {
       EVT CCVT = getSetCCResultType(LL.getValueType());
       if (VT == CCVT || (!LegalOperations && VT == MVT::i1)) {
         SDLoc DL(N0);
@@ -2957,14 +2957,14 @@
 
   if (N0.getOpcode() == ISD::ADD && N1.getOpcode() == ISD::SRL &&
       VT.getSizeInBits() <= 64) {
-    if (ConstantSDNode *ADDI = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
+    if (auto *ADDI = dyn_cast<ConstantIntSDNode>(N0.getOperand(1))) {
       APInt ADDC = ADDI->getAPIntValue();
       if (!TLI.isLegalAddImmediate(ADDC.getSExtValue())) {
         // Look for (and (add x, c1), (lshr y, c2)). If C1 wasn't a legal
         // immediate for an add, but it is legal if its top c2 bits are set,
         // transform the ADD so the immediate doesn't need to be materialized
         // in a register.
-        if (ConstantSDNode *SRLI = dyn_cast<ConstantSDNode>(N1.getOperand(1))) {
+        if (auto *SRLI = dyn_cast<ConstantIntSDNode>(N1.getOperand(1))) {
           APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
                                              SRLI->getZExtValue());
           if (DAG.MaskedValueIsZero(N0.getOperand(1), Mask)) {
@@ -2988,8 +2988,8 @@
   // (and (srl i64:x, K), KMask) ->
   //   (i64 zero_extend (and (srl (i32 (trunc i64:x)), K)), KMask)
   if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
-    if (ConstantSDNode *CAnd = dyn_cast<ConstantSDNode>(N1)) {
-      if (ConstantSDNode *CShift = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
+    if (auto *CAnd = dyn_cast<ConstantIntSDNode>(N1)) {
+      if (auto *CShift = dyn_cast<ConstantIntSDNode>(N0.getOperand(1))) {
         unsigned Size = VT.getSizeInBits();
         const APInt &AndMask = CAnd->getAPIntValue();
         unsigned ShiftBits = CShift->getZExtValue();
@@ -3031,7 +3031,7 @@
   return SDValue();
 }
 
-bool DAGCombiner::isAndLoadExtLoad(ConstantSDNode *AndC, LoadSDNode *LoadN,
+bool DAGCombiner::isAndLoadExtLoad(ConstantIntSDNode *AndC, LoadSDNode *LoadN,
                                    EVT LoadResultTy, EVT &ExtVT, EVT &LoadedVT,
                                    bool &NarrowLoad) {
   uint32_t ActiveBits = AndC->getAPIntValue().getActiveBits();
@@ -3099,8 +3099,8 @@
   }
 
   // fold (and c1, c2) -> c1&c2
-  ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
-  ConstantSDNode *N1C = isConstOrConstSplat(N1);
+  ConstantIntSDNode *N0C = getAsNonOpaqueConstant(N0);
+  ConstantIntSDNode *N1C = isConstOrConstSplat(N1);
   if (N0C && N1C && !N1C->isOpaque())
     return DAG.FoldConstantArithmetic(ISD::AND, SDLoc(N), VT, N0C, N1C);
   // canonicalize constant to RHS
@@ -3120,7 +3120,7 @@
     return RAND;
   // fold (and (or x, C), D) -> D if (C & D) == D
   if (N1C && N0.getOpcode() == ISD::OR)
-    if (ConstantSDNode *ORI = isConstOrConstSplat(N0.getOperand(1)))
+    if (ConstantIntSDNode *ORI = isConstOrConstSplat(N0.getOperand(1)))
       if ((ORI->getAPIntValue() & N1C->getAPIntValue()) == N1C->getAPIntValue())
         return N1;
   // fold (and (any_ext V), c) -> (zero_ext V) if 'and' only clears top bits.
@@ -3160,7 +3160,7 @@
     // This can be a pure constant or a vector splat, in which case we treat the
     // vector as a scalar and use the splat value.
     APInt Constant = APInt::getNullValue(1);
-    if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
+    if (const auto *C = dyn_cast<ConstantIntSDNode>(N1)) {
       Constant = C->getAPIntValue();
     } else if (BuildVectorSDNode *Vector = dyn_cast<BuildVectorSDNode>(N1)) {
       APInt SplatValue, SplatUndef;
@@ -3322,7 +3322,7 @@
   // Note: the SimplifyDemandedBits fold below can make an information-losing
   // transform, and then we have no way to find this better fold.
   if (N1C && N1C->isOne() && N0.getOpcode() == ISD::SUB) {
-    ConstantSDNode *SubLHS = isConstOrConstSplat(N0.getOperand(0));
+    ConstantIntSDNode *SubLHS = isConstOrConstSplat(N0.getOperand(0));
     SDValue SubRHS = N0.getOperand(1);
     if (SubLHS && SubLHS->isNullValue()) {
       if (SubRHS.getOpcode() == ISD::ZERO_EXTEND &&
@@ -3410,7 +3410,7 @@
   if (N0.getOpcode() == ISD::AND) {
     if (!N0.getNode()->hasOneUse())
       return SDValue();
-    ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
+    auto *N01C = dyn_cast<ConstantIntSDNode>(N0.getOperand(1));
     if (!N01C || N01C->getZExtValue() != 0xFF00)
       return SDValue();
     N0 = N0.getOperand(0);
@@ -3420,7 +3420,7 @@
   if (N1.getOpcode() == ISD::AND) {
     if (!N1.getNode()->hasOneUse())
       return SDValue();
-    ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
+    auto *N11C = dyn_cast<ConstantIntSDNode>(N1.getOperand(1));
     if (!N11C || N11C->getZExtValue() != 0xFF)
       return SDValue();
     N1 = N1.getOperand(0);
@@ -3434,8 +3434,8 @@
   if (!N0.getNode()->hasOneUse() || !N1.getNode()->hasOneUse())
     return SDValue();
 
-  ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
-  ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
+  auto *N01C = dyn_cast<ConstantIntSDNode>(N0.getOperand(1));
+  auto *N11C = dyn_cast<ConstantIntSDNode>(N1.getOperand(1));
   if (!N01C || !N11C)
     return SDValue();
   if (N01C->getZExtValue() != 8 || N11C->getZExtValue() != 8)
@@ -3446,7 +3446,7 @@
   if (!LookPassAnd0 && N00.getOpcode() == ISD::AND) {
     if (!N00.getNode()->hasOneUse())
       return SDValue();
-    ConstantSDNode *N001C = dyn_cast<ConstantSDNode>(N00.getOperand(1));
+    auto *N001C = dyn_cast<ConstantIntSDNode>(N00.getOperand(1));
     if (!N001C || N001C->getZExtValue() != 0xFF)
       return SDValue();
     N00 = N00.getOperand(0);
@@ -3457,7 +3457,7 @@
   if (!LookPassAnd1 && N10.getOpcode() == ISD::AND) {
     if (!N10.getNode()->hasOneUse())
       return SDValue();
-    ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N10.getOperand(1));
+    auto *N101C = dyn_cast<ConstantIntSDNode>(N10.getOperand(1));
     if (!N101C || N101C->getZExtValue() != 0xFF00)
       return SDValue();
     N10 = N10.getOperand(0);
@@ -3509,7 +3509,7 @@
   if (Opc != ISD::AND && Opc != ISD::SHL && Opc != ISD::SRL)
     return false;
 
-  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N.getOperand(1));
+  auto *N1C = dyn_cast<ConstantIntSDNode>(N.getOperand(1));
   if (!N1C)
     return false;
 
@@ -3531,7 +3531,7 @@
       // (x >> 8) & 0xff0000
       if (N0.getOpcode() != ISD::SRL)
         return false;
-      ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
+      auto *C = dyn_cast<ConstantIntSDNode>(N0.getOperand(1));
       if (!C || C->getZExtValue() != 8)
         return false;
     } else {
@@ -3539,7 +3539,7 @@
       // (x << 8) & 0xff000000
       if (N0.getOpcode() != ISD::SHL)
         return false;
-      ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
+      auto *C = dyn_cast<ConstantIntSDNode>(N0.getOperand(1));
       if (!C || C->getZExtValue() != 8)
         return false;
     }
@@ -3548,7 +3548,7 @@
     // (x & 0xff0000) << 8
     if (Num != 0 && Num != 2)
       return false;
-    ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
+    auto *C = dyn_cast<ConstantIntSDNode>(N.getOperand(1));
     if (!C || C->getZExtValue() != 8)
       return false;
   } else { // Opc == ISD::SRL
@@ -3556,7 +3556,7 @@
     // (x & 0xff000000) >> 8
     if (Num != 1 && Num != 3)
       return false;
-    ConstantSDNode *C = dyn_cast<ConstantSDNode>(N.getOperand(1));
+    auto *C = dyn_cast<ConstantIntSDNode>(N.getOperand(1));
     if (!C || C->getZExtValue() != 8)
       return false;
   }
@@ -3713,10 +3713,10 @@
       (N0.getNode()->hasOneUse() || N1.getNode()->hasOneUse())) {
     // We can only do this xform if we know that bits from X that are set in C2
     // but not in C1 are already zero.  Likewise for Y.
-    if (const ConstantSDNode *N0O1C =
-        getAsNonOpaqueConstant(N0.getOperand(1))) {
-      if (const ConstantSDNode *N1O1C =
-          getAsNonOpaqueConstant(N1.getOperand(1))) {
+    if (const ConstantIntSDNode *N0O1C =
+            getAsNonOpaqueConstant(N0.getOperand(1))) {
+      if (const ConstantIntSDNode *N1O1C =
+              getAsNonOpaqueConstant(N1.getOperand(1))) {
         // We can only do this xform if we know that bits from X that are set in
         // C2 but not in C1 are already zero.  Likewise for Y.
         const APInt &LHSMask = N0O1C->getAPIntValue();
@@ -3845,8 +3845,8 @@
   }
 
   // fold (or c1, c2) -> c1|c2
-  ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
-  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
+  ConstantIntSDNode *N0C = getAsNonOpaqueConstant(N0);
+  auto *N1C = dyn_cast<ConstantIntSDNode>(N1);
   if (N0C && N1C && !N1C->isOpaque())
     return DAG.FoldConstantArithmetic(ISD::OR, SDLoc(N), VT, N0C, N1C);
   // canonicalize constant to RHS
@@ -3878,8 +3878,8 @@
   // Canonicalize (or (and X, c1), c2) -> (and (or X, c2), c1|c2)
   // iff (c1 & c2) == 0.
   if (N1C && N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
-             isa<ConstantSDNode>(N0.getOperand(1))) {
-    ConstantSDNode *C1 = cast<ConstantSDNode>(N0.getOperand(1));
+      isa<ConstantIntSDNode>(N0.getOperand(1))) {
+    auto *C1 = cast<ConstantIntSDNode>(N0.getOperand(1));
     if ((C1->getAPIntValue() & N1C->getAPIntValue()) != 0) {
       if (SDValue COR = DAG.FoldConstantArithmetic(ISD::OR, SDLoc(N1), VT,
                                                    N1C, C1))
@@ -3968,7 +3968,7 @@
   // Below, Mask == EltSize - 1 when using [A] and is all-ones otherwise.
   unsigned MaskLoBits = 0;
   if (Neg.getOpcode() == ISD::AND && isPowerOf2_64(EltSize)) {
-    if (ConstantSDNode *NegC = isConstOrConstSplat(Neg.getOperand(1))) {
+    if (ConstantIntSDNode *NegC = isConstOrConstSplat(Neg.getOperand(1))) {
       if (NegC->getAPIntValue() == EltSize - 1) {
         Neg = Neg.getOperand(0);
         MaskLoBits = Log2_64(EltSize);
@@ -3979,7 +3979,7 @@
   // Check whether Neg has the form (sub NegC, NegOp1) for some NegC and NegOp1.
   if (Neg.getOpcode() != ISD::SUB)
     return false;
-  ConstantSDNode *NegC = isConstOrConstSplat(Neg.getOperand(0));
+  ConstantIntSDNode *NegC = isConstOrConstSplat(Neg.getOperand(0));
   if (!NegC)
     return false;
   SDValue NegOp1 = Neg.getOperand(1);
@@ -3987,7 +3987,7 @@
   // On the RHS of [A], if Pos is Pos' & (EltSize - 1), just replace Pos with
   // Pos'.  The truncation is redundant for the purpose of the equality.
   if (MaskLoBits && Pos.getOpcode() == ISD::AND)
-    if (ConstantSDNode *PosC = isConstOrConstSplat(Pos.getOperand(1)))
+    if (ConstantIntSDNode *PosC = isConstOrConstSplat(Pos.getOperand(1)))
       if (PosC->getAPIntValue() == EltSize - 1)
         Pos = Pos.getOperand(0);
 
@@ -4014,7 +4014,7 @@
   //                NegC & Mask == (EltSize - PosC) & Mask
   //             EltSize & Mask == (NegC + PosC) & Mask
   else if (Pos.getOpcode() == ISD::ADD && Pos.getOperand(0) == NegOp1) {
-    if (ConstantSDNode *PosC = isConstOrConstSplat(Pos.getOperand(1)))
+    if (ConstantIntSDNode *PosC = isConstOrConstSplat(Pos.getOperand(1)))
       Width = PosC->getAPIntValue() + NegC->getAPIntValue();
     else
       return false;
@@ -4191,8 +4191,8 @@
   if (N1.isUndef())
     return N1;
   // fold (xor c1, c2) -> c1^c2
-  ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
-  ConstantSDNode *N1C = getAsNonOpaqueConstant(N1);
+  ConstantIntSDNode *N0C = getAsNonOpaqueConstant(N0);
+  ConstantIntSDNode *N1C = getAsNonOpaqueConstant(N1);
   if (N0C && N1C)
     return DAG.FoldConstantArithmetic(ISD::XOR, SDLoc(N), VT, N0C, N1C);
   // canonicalize constant to RHS
@@ -4255,7 +4255,7 @@
   if (isAllOnesConstant(N1) &&
       (N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
     SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
-    if (isa<ConstantSDNode>(RHS) || isa<ConstantSDNode>(LHS)) {
+    if (isa<ConstantIntSDNode>(RHS) || isa<ConstantIntSDNode>(LHS)) {
       unsigned NewOpcode = N0.getOpcode() == ISD::AND ? ISD::OR : ISD::AND;
       LHS = DAG.getNode(ISD::XOR, SDLoc(LHS), VT, LHS, N1); // LHS = ~LHS
       RHS = DAG.getNode(ISD::XOR, SDLoc(RHS), VT, RHS, N1); // RHS = ~RHS
@@ -4273,13 +4273,15 @@
   }
   // fold (xor (xor x, c1), c2) -> (xor x, (xor c1, c2))
   if (N1C && N0.getOpcode() == ISD::XOR) {
-    if (const ConstantSDNode *N00C = getAsNonOpaqueConstant(N0.getOperand(0))) {
+    if (const ConstantIntSDNode *N00C =
+            getAsNonOpaqueConstant(N0.getOperand(0))) {
       SDLoc DL(N);
       return DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(1),
                          DAG.getConstant(N1C->getAPIntValue() ^
                                          N00C->getAPIntValue(), DL, VT));
     }
-    if (const ConstantSDNode *N01C = getAsNonOpaqueConstant(N0.getOperand(1))) {
+    if (const ConstantIntSDNode *N01C =
+            getAsNonOpaqueConstant(N0.getOperand(1))) {
       SDLoc DL(N);
       return DAG.getNode(ISD::XOR, DL, VT, N0.getOperand(0),
                          DAG.getConstant(N1C->getAPIntValue() ^
@@ -4330,7 +4332,7 @@
 
 /// Handle transforms common to the three shifts, when the shift amount is a
 /// constant.
-SDValue DAGCombiner::visitShiftByConstant(SDNode *N, ConstantSDNode *Amt) {
+SDValue DAGCombiner::visitShiftByConstant(SDNode *N, ConstantIntSDNode *Amt) {
   SDNode *LHS = N->getOperand(0).getNode();
   if (!LHS->hasOneUse()) return SDValue();
 
@@ -4357,7 +4359,7 @@
   }
 
   // We require the RHS of the binop to be a constant and not opaque as well.
-  ConstantSDNode *BinOpCst = getAsNonOpaqueConstant(LHS->getOperand(1));
+  ConstantIntSDNode *BinOpCst = getAsNonOpaqueConstant(LHS->getOperand(1));
   if (!BinOpCst) return SDValue();
 
   // FIXME: disable this unless the input to the binop is a shift by a constant.
@@ -4369,7 +4371,7 @@
   if ((BinOpLHSVal->getOpcode() != ISD::SHL &&
        BinOpLHSVal->getOpcode() != ISD::SRA &&
        BinOpLHSVal->getOpcode() != ISD::SRL) ||
-      !isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
+      !isa<ConstantIntSDNode>(BinOpLHSVal->getOperand(1)))
     return SDValue();
 
   EVT VT = N->getValueType(0);
@@ -4391,7 +4393,7 @@
   SDValue NewRHS = DAG.getNode(N->getOpcode(), SDLoc(LHS->getOperand(1)),
                                N->getValueType(0),
                                LHS->getOperand(1), N->getOperand(1));
-  assert(isa<ConstantSDNode>(NewRHS) && "Folding was not successful!");
+  assert(isa<ConstantIntSDNode>(NewRHS) && "Folding was not successful!");
 
   // Create the new shift.
   SDValue NewShift = DAG.getNode(N->getOpcode(),
@@ -4410,7 +4412,7 @@
   if (N->hasOneUse() && N->getOperand(0).hasOneUse()) {
     SDValue N01 = N->getOperand(0).getOperand(1);
 
-    if (ConstantSDNode *N01C = isConstOrConstSplat(N01)) {
+    if (ConstantIntSDNode *N01C = isConstOrConstSplat(N01)) {
       if (!N01C->isOpaque()) {
         EVT TruncVT = N->getValueType(0);
         SDValue N00 = N->getOperand(0).getOperand(0);
@@ -4447,7 +4449,7 @@
   unsigned OpSizeInBits = VT.getScalarSizeInBits();
 
   // fold vector ops
-  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
+  auto *N1C = dyn_cast<ConstantIntSDNode>(N1);
   if (VT.isVector()) {
     if (SDValue FoldedVOp = SimplifyVBinOp(N))
       return FoldedVOp;
@@ -4475,7 +4477,7 @@
   }
 
   // fold (shl c1, c2) -> c1<<c2
-  ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
+  ConstantIntSDNode *N0C = getAsNonOpaqueConstant(N0);
   if (N0C && N1C && !N1C->isOpaque())
     return DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N), VT, N0C, N1C);
   // fold (shl 0, x) -> 0
@@ -4506,7 +4508,7 @@
 
   // fold (shl (shl x, c1), c2) -> 0 or (shl x, (add c1, c2))
   if (N1C && N0.getOpcode() == ISD::SHL) {
-    if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
+    if (ConstantIntSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
       SDLoc DL(N);
       APInt c1 = N0C1->getAPIntValue();
       APInt c2 = N1C->getAPIntValue();
@@ -4532,7 +4534,7 @@
               N0.getOpcode() == ISD::SIGN_EXTEND) &&
       N0.getOperand(0).getOpcode() == ISD::SHL) {
     SDValue N0Op0 = N0.getOperand(0);
-    if (ConstantSDNode *N0Op0C1 = isConstOrConstSplat(N0Op0.getOperand(1))) {
+    if (ConstantIntSDNode *N0Op0C1 = isConstOrConstSplat(N0Op0.getOperand(1))) {
       APInt c1 = N0Op0C1->getAPIntValue();
       APInt c2 = N1C->getAPIntValue();
       zeroExtendToMatch(c1, c2, 1 /* Overflow Bit */);
@@ -4559,7 +4561,7 @@
   if (N1C && N0.getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse() &&
       N0.getOperand(0).getOpcode() == ISD::SRL) {
     SDValue N0Op0 = N0.getOperand(0);
-    if (ConstantSDNode *N0Op0C1 = isConstOrConstSplat(N0Op0.getOperand(1))) {
+    if (ConstantIntSDNode *N0Op0C1 = isConstOrConstSplat(N0Op0.getOperand(1))) {
       if (N0Op0C1->getAPIntValue().ult(VT.getScalarSizeInBits())) {
         uint64_t c1 = N0Op0C1->getZExtValue();
         uint64_t c2 = N1C->getZExtValue();
@@ -4581,7 +4583,7 @@
   // fold (shl (sr[la] exact X,  C1), C2) -> (sr[la] X, (C2-C1)) if C1  > C2
   if (N1C && (N0.getOpcode() == ISD::SRL || N0.getOpcode() == ISD::SRA) &&
       cast<BinaryWithFlagsSDNode>(N0)->Flags.hasExact()) {
-    if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
+    if (ConstantIntSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
       uint64_t C1 = N0C1->getZExtValue();
       uint64_t C2 = N1C->getZExtValue();
       SDLoc DL(N);
@@ -4598,7 +4600,7 @@
   // Only fold this if the inner shift has no other uses -- if it does, folding
   // this will increase the total number of instructions.
   if (N1C && N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
-    if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
+    if (ConstantIntSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
       uint64_t c1 = N0C1->getZExtValue();
       if (c1 < OpSizeInBits) {
         uint64_t c2 = N1C->getZExtValue();
@@ -4638,7 +4640,7 @@
   // into a shift.
   APInt Val;
   if (N1C && N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse() &&
-      (isa<ConstantSDNode>(N0.getOperand(1)) ||
+      (isa<ConstantIntSDNode>(N0.getOperand(1)) ||
        ISD::isConstantSplatVector(N0.getOperand(1).getNode(), Val))) {
     SDValue Shl0 = DAG.getNode(ISD::SHL, SDLoc(N0), VT, N0.getOperand(0), N1);
     SDValue Shl1 = DAG.getNode(ISD::SHL, SDLoc(N1), VT, N0.getOperand(1), N1);
@@ -4647,7 +4649,7 @@
 
   // fold (shl (mul x, c1), c2) -> (mul x, c1 << c2)
   if (N1C && N0.getOpcode() == ISD::MUL && N0.getNode()->hasOneUse()) {
-    if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
+    if (ConstantIntSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
       if (SDValue Folded =
               DAG.FoldConstantArithmetic(ISD::SHL, SDLoc(N1), VT, N0C1, N1C))
         return DAG.getNode(ISD::MUL, SDLoc(N), VT, N0.getOperand(0), Folded);
@@ -4668,7 +4670,7 @@
   unsigned OpSizeInBits = VT.getScalarSizeInBits();
 
   // fold vector ops
-  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
+  auto *N1C = dyn_cast<ConstantIntSDNode>(N1);
   if (VT.isVector()) {
     if (SDValue FoldedVOp = SimplifyVBinOp(N))
       return FoldedVOp;
@@ -4677,7 +4679,7 @@
   }
 
   // fold (sra c1, c2) -> (sra c1, c2)
-  ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
+  ConstantIntSDNode *N0C = getAsNonOpaqueConstant(N0);
   if (N0C && N1C && !N1C->isOpaque())
     return DAG.FoldConstantArithmetic(ISD::SRA, SDLoc(N), VT, N0C, N1C);
   // fold (sra 0, x) -> 0
@@ -4708,7 +4710,7 @@
 
   // fold (sra (sra x, c1), c2) -> (sra x, (add c1, c2))
   if (N1C && N0.getOpcode() == ISD::SRA) {
-    if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
+    if (ConstantIntSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
       SDLoc DL(N);
       APInt c1 = N0C1->getAPIntValue();
       APInt c2 = N1C->getAPIntValue();
@@ -4731,7 +4733,7 @@
   // code.
   if (N0.getOpcode() == ISD::SHL && N1C) {
     // Get the two constanst of the shifts, CN0 = m, CN = n.
-    const ConstantSDNode *N01C = isConstOrConstSplat(N0.getOperand(1));
+    const ConstantIntSDNode *N01C = isConstOrConstSplat(N0.getOperand(1));
     if (N01C) {
       LLVMContext &Ctx = *DAG.getContext();
       // Determine what the truncate's result bitsize and type would be.
@@ -4781,7 +4783,8 @@
       N0.getOperand(0).getOperand(1).hasOneUse() &&
       N1C) {
     SDValue N0Op0 = N0.getOperand(0);
-    if (ConstantSDNode *LargeShift = isConstOrConstSplat(N0Op0.getOperand(1))) {
+    if (ConstantIntSDNode *LargeShift =
+            isConstOrConstSplat(N0Op0.getOperand(1))) {
       unsigned LargeShiftVal = LargeShift->getZExtValue();
       EVT LargeVT = N0Op0.getValueType();
 
@@ -4820,7 +4823,7 @@
   unsigned OpSizeInBits = VT.getScalarSizeInBits();
 
   // fold vector ops
-  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
+  auto *N1C = dyn_cast<ConstantIntSDNode>(N1);
   if (VT.isVector()) {
     if (SDValue FoldedVOp = SimplifyVBinOp(N))
       return FoldedVOp;
@@ -4829,7 +4832,7 @@
   }
 
   // fold (srl c1, c2) -> c1 >>u c2
-  ConstantSDNode *N0C = getAsNonOpaqueConstant(N0);
+  ConstantIntSDNode *N0C = getAsNonOpaqueConstant(N0);
   if (N0C && N1C && !N1C->isOpaque())
     return DAG.FoldConstantArithmetic(ISD::SRL, SDLoc(N), VT, N0C, N1C);
   // fold (srl 0, x) -> 0
@@ -4848,7 +4851,7 @@
 
   // fold (srl (srl x, c1), c2) -> 0 or (srl x, (add c1, c2))
   if (N1C && N0.getOpcode() == ISD::SRL) {
-    if (ConstantSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
+    if (ConstantIntSDNode *N0C1 = isConstOrConstSplat(N0.getOperand(1))) {
       SDLoc DL(N);
       APInt c1 = N0C1->getAPIntValue();
       APInt c2 = N1C->getAPIntValue();
@@ -4867,9 +4870,9 @@
   // fold (srl (trunc (srl x, c1)), c2) -> 0 or (trunc (srl x, (add c1, c2)))
   if (N1C && N0.getOpcode() == ISD::TRUNCATE &&
       N0.getOperand(0).getOpcode() == ISD::SRL &&
-      isa<ConstantSDNode>(N0.getOperand(0)->getOperand(1))) {
-    uint64_t c1 =
-      cast<ConstantSDNode>(N0.getOperand(0)->getOperand(1))->getZExtValue();
+      isa<ConstantIntSDNode>(N0.getOperand(0)->getOperand(1))) {
+    uint64_t c1 = cast<ConstantIntSDNode>(N0.getOperand(0)->getOperand(1))
+                      ->getZExtValue();
     uint64_t c2 = N1C->getZExtValue();
     EVT InnerShiftVT = N0.getOperand(0).getValueType();
     EVT ShiftCountVT = N0.getOperand(0)->getOperand(1).getValueType();
@@ -5173,7 +5176,7 @@
   // fold (select C, X, X) -> X
   if (N1 == N2)
     return N1;
-  if (const ConstantSDNode *N0C = dyn_cast<const ConstantSDNode>(N0)) {
+  if (const ConstantIntSDNode *N0C = dyn_cast<const ConstantIntSDNode>(N0)) {
     // fold (select true, X, Y) -> X
     // fold (select false, X, Y) -> Y
     return !N0C->isNullValue() ? N1 : N2;
@@ -5290,7 +5293,7 @@
   // select (xor Cond, 0), X, Y -> selext Cond, X, Y
   if (VT0 == MVT::i1) {
     if (N0->getOpcode() == ISD::XOR) {
-      if (auto *C = dyn_cast<ConstantSDNode>(N0->getOperand(1))) {
+      if (auto *C = dyn_cast<ConstantIntSDNode>(N0->getOperand(1))) {
         SDValue Cond0 = N0->getOperand(0);
         if (C->isOne())
           return DAG.getNode(ISD::SELECT, SDLoc(N), N1.getValueType(),
@@ -5355,7 +5358,7 @@
 }
 
 // This function assumes all the vselect's arguments are CONCAT_VECTOR
-// nodes and that the condition is a BV of ConstantSDNodes (or undefs).
+// nodes and that the condition is a BV of ConstantIntSDNodes (or undefs).
 static SDValue ConvertSelectToConcatVector(SDNode *N, SelectionDAG &DAG) {
   SDLoc DL(N);
   SDValue Cond = N->getOperand(0);
@@ -5377,25 +5380,25 @@
   // Skip BV elements until we find one that's not an UNDEF
   // After we find an UNDEF element, keep looping until we get to half the
   // length of the BV and see if all the non-undef nodes are the same.
-  ConstantSDNode *BottomHalf = nullptr;
+  ConstantIntSDNode *BottomHalf = nullptr;
   for (int i = 0; i < NumElems / 2; ++i) {
     if (Cond->getOperand(i)->isUndef())
       continue;
 
     if (BottomHalf == nullptr)
-      BottomHalf = cast<ConstantSDNode>(Cond.getOperand(i));
+      BottomHalf = cast<ConstantIntSDNode>(Cond.getOperand(i));
     else if (Cond->getOperand(i).getNode() != BottomHalf)
       return SDValue();
   }
 
   // Do the same for the second half of the BuildVector
-  ConstantSDNode *TopHalf = nullptr;
+  ConstantIntSDNode *TopHalf = nullptr;
   for (int i = NumElems / 2; i < NumElems; ++i) {
     if (Cond->getOperand(i)->isUndef())
       continue;
 
     if (TopHalf == nullptr)
-      TopHalf = cast<ConstantSDNode>(Cond.getOperand(i));
+      TopHalf = cast<ConstantIntSDNode>(Cond.getOperand(i));
     else if (Cond->getOperand(i).getNode() != TopHalf)
       return SDValue();
   }
@@ -5787,7 +5790,7 @@
   // and addressed.
   if (N1.getOpcode() == ISD::CONCAT_VECTORS &&
       N2.getOpcode() == ISD::CONCAT_VECTORS &&
-      ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) {
+      ISD::isBuildVectorOfConstantIntSDNodes(N0.getNode())) {
     if (SDValue CV = ConvertSelectToConcatVector(N, DAG))
       return CV;
   }
@@ -5812,7 +5815,7 @@
                                   CC, SDLoc(N), false)) {
     AddToWorklist(SCC.getNode());
 
-    if (ConstantSDNode *SCCC = dyn_cast<ConstantSDNode>(SCC.getNode())) {
+    if (auto *SCCC = dyn_cast<ConstantIntSDNode>(SCC.getNode())) {
       if (!SCCC->isNullValue())
         return N2;    // cond always true -> true val
       else
@@ -5856,7 +5859,7 @@
   return SDValue();
 }
 
-/// Try to fold a sext/zext/aext dag node into a ConstantSDNode or
+/// Try to fold a sext/zext/aext dag node into a ConstantIntSDNode or
 /// a build_vector of constants.
 /// This function is called by the DAGCombiner when visiting sext/zext/aext
 /// dag nodes (see for example method DAGCombiner::visitSIGN_EXTEND).
@@ -5877,7 +5880,7 @@
   // fold (sext c1) -> c1
   // fold (zext c1) -> c1
   // fold (aext c1) -> c1
-  if (isa<ConstantSDNode>(N0))
+  if (isa<ConstantIntSDNode>(N0))
     return DAG.getNode(Opcode, SDLoc(N), VT, N0).getNode();
 
   // fold (sext (build_vector AllConstants) -> (build_vector AllConstants)
@@ -5885,8 +5888,8 @@
   // fold (aext (build_vector AllConstants) -> (build_vector AllConstants)
   EVT SVT = VT.getScalarType();
   if (!(VT.isVector() &&
-      (!LegalTypes || (!LegalOperations && TLI.isTypeLegal(SVT))) &&
-      ISD::isBuildVectorOfConstantSDNodes(N0.getNode())))
+        (!LegalTypes || (!LegalOperations && TLI.isTypeLegal(SVT))) &&
+        ISD::isBuildVectorOfConstantIntSDNodes(N0.getNode())))
     return nullptr;
 
   // We can fold this node into a build_vector.
@@ -5906,7 +5909,7 @@
     SDLoc DL(Op);
     // Get the constant value and if needed trunc it to the size of the type.
     // Nodes like build_vector might have constants wider than the scalar type.
-    APInt C = cast<ConstantSDNode>(Op)->getAPIntValue().zextOrTrunc(EVTBits);
+    APInt C = cast<ConstantIntSDNode>(Op)->getAPIntValue().zextOrTrunc(EVTBits);
     if (Opcode == ISD::SIGN_EXTEND || Opcode == ISD::SIGN_EXTEND_VECTOR_INREG)
       Elts.push_back(DAG.getConstant(C.sext(VTBits), DL, SVT));
     else
@@ -5945,7 +5948,7 @@
         SDValue UseOp = User->getOperand(i);
         if (UseOp == N0)
           continue;
-        if (!isa<ConstantSDNode>(UseOp))
+        if (!isa<ConstantIntSDNode>(UseOp))
           return false;
         Add = true;
       }
@@ -6235,7 +6238,7 @@
                                          LN0->getChain(), LN0->getBasePtr(),
                                          LN0->getMemoryVT(),
                                          LN0->getMemOperand());
-        APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
+        APInt Mask = cast<ConstantIntSDNode>(N0.getOperand(1))->getAPIntValue();
         Mask = Mask.sext(VT.getSizeInBits());
         SDLoc DL(N);
         SDValue And = DAG.getNode(N0.getOpcode(), DL, VT,
@@ -6477,7 +6480,7 @@
     } else if (X.getValueType().bitsGT(VT)) {
       X = DAG.getNode(ISD::TRUNCATE, SDLoc(X), VT, X);
     }
-    APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
+    APInt Mask = cast<ConstantIntSDNode>(N0.getOperand(1))->getAPIntValue();
     Mask = Mask.zext(VT.getSizeInBits());
     SDLoc DL(N);
     return DAG.getNode(ISD::AND, DL, VT,
@@ -6535,7 +6538,7 @@
       SmallVector<SDNode*, 4> SetCCs;
       if (!N0.hasOneUse()) {
         if (N0.getOpcode() == ISD::AND) {
-          auto *AndC = cast<ConstantSDNode>(N0.getOperand(1));
+          auto *AndC = cast<ConstantIntSDNode>(N0.getOperand(1));
           auto NarrowLoad = false;
           EVT LoadResultTy = AndC->getValueType(0);
           EVT ExtVT, LoadedVT;
@@ -6552,7 +6555,7 @@
                                          LN0->getChain(), LN0->getBasePtr(),
                                          LN0->getMemoryVT(),
                                          LN0->getMemOperand());
-        APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
+        APInt Mask = cast<ConstantIntSDNode>(N0.getOperand(1))->getAPIntValue();
         Mask = Mask.zext(VT.getSizeInBits());
         SDLoc DL(N);
         SDValue And = DAG.getNode(N0.getOpcode(), DL, VT,
@@ -6637,11 +6640,10 @@
 
   // (zext (shl (zext x), cst)) -> (shl (zext x), cst)
   if ((N0.getOpcode() == ISD::SHL || N0.getOpcode() == ISD::SRL) &&
-      isa<ConstantSDNode>(N0.getOperand(1)) &&
-      N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND &&
-      N0.hasOneUse()) {
+      isa<ConstantIntSDNode>(N0.getOperand(1)) &&
+      N0.getOperand(0).getOpcode() == ISD::ZERO_EXTEND && N0.hasOneUse()) {
     SDValue ShAmt = N0.getOperand(1);
-    unsigned ShAmtVal = cast<ConstantSDNode>(ShAmt)->getZExtValue();
+    unsigned ShAmtVal = cast<ConstantIntSDNode>(ShAmt)->getZExtValue();
     if (N0.getOpcode() == ISD::SHL) {
       SDValue InnerZExt = N0.getOperand(0);
       // If the original shl may be shifting out bits, do not perform this
@@ -6719,7 +6721,7 @@
     } else if (X.getValueType().bitsGT(VT)) {
       X = DAG.getNode(ISD::TRUNCATE, SDLoc(N), VT, X);
     }
-    APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
+    APInt Mask = cast<ConstantIntSDNode>(N0.getOperand(1))->getAPIntValue();
     Mask = Mask.zext(VT.getSizeInBits());
     SDLoc DL(N);
     return DAG.getNode(ISD::AND, DL, VT,
@@ -6824,7 +6826,7 @@
   switch (V.getOpcode()) {
   default: break;
   case ISD::Constant: {
-    const ConstantSDNode *CV = cast<ConstantSDNode>(V.getNode());
+    const auto *CV = cast<ConstantIntSDNode>(V.getNode());
     assert(CV && "Const value should be ConstSDNode.");
     const APInt &CVal = CV->getAPIntValue();
     APInt NewVal = CVal & Mask;
@@ -6844,7 +6846,7 @@
     // Only look at single-use SRLs.
     if (!V.getNode()->hasOneUse())
       break;
-    if (ConstantSDNode *RHSC = getAsNonOpaqueConstant(V.getOperand(1))) {
+    if (ConstantIntSDNode *RHSC = getAsNonOpaqueConstant(V.getOperand(1))) {
       // See if we can recursively simplify the LHS.
       unsigned Amt = RHSC->getZExtValue();
 
@@ -6885,7 +6887,7 @@
     // Another special-case: SRL is basically zero-extending a narrower value.
     ExtType = ISD::ZEXTLOAD;
     N0 = SDValue(N, 0);
-    ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
+    auto *N01 = dyn_cast<ConstantIntSDNode>(N0.getOperand(1));
     if (!N01) return SDValue();
     ExtVT = EVT::getIntegerVT(*DAG.getContext(),
                               VT.getSizeInBits() - N01->getZExtValue());
@@ -6902,7 +6904,7 @@
 
   unsigned ShAmt = 0;
   if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
-    if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
+    if (auto *N01 = dyn_cast<ConstantIntSDNode>(N0.getOperand(1))) {
       ShAmt = N01->getZExtValue();
       // Is the shift amount a multiple of size of VT?
       if ((ShAmt & (EVTBits-1)) == 0) {
@@ -6934,7 +6936,7 @@
   unsigned ShLeftAmt = 0;
   if (ShAmt == 0 && N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
       ExtVT == VT && TLI.isNarrowingProfitable(N0.getValueType(), VT)) {
-    if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
+    if (auto *N01 = dyn_cast<ConstantIntSDNode>(N0.getOperand(1))) {
       ShLeftAmt = N01->getZExtValue();
       N0 = N0.getOperand(0);
     }
@@ -7088,7 +7090,7 @@
   // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
   // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
   if (N0.getOpcode() == ISD::SRL) {
-    if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
+    if (auto *ShAmt = dyn_cast<ConstantIntSDNode>(N0.getOperand(1)))
       if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
         // We can turn this into an SRA iff the input to the SRL is already sign
         // extended enough.
@@ -7227,8 +7229,8 @@
     assert(NVT.getSizeInBits() == VecTy.getSizeInBits() && "Invalid Size");
 
     SDValue EltNo = N0->getOperand(1);
-    if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) {
-      int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
+    if (isa<ConstantIntSDNode>(EltNo) && isTypeLegal(NVT)) {
+      int Elt = cast<ConstantIntSDNode>(EltNo)->getZExtValue();
       EVT IndexTy = TLI.getVectorIdxTy(DAG.getDataLayout());
       int Index = isLE ? (Elt*SizeRatio) : (Elt*SizeRatio + (SizeRatio-1));
 
@@ -7256,7 +7258,7 @@
   if (N0.getOpcode() == ISD::SHL && N0.hasOneUse() &&
       (!LegalOperations || TLI.isOperationLegalOrCustom(ISD::SHL, VT)) &&
       TLI.isTypeDesirableForOp(ISD::SHL, VT)) {
-    if (const ConstantSDNode *CAmt = isConstOrConstSplat(N0.getOperand(1))) {
+    if (const ConstantIntSDNode *CAmt = isConstOrConstSplat(N0.getOperand(1))) {
       uint64_t Amt = CAmt->getZExtValue();
       unsigned Size = VT.getScalarSizeInBits();
 
@@ -7476,7 +7478,7 @@
   // Fold (bitcast int (and (bitcast fp X to int), 0x7fff...) to fp) -> fabs X
   // Fold (bitcast int (xor (bitcast fp X to int), 0x8000...) to fp) -> fneg X
   SDValue LogicOp0 = N0.getOperand(0);
-  ConstantSDNode *LogicOp1 = dyn_cast<ConstantSDNode>(N0.getOperand(1));
+  auto *LogicOp1 = dyn_cast<ConstantIntSDNode>(N0.getOperand(1));
   if (LogicOp1 && LogicOp1->getAPIntValue() == SignMask &&
       LogicOp0.getOpcode() == ISD::BITCAST &&
       LogicOp0->getOperand(0).getValueType() == VT)
@@ -7506,12 +7508,12 @@
   }
 
   // If the input is a constant, let getNode fold it.
-  if (isa<ConstantSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
+  if (isa<ConstantIntSDNode>(N0) || isa<ConstantFPSDNode>(N0)) {
     // If we can't allow illegal operations, we need to check that this is just
     // a fp -> int or int -> conversion and that the resulting operation will
     // be legal.
     if (!LegalOperations ||
-        (isa<ConstantSDNode>(N0) && VT.isFloatingPoint() && !VT.isVector() &&
+        (isa<ConstantIntSDNode>(N0) && VT.isFloatingPoint() && !VT.isVector() &&
          TLI.isOperationLegal(ISD::ConstantFP, VT)) ||
         (isa<ConstantFPSDNode>(N0) && VT.isInteger() && !VT.isVector() &&
          TLI.isOperationLegal(ISD::Constant, VT)))
@@ -7698,7 +7700,7 @@
       if (Op.getOpcode() == ISD::BITCAST &&
           Op.getOperand(0).getValueType() == VT)
         return SDValue(Op.getOperand(0));
-      if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) ||
+      if (ISD::isBuildVectorOfConstantIntSDNodes(Op.getNode()) ||
           ISD::isBuildVectorOfConstantFPSDNodes(Op.getNode()))
         return DAG.getBitcast(VT, Op);
       return SDValue();
@@ -7813,8 +7815,10 @@
         if (Op.isUndef()) continue;
         EltIsUndef = false;
 
-        NewBits |= cast<ConstantSDNode>(Op)->getAPIntValue().
-                   zextOrTrunc(SrcBitSize).zext(DstBitSize);
+        NewBits |= cast<ConstantIntSDNode>(Op)
+                       ->getAPIntValue()
+                       .zextOrTrunc(SrcBitSize)
+                       .zext(DstBitSize);
       }
 
       if (EltIsUndef)
@@ -7840,8 +7844,8 @@
       continue;
     }
 
-    APInt OpVal = cast<ConstantSDNode>(Op)->
-                  getAPIntValue().zextOrTrunc(SrcBitSize);
+    APInt OpVal =
+        cast<ConstantIntSDNode>(Op)->getAPIntValue().zextOrTrunc(SrcBitSize);
 
     for (unsigned j = 0; j != NumOutputsPerInput; ++j) {
       APInt ThisVal = OpVal.trunc(DstBitSize);
@@ -9591,10 +9595,12 @@
       SDValue AndOp1 = Op0.getOperand(1);
 
       if (AndOp1.getOpcode() == ISD::Constant) {
-        const APInt &AndConst = cast<ConstantSDNode>(AndOp1)->getAPIntValue();
+        const APInt &AndConst =
+            cast<ConstantIntSDNode>(AndOp1)->getAPIntValue();
 
         if (AndConst.isPowerOf2() &&
-            cast<ConstantSDNode>(Op1)->getAPIntValue()==AndConst.logBase2()) {
+            cast<ConstantIntSDNode>(Op1)->getAPIntValue() ==
+                AndConst.logBase2()) {
           SDLoc DL(N);
           SDValue SetCC =
             DAG.getSetCC(DL,
@@ -9730,7 +9736,7 @@
 
   TargetLowering::AddrMode AM;
   if (N->getOpcode() == ISD::ADD) {
-    ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
+    auto *Offset = dyn_cast<ConstantIntSDNode>(N->getOperand(1));
     if (Offset)
       // [reg +/- imm]
       AM.BaseOffs = Offset->getSExtValue();
@@ -9738,7 +9744,7 @@
       // [reg +/- reg]
       AM.Scale = 1;
   } else if (N->getOpcode() == ISD::SUB) {
-    ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
+    auto *Offset = dyn_cast<ConstantIntSDNode>(N->getOperand(1));
     if (Offset)
       // [reg +/- imm]
       AM.BaseOffs = -Offset->getSExtValue();
@@ -9802,7 +9808,7 @@
   // constant base with a variable offset so that constant coercion
   // will work with the patterns in canonical form.
   bool Swapped = false;
-  if (isa<ConstantSDNode>(BasePtr)) {
+  if (isa<ConstantIntSDNode>(BasePtr)) {
     std::swap(BasePtr, Offset);
     Swapped = true;
   }
@@ -9840,7 +9846,7 @@
   // can be folded with this one. We should do this to avoid having to keep
   // a copy of the original base pointer.
   SmallVector<SDNode *, 16> OtherUses;
-  if (isa<ConstantSDNode>(Offset))
+  if (isa<ConstantIntSDNode>(Offset))
     for (SDNode::use_iterator UI = BasePtr.getNode()->use_begin(),
                               UE = BasePtr.getNode()->use_end();
          UI != UE; ++UI) {
@@ -9860,7 +9866,7 @@
       }
 
       SDValue Op1 = Use.getUser()->getOperand((UI.getOperandNo() + 1) & 1);
-      if (!isa<ConstantSDNode>(Op1)) {
+      if (!isa<ConstantIntSDNode>(Op1)) {
         OtherUses.clear();
         break;
       }
@@ -9942,11 +9948,10 @@
     // Therefore, we have:
     //   t0 = (x0 * offset0 - x1 * y0 * y1 *offset1) + (y0 * y1) * t1
 
-    ConstantSDNode *CN =
-      cast<ConstantSDNode>(OtherUses[i]->getOperand(OffsetIdx));
+    auto *CN = cast<ConstantIntSDNode>(OtherUses[i]->getOperand(OffsetIdx));
     int X0, X1, Y0, Y1;
     const APInt &Offset0 = CN->getAPIntValue();
-    APInt Offset1 = cast<ConstantSDNode>(Offset)->getAPIntValue();
+    APInt Offset1 = cast<ConstantIntSDNode>(Offset)->getAPIntValue();
 
     X0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 1) ? -1 : 1;
     Y0 = (OtherUses[i]->getOpcode() == ISD::SUB && OffsetIdx == 0) ? -1 : 1;
@@ -10111,10 +10116,10 @@
   // TargetConstants in general ADD nodes. We can convert these constants into
   // regular Constants (if the constant is not opaque).
   assert((Inc.getOpcode() != ISD::TargetConstant ||
-          !cast<ConstantSDNode>(Inc)->isOpaque()) &&
+          !cast<ConstantIntSDNode>(Inc)->isOpaque()) &&
          "Cannot split out indexing using opaque target constants");
   if (Inc.getOpcode() == ISD::TargetConstant) {
-    ConstantSDNode *ConstInc = cast<ConstantSDNode>(Inc);
+    auto *ConstInc = cast<ConstantIntSDNode>(Inc);
     Inc = DAG.getConstant(*ConstInc->getConstantIntValue(), SDLoc(Inc),
                           ConstInc->getValueType(0));
   }
@@ -10164,7 +10169,7 @@
       // valid for a different type of node, and we cannot convert an opaque
       // target constant into a regular constant).
       bool HasOTCInc = LD->getOperand(2).getOpcode() == ISD::TargetConstant &&
-                       cast<ConstantSDNode>(LD->getOperand(2))->isOpaque();
+                       cast<ConstantIntSDNode>(LD->getOperand(2))->isOpaque();
 
       if (!N->hasAnyUseOfValue(0) &&
           ((MaySplitLoadIndex && !HasOTCInc) || !N->hasAnyUseOfValue(1))) {
@@ -10745,8 +10750,8 @@
 
     // Check if this is a trunc(lshr).
     if (User->getOpcode() == ISD::SRL && User->hasOneUse() &&
-        isa<ConstantSDNode>(User->getOperand(1))) {
-      Shift = cast<ConstantSDNode>(User->getOperand(1))->getZExtValue();
+        isa<ConstantIntSDNode>(User->getOperand(1))) {
+      Shift = cast<ConstantIntSDNode>(User->getOperand(1))->getZExtValue();
       User = *User->use_begin();
     }
 
@@ -10819,8 +10824,7 @@
   std::pair<unsigned, unsigned> Result(0, 0);
 
   // Check for the structure we're looking for.
-  if (V->getOpcode() != ISD::AND ||
-      !isa<ConstantSDNode>(V->getOperand(1)) ||
+  if (V->getOpcode() != ISD::AND || !isa<ConstantIntSDNode>(V->getOperand(1)) ||
       !ISD::isNormalLoad(V->getOperand(0).getNode()))
     return Result;
 
@@ -10853,7 +10857,7 @@
   // Check the constant mask.  Invert it so that the bits being masked out are
   // 0 and the bits being kept are 1.  Use getSExtValue so that leading bits
   // follow the sign bit for uniformity.
-  uint64_t NotMask = ~cast<ConstantSDNode>(V->getOperand(1))->getSExtValue();
+  uint64_t NotMask = ~cast<ConstantIntSDNode>(V->getOperand(1))->getSExtValue();
   unsigned NotMaskLZ = countLeadingZeros(NotMask);
   if (NotMaskLZ & 7) return Result;  // Must be multiple of a byte.
   unsigned NotMaskTZ = countTrailingZeros(NotMask);
@@ -11003,7 +11007,7 @@
     // Find the type to narrow it the load / op / store to.
     SDValue N1 = Value.getOperand(1);
     unsigned BitWidth = N1.getValueSizeInBits();
-    APInt Imm = cast<ConstantSDNode>(N1)->getAPIntValue();
+    APInt Imm = cast<ConstantIntSDNode>(N1)->getAPIntValue();
     if (Opc == ISD::AND)
       Imm ^= APInt::getAllOnesValue(BitWidth);
     if (Imm == 0 || Imm.isAllOnesValue())
@@ -11183,8 +11187,9 @@
 
     // We know that we have at least an ADD instruction. Try to pattern match
     // the simple case of BASE + OFFSET.
-    if (isa<ConstantSDNode>(Ptr->getOperand(1))) {
-      int64_t Offset = cast<ConstantSDNode>(Ptr->getOperand(1))->getSExtValue();
+    if (isa<ConstantIntSDNode>(Ptr->getOperand(1))) {
+      int64_t Offset =
+          cast<ConstantIntSDNode>(Ptr->getOperand(1))->getSExtValue();
       return  BaseIndexOffset(Ptr->getOperand(0), SDValue(), Offset,
                               IsIndexSignExt);
     }
@@ -11215,7 +11220,7 @@
     SDValue Index = IndexOffset->getOperand(0);
     SDValue Offset = IndexOffset->getOperand(1);
 
-    if (!isa<ConstantSDNode>(Offset))
+    if (!isa<ConstantIntSDNode>(Offset))
       return BaseIndexOffset(Ptr, SDValue(), 0, IsIndexSignExt);
 
     // Ignore signextends.
@@ -11224,7 +11229,7 @@
       IsIndexSignExt = true;
     } else IsIndexSignExt = false;
 
-    int64_t Off = cast<ConstantSDNode>(Offset)->getSExtValue();
+    int64_t Off = cast<ConstantIntSDNode>(Offset)->getSExtValue();
     return BaseIndexOffset(Base, Index, Off, IsIndexSignExt);
   }
 };
@@ -11392,7 +11397,7 @@
 
       SDValue Val = St->getValue();
       StoreInt <<= ElementSizeBytes * 8;
-      if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val)) {
+      if (auto *C = dyn_cast<ConstantIntSDNode>(Val)) {
         StoreInt |= C->getAPIntValue().zext(SizeInBits);
       } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Val)) {
         StoreInt |= C->getValueAPF().bitcastToAPInt().zext(SizeInBits);
@@ -11606,8 +11611,8 @@
   // are not constants, loads, or extracted vector elements.
   SDValue StoredVal = St->getValue();
   bool IsLoadSrc = isa<LoadSDNode>(StoredVal);
-  bool IsConstantSrc = isa<ConstantSDNode>(StoredVal) ||
-                       isa<ConstantFPSDNode>(StoredVal);
+  bool IsConstantSrc =
+      isa<ConstantIntSDNode>(StoredVal) || isa<ConstantFPSDNode>(StoredVal);
   bool IsExtractVecSrc = (StoredVal.getOpcode() == ISD::EXTRACT_VECTOR_ELT ||
                           StoredVal.getOpcode() == ISD::EXTRACT_SUBVECTOR);
 
@@ -11700,7 +11705,7 @@
       StoreSDNode *St  = cast<StoreSDNode>(StoreNodes[i].MemNode);
       SDValue StoredVal = St->getValue();
 
-      if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(StoredVal)) {
+      if (auto *C = dyn_cast<ConstantIntSDNode>(StoredVal)) {
         NonZero |= !C->isNullValue();
       } else if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(StoredVal)) {
         NonZero |= !C->getConstantFPValue()->isNullValue();
@@ -12320,7 +12325,7 @@
 
   // Match shift amount to HalfValBitSize.
   unsigned HalfValBitSize = Val.getValueSizeInBits() / 2;
-  ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(Op1.getOperand(1));
+  auto *ShAmt = dyn_cast<ConstantIntSDNode>(Op1.getOperand(1));
   if (!ShAmt || ShAmt->getAPIntValue() != HalfValBitSize)
     return SDValue();
 
@@ -12381,9 +12386,9 @@
     return SDValue();
 
   // Check that we know which element is being inserted
-  if (!isa<ConstantSDNode>(EltNo))
+  if (!isa<ConstantIntSDNode>(EltNo))
     return SDValue();
-  unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
+  unsigned Elt = cast<ConstantIntSDNode>(EltNo)->getZExtValue();
 
   // Canonicalize insert_vector_elt dag nodes.
   // Example:
@@ -12392,10 +12397,10 @@
   //
   // Do this only if the child insert_vector node has one use; also
   // do this only if indices are both constants and Idx1 < Idx0.
-  if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse()
-      && isa<ConstantSDNode>(InVec.getOperand(2))) {
+  if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT && InVec.hasOneUse() &&
+      isa<ConstantIntSDNode>(InVec.getOperand(2))) {
     unsigned OtherElt =
-      cast<ConstantSDNode>(InVec.getOperand(2))->getZExtValue();
+        cast<ConstantIntSDNode>(InVec.getOperand(2))->getZExtValue();
     if (Elt < OtherElt) {
       // Swap nodes.
       SDValue NewOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT,
@@ -12458,7 +12463,7 @@
   EVT PtrType = NewPtr.getValueType();
   MachinePointerInfo MPI;
   SDLoc DL(EVE);
-  if (auto *ConstEltNo = dyn_cast<ConstantSDNode>(EltNo)) {
+  if (auto *ConstEltNo = dyn_cast<ConstantIntSDNode>(EltNo)) {
     int Elt = ConstEltNo->getZExtValue();
     unsigned PtrOff = VecEltVT.getSizeInBits() * Elt / 8;
     Offset = DAG.getConstant(PtrOff, DL, PtrType);
@@ -12535,7 +12540,7 @@
   }
 
   SDValue EltNo = N->getOperand(1);
-  ConstantSDNode *ConstEltNo = dyn_cast<ConstantSDNode>(EltNo);
+  auto *ConstEltNo = dyn_cast<ConstantIntSDNode>(EltNo);
 
   // extract_vector_elt (build_vector x, y), 1 -> y
   if (ConstEltNo &&
@@ -12662,7 +12667,7 @@
   // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
 
   if (ConstEltNo) {
-    int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
+    int Elt = cast<ConstantIntSDNode>(EltNo)->getZExtValue();
 
     LoadSDNode *LN0 = nullptr;
     const ShuffleVectorSDNode *SVN = nullptr;
@@ -12977,7 +12982,7 @@
 
     SDValue Extract = N->getOperand(i);
     unsigned ExtIndex =
-        cast<ConstantSDNode>(Extract.getOperand(1))->getZExtValue();
+        cast<ConstantIntSDNode>(Extract.getOperand(1))->getZExtValue();
 
     if (VectorMask[i] == (int)LeftIdx) {
       Mask[i] = ExtIndex;
@@ -13047,7 +13052,7 @@
     // Not an undef or zero. If the input is something other than an
     // EXTRACT_VECTOR_ELT with a constant index, bail out.
     if (Op.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
-        !isa<ConstantSDNode>(Op.getOperand(1)))
+        !isa<ConstantIntSDNode>(Op.getOperand(1)))
       return SDValue();
 
     SDValue ExtractedFromVec = Op.getOperand(0);
@@ -13288,9 +13293,9 @@
       continue;
     }
 
-    if (!isa<ConstantSDNode>(Op.getOperand(1)))
+    if (!isa<ConstantIntSDNode>(Op.getOperand(1)))
       return SDValue();
-    int ExtIdx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
+    int ExtIdx = cast<ConstantIntSDNode>(Op.getOperand(1))->getZExtValue();
 
     // Ensure that we are extracting a subvector from a vector the same
     // size as the result.
@@ -13462,7 +13467,7 @@
     }
 
     unsigned IdentityIndex = i * PartNumElem;
-    ConstantSDNode *CS = dyn_cast<ConstantSDNode>(Op.getOperand(1));
+    auto *CS = dyn_cast<ConstantIntSDNode>(Op.getOperand(1));
     // The extract index must be constant.
     if (!CS)
       return SDValue();
@@ -13511,8 +13516,8 @@
       return SDValue();
 
     // Only handle cases where both indexes are constants with the same type.
-    ConstantSDNode *ExtIdx = dyn_cast<ConstantSDNode>(N->getOperand(1));
-    ConstantSDNode *InsIdx = dyn_cast<ConstantSDNode>(V->getOperand(2));
+    auto *ExtIdx = dyn_cast<ConstantIntSDNode>(N->getOperand(1));
+    auto *InsIdx = dyn_cast<ConstantIntSDNode>(V->getOperand(2));
 
     if (InsIdx && ExtIdx &&
         InsIdx->getValueType(0).getSizeInBits() <= 64 &&
@@ -13573,7 +13578,7 @@
   case ISD::INSERT_SUBVECTOR: {
     SDValue BaseV = V->getOperand(0);
     SDValue SubV = V->getOperand(1);
-    auto *IdxN = dyn_cast<ConstantSDNode>(V->getOperand(2));
+    auto *IdxN = dyn_cast<ConstantIntSDNode>(V->getOperand(2));
     if (!IdxN)
       return V;
 
@@ -14050,7 +14055,7 @@
 
     // FIXME: We could support implicit truncation if the shuffle can be
     // scaled to a smaller vector scalar type.
-    ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(EltNo);
+    auto *C0 = dyn_cast<ConstantIntSDNode>(EltNo);
     if (C0 && VT == InVec.getValueType() &&
         VT.getScalarType() == InVal.getValueType()) {
       SmallVector<int, 8> NewMask(VT.getVectorNumElements(), -1);
@@ -14088,7 +14093,7 @@
   // one of the halves, we can optimize into a single concat_vectors.
   if (N0.getOpcode() == ISD::CONCAT_VECTORS && N0->getNumOperands() == 2 &&
       N2.getOpcode() == ISD::Constant) {
-    APInt InsIdx = cast<ConstantSDNode>(N2)->getAPIntValue();
+    APInt InsIdx = cast<ConstantIntSDNode>(N2)->getAPIntValue();
 
     // Lower half: fold (insert_subvector (concat_vectors X, Y), Z) ->
     // (concat_vectors Z, Y)
@@ -14121,7 +14126,7 @@
 
   // fold fp16_to_fp(op & 0xffff) -> fp16_to_fp(op)
   if (N0->getOpcode() == ISD::AND) {
-    ConstantSDNode *AndConst = getAsNonOpaqueConstant(N0.getOperand(1));
+    ConstantIntSDNode *AndConst = getAsNonOpaqueConstant(N0.getOperand(1));
     if (AndConst && AndConst->getAPIntValue() == 0xffff) {
       return DAG.getNode(ISD::FP16_TO_FP, SDLoc(N), N->getValueType(0),
                          N0.getOperand(0));
@@ -14176,8 +14181,8 @@
       }
 
       APInt Bits;
-      if (isa<ConstantSDNode>(Elt))
-        Bits = cast<ConstantSDNode>(Elt)->getAPIntValue();
+      if (isa<ConstantIntSDNode>(Elt))
+        Bits = cast<ConstantIntSDNode>(Elt)->getAPIntValue();
       else if (isa<ConstantFPSDNode>(Elt))
         Bits = cast<ConstantFPSDNode>(Elt)->getValueAPF().bitcastToAPInt();
       else
@@ -14460,15 +14465,16 @@
   if (N2 == N3) return N2;
 
   EVT VT = N2.getValueType();
-  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
-  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
+  auto *N1C = dyn_cast<ConstantIntSDNode>(N1.getNode());
+  auto *N2C = dyn_cast<ConstantIntSDNode>(N2.getNode());
 
   // Determine if the condition we're dealing with is constant
   SDValue SCC = SimplifySetCC(getSetCCResultType(N0.getValueType()),
                               N0, N1, CC, DL, false);
   if (SCC.getNode()) AddToWorklist(SCC.getNode());
 
-  if (ConstantSDNode *SCCC = dyn_cast_or_null<ConstantSDNode>(SCC.getNode())) {
+  if (ConstantIntSDNode *SCCC =
+          dyn_cast_or_null<ConstantIntSDNode>(SCC.getNode())) {
     // fold select_cc true, x, y -> x
     // fold select_cc false, x, y -> y
     return !SCCC->isNullValue() ? N2 : N3;
@@ -14599,7 +14605,7 @@
   if (CC == ISD::SETEQ && N0->getOpcode() == ISD::AND &&
       N0->getValueType(0) == VT && isNullConstant(N1) && isNullConstant(N2)) {
     SDValue AndLHS = N0->getOperand(0);
-    ConstantSDNode *ConstAndRHS = dyn_cast<ConstantSDNode>(N0->getOperand(1));
+    auto *ConstAndRHS = dyn_cast<ConstantIntSDNode>(N0->getOperand(1));
     if (ConstAndRHS && ConstAndRHS->getAPIntValue().countPopulation() == 1) {
       // Shift the tested bit over the sign bit.
       const APInt &AndMask = ConstAndRHS->getAPIntValue();
@@ -14671,15 +14677,15 @@
   // select_cc setlt    X,  1, -X,  X ->
   // Y = sra (X, size(X)-1); xor (add (X, Y), Y)
   if (N1C) {
-    ConstantSDNode *SubC = nullptr;
+    ConstantIntSDNode *SubC = nullptr;
     if (((N1C->isNullValue() && (CC == ISD::SETGT || CC == ISD::SETGE)) ||
          (N1C->isAllOnesValue() && CC == ISD::SETGT)) &&
         N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1))
-      SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0));
+      SubC = dyn_cast<ConstantIntSDNode>(N3.getOperand(0));
     else if (((N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE)) ||
               (N1C->isOne() && CC == ISD::SETLT)) &&
              N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1))
-      SubC = dyn_cast<ConstantSDNode>(N2.getOperand(0));
+      SubC = dyn_cast<ConstantIntSDNode>(N2.getOperand(0));
 
     EVT XType = N0.getValueType();
     if (SubC && SubC->isNullValue() && XType.isInteger()) {
@@ -14711,7 +14717,7 @@
     if (CC == ISD::SETNE)
       std::swap(ValueOnZero, Count);
     // Check if the value on zero is a constant equal to the bits in the type.
-    if (auto *ValueOnZeroC = dyn_cast<ConstantSDNode>(ValueOnZero)) {
+    if (auto *ValueOnZeroC = dyn_cast<ConstantIntSDNode>(ValueOnZero)) {
       if (ValueOnZeroC->getAPIntValue() == VT.getSizeInBits()) {
         // If the other operand is cttz/cttz_zero_undef of N0, and cttz is
         // legal, combine to just cttz.
@@ -14753,7 +14759,7 @@
   if (DAG.getMachineFunction().getFunction()->optForMinSize())
     return SDValue();
 
-  ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
+  ConstantIntSDNode *C = isConstOrConstSplat(N->getOperand(1));
   if (!C)
     return SDValue();
 
@@ -14773,7 +14779,7 @@
 /// Given an ISD::SDIV node expressing a divide by constant power of 2, return a
 /// DAG expression that will generate the same value by right shifting.
 SDValue DAGCombiner::BuildSDIVPow2(SDNode *N) {
-  ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
+  ConstantIntSDNode *C = isConstOrConstSplat(N->getOperand(1));
   if (!C)
     return SDValue();
 
@@ -14799,7 +14805,7 @@
   if (DAG.getMachineFunction().getFunction()->optForMinSize())
     return SDValue();
 
-  ConstantSDNode *C = isConstOrConstSplat(N->getOperand(1));
+  ConstantIntSDNode *C = isConstOrConstSplat(N->getOperand(1));
   if (!C)
     return SDValue();
 
@@ -15011,7 +15017,7 @@
 
   // If it's an adding a simple constant then integrate the offset.
   if (Base.getOpcode() == ISD::ADD) {
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Base.getOperand(1))) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Base.getOperand(1))) {
       Base = Base.getOperand(0);
       Offset += C->getZExtValue();
     }
@@ -15027,7 +15033,8 @@
   }
 
   // Return the underlying Constant value, and update the Offset.  Return false
-  // for ConstantSDNodes since the same constant pool entry may be represented
+  // for ConstantIntSDNodes since the same constant pool entry may be
+  // represented
   // by multiple nodes with different offsets.
   if (ConstantPoolSDNode *C = dyn_cast<ConstantPoolSDNode>(Base)) {
     CV = C->isMachineConstantPoolEntry() ? (const void *)C->getMachineCPVal()
Index: llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
+++ llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
@@ -387,7 +387,7 @@
   if (Op.isMachineOpcode()) {
     AddRegisterOperand(MIB, Op, IIOpNum, II, VRBaseMap,
                        IsDebug, IsClone, IsCloned);
-  } else if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+  } else if (auto *C = dyn_cast<ConstantIntSDNode>(Op)) {
     MIB.addImm(C->getSExtValue());
   } else if (ConstantFPSDNode *F = dyn_cast<ConstantFPSDNode>(Op)) {
     MIB.addFPImm(F->getConstantFPValue());
@@ -496,7 +496,8 @@
     // EXTRACT_SUBREG is lowered as %dst = COPY %src:sub.  There are no
     // constraints on the %dst register, COPY can target all legal register
     // classes.
-    unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
+    unsigned SubIdx =
+        cast<ConstantIntSDNode>(Node->getOperand(1))->getZExtValue();
     const TargetRegisterClass *TRC =
       TLI->getRegClassFor(Node->getSimpleValueType(0));
 
@@ -537,7 +538,7 @@
     SDValue N0 = Node->getOperand(0);
     SDValue N1 = Node->getOperand(1);
     SDValue N2 = Node->getOperand(2);
-    unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue();
+    unsigned SubIdx = cast<ConstantIntSDNode>(N2)->getZExtValue();
 
     // Figure out the register class to create for the destreg.  It should be
     // the largest legal register class supporting SubIdx sub-registers.
@@ -567,7 +568,7 @@
     // If creating a subreg_to_reg, then the first input operand
     // is an implicit value immediate, otherwise it's a register
     if (Opc == TargetOpcode::SUBREG_TO_REG) {
-      const ConstantSDNode *SD = cast<ConstantSDNode>(N0);
+      const auto *SD = cast<ConstantIntSDNode>(N0);
       MIB.addImm(SD->getZExtValue());
     } else
       AddOperand(MIB, N0, 0, nullptr, VRBaseMap, /*IsDebug=*/false,
@@ -596,7 +597,8 @@
   unsigned VReg = getVR(Node->getOperand(0), VRBaseMap);
 
   // Create the new VReg in the destination class and emit a copy.
-  unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
+  unsigned DstRCIdx =
+      cast<ConstantIntSDNode>(Node->getOperand(1))->getZExtValue();
   const TargetRegisterClass *DstRC =
     TRI->getAllocatableClass(TRI->getRegClass(DstRCIdx));
   unsigned NewVReg = MRI->createVirtualRegister(DstRC);
@@ -614,7 +616,8 @@
 void InstrEmitter::EmitRegSequence(SDNode *Node,
                                   DenseMap<SDValue, unsigned> &VRBaseMap,
                                   bool IsClone, bool IsCloned) {
-  unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
+  unsigned DstRCIdx =
+      cast<ConstantIntSDNode>(Node->getOperand(0))->getZExtValue();
   const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
   unsigned NewVReg = MRI->createVirtualRegister(TRI->getAllocatableClass(RC));
   const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE);
@@ -629,7 +632,7 @@
       // Skip physical registers as they don't have a vreg to get and we'll
       // insert copies for them in TwoAddressInstructionPass anyway.
       if (!R || !TargetRegisterInfo::isPhysicalRegister(R->getReg())) {
-        unsigned SubIdx = cast<ConstantSDNode>(Op)->getZExtValue();
+        unsigned SubIdx = cast<ConstantIntSDNode>(Op)->getZExtValue();
         unsigned SubReg = getVR(Node->getOperand(i-1), VRBaseMap);
         const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
         const TargetRegisterClass *SRC =
@@ -956,8 +959,8 @@
     // Add the HasSideEffect, isAlignStack, AsmDialect, MayLoad and MayStore
     // bits.
     int64_t ExtraInfo =
-      cast<ConstantSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))->
-                          getZExtValue();
+        cast<ConstantIntSDNode>(Node->getOperand(InlineAsm::Op_ExtraInfo))
+            ->getZExtValue();
     MIB.addImm(ExtraInfo);
 
     // Remember to operand index of the group flags.
@@ -969,7 +972,7 @@
     // Add all of the operand registers to the instruction.
     for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
       unsigned Flags =
-        cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
+          cast<ConstantIntSDNode>(Node->getOperand(i))->getZExtValue();
       const unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
 
       GroupIdx.push_back(MIB->getNumOperands());
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -156,7 +156,7 @@
   SDValue ExpandVectorBuildThroughStack(SDNode* Node);
 
   SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP);
-  SDValue ExpandConstant(ConstantSDNode *CP);
+  SDValue ExpandConstant(ConstantIntSDNode *CP);
 
   // if ExpandNode returns false, LegalizeOp falls back to ConvertNodeToLibcall
   bool ExpandNode(SDNode *Node);
@@ -298,7 +298,7 @@
 }
 
 /// Expands the Constant node to a load from the constant pool.
-SDValue SelectionDAGLegalize::ExpandConstant(ConstantSDNode *CP) {
+SDValue SelectionDAGLegalize::ExpandConstant(ConstantIntSDNode *CP) {
   SDLoc dl(CP);
   EVT VT = CP->getValueType(0);
   SDValue CPIdx = DAG.getConstantPool(CP->getConstantIntValue(),
@@ -358,7 +358,7 @@
 SDValue SelectionDAGLegalize::ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val,
                                                       SDValue Idx,
                                                       const SDLoc &dl) {
-  if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) {
+  if (auto *InsertPos = dyn_cast<ConstantIntSDNode>(Idx)) {
     // SCALAR_TO_VECTOR requires that the type of the value being inserted
     // match the element type of the vector being created, except for
     // integers in which case the inserted value can be over width.
@@ -1514,7 +1514,7 @@
   SDValue Size  = Tmp2.getOperand(1);
   SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT);
   Chain = SP.getValue(1);
-  unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue();
+  unsigned Align = cast<ConstantIntSDNode>(Tmp3)->getZExtValue();
   unsigned StackAlign =
       DAG.getSubtarget().getFrameLowering()->getStackAlignment();
   Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size);       // Value
@@ -1822,7 +1822,7 @@
       continue;
     if (i > 0)
       isOnlyLowElement = false;
-    if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
+    if (!isa<ConstantFPSDNode>(V) && !isa<ConstantIntSDNode>(V))
       isConstant = false;
 
     if (!Value1.getNode()) {
@@ -1848,8 +1848,7 @@
       if (ConstantFPSDNode *V =
           dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) {
         CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue()));
-      } else if (ConstantSDNode *V =
-                 dyn_cast<ConstantSDNode>(Node->getOperand(i))) {
+      } else if (auto *V = dyn_cast<ConstantIntSDNode>(Node->getOperand(i))) {
         if (OpVT==EltVT)
           CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
         else {
@@ -3109,7 +3108,7 @@
   }
   case ISD::EXTRACT_ELEMENT: {
     EVT OpTy = Node->getOperand(0).getValueType();
-    if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
+    if (cast<ConstantIntSDNode>(Node->getOperand(1))->getZExtValue()) {
       // 1 -> Hi
       Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
                          DAG.getConstant(OpTy.getSizeInBits() / 2, dl,
@@ -3239,7 +3238,7 @@
     break;
   }
   case ISD::Constant: {
-    ConstantSDNode *CP = cast<ConstantSDNode>(Node);
+    auto *CP = cast<ConstantIntSDNode>(Node);
     Results.push_back(ExpandConstant(CP));
     break;
   }
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -1953,13 +1953,13 @@
 
   // If the index is constant, try to extract the value from the legalized
   // vector type.
-  if (isa<ConstantSDNode>(N->getOperand(1))) {
+  if (isa<ConstantIntSDNode>(N->getOperand(1))) {
     SDValue Vec = N->getOperand(0);
     SDValue Idx = N->getOperand(1);
     EVT VecVT = Vec->getValueType(0);
     EVT EltVT = VecVT.getVectorElementType();
 
-    uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
+    uint64_t IdxVal = cast<ConstantIntSDNode>(Idx)->getZExtValue();
 
     switch (getTypeAction(VecVT)) {
     default: break;
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -354,7 +354,7 @@
   SDValue Result = DAG.getNode(Opc, dl,
                                TLI.getTypeToTransformTo(*DAG.getContext(), VT),
                                SDValue(N, 0));
-  assert(isa<ConstantSDNode>(Result) && "Didn't constant fold ext?");
+  assert(isa<ConstantIntSDNode>(Result) && "Didn't constant fold ext?");
   return Result;
 }
 
@@ -1957,7 +1957,7 @@
                                              SDValue &Lo, SDValue &Hi) {
   EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0));
   unsigned NBitWidth = NVT.getSizeInBits();
-  auto Constant = cast<ConstantSDNode>(N);
+  auto Constant = cast<ConstantIntSDNode>(N);
   const APInt &Cst = Constant->getAPIntValue();
   bool IsTarget = Constant->isTargetOpcode();
   bool IsOpaque = Constant->isOpaque();
@@ -2348,7 +2348,7 @@
 
   // If we can emit an efficient shift operation, do so now.  Check to see if
   // the RHS is a constant.
-  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
+  if (auto *CN = dyn_cast<ConstantIntSDNode>(N->getOperand(1)))
     return ExpandShiftByConstant(N, CN->getAPIntValue(), Lo, Hi);
 
   // If we can determine that the high bit of the shift is zero or one, even if
@@ -2817,7 +2817,7 @@
 
   if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
     if (RHSLo == RHSHi) {
-      if (ConstantSDNode *RHSCST = dyn_cast<ConstantSDNode>(RHSLo)) {
+      if (auto *RHSCST = dyn_cast<ConstantIntSDNode>(RHSLo)) {
         if (RHSCST->isAllOnesValue()) {
           // Equality comparison to -1.
           NewLHS = DAG.getNode(ISD::AND, dl,
@@ -2837,7 +2837,7 @@
 
   // If this is a comparison of the sign bit, just look at the top part.
   // X > -1,  x < 0
-  if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(NewRHS))
+  if (auto *CST = dyn_cast<ConstantIntSDNode>(NewRHS))
     if ((CCCode == ISD::SETLT && CST->isNullValue()) ||     // X < 0
         (CCCode == ISD::SETGT && CST->isAllOnesValue())) {  // X > -1
       NewLHS = LHSHi;
@@ -2884,8 +2884,8 @@
         DAG.getNode(ISD::SETCC, dl, getSetCCResultType(LHSHi.getValueType()),
                     LHSHi, RHSHi, DAG.getCondCode(CCCode));
 
-  ConstantSDNode *LoCmpC = dyn_cast<ConstantSDNode>(LoCmp.getNode());
-  ConstantSDNode *HiCmpC = dyn_cast<ConstantSDNode>(HiCmp.getNode());
+  auto *LoCmpC = dyn_cast<ConstantIntSDNode>(LoCmp.getNode());
+  auto *HiCmpC = dyn_cast<ConstantIntSDNode>(HiCmp.getNode());
 
   bool EqAllowed = (CCCode == ISD::SETLE || CCCode == ISD::SETGE ||
                     CCCode == ISD::SETUGE || CCCode == ISD::SETULE);
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
@@ -200,8 +200,8 @@
 void DAGTypeLegalizer::ExpandRes_EXTRACT_ELEMENT(SDNode *N, SDValue &Lo,
                                                  SDValue &Hi) {
   GetExpandedOp(N->getOperand(0), Lo, Hi);
-  SDValue Part = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() ?
-                   Hi : Lo;
+  SDValue Part =
+      cast<ConstantIntSDNode>(N->getOperand(1))->getZExtValue() ? Hi : Lo;
 
   assert(Part.getValueType() == N->getValueType(0) &&
          "Type twice as big as expanded type not itself expanded!");
@@ -407,7 +407,7 @@
 SDValue DAGTypeLegalizer::ExpandOp_EXTRACT_ELEMENT(SDNode *N) {
   SDValue Lo, Hi;
   GetExpandedOp(N->getOperand(0), Lo, Hi);
-  return cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() ? Hi : Lo;
+  return cast<ConstantIntSDNode>(N->getOperand(1))->getZExtValue() ? Hi : Lo;
 }
 
 SDValue DAGTypeLegalizer::ExpandOp_INSERT_VECTOR_ELT(SDNode *N) {
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -368,7 +368,7 @@
   SDValue Arg = N->getOperand(2).getOperand(0);
   if (Arg.isUndef())
     return DAG.getUNDEF(N->getValueType(0).getVectorElementType());
-  unsigned Op = !cast<ConstantSDNode>(Arg)->isNullValue();
+  unsigned Op = !cast<ConstantIntSDNode>(Arg)->isNullValue();
   return GetScalarizedVector(N->getOperand(Op));
 }
 
@@ -831,7 +831,7 @@
   std::tie(LoVT, HiVT) = DAG.GetSplitDestVTs(N->getValueType(0));
 
   Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
-  uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
+  uint64_t IdxVal = cast<ConstantIntSDNode>(Idx)->getZExtValue();
   Hi = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, HiVT, Vec,
                    DAG.getConstant(IdxVal + LoVT.getVectorNumElements(), dl,
                                    TLI.getVectorIdxTy(DAG.getDataLayout())));
@@ -856,7 +856,7 @@
   // TODO: The IdxVal == 0 constraint is artificial, we could do this whenever
   // the index is constant and there is no boundary crossing. But those cases
   // don't seem to get hit in practice.
-  if (ConstantSDNode *ConstIdx = dyn_cast<ConstantSDNode>(Idx)) {
+  if (auto *ConstIdx = dyn_cast<ConstantIntSDNode>(Idx)) {
     unsigned IdxVal = ConstIdx->getZExtValue();
     if ((IdxVal == 0) && (IdxVal + SubElems <= VecElems / 2)) {
       EVT LoVT, HiVT;
@@ -976,7 +976,7 @@
   SDLoc dl(N);
   GetSplitVector(Vec, Lo, Hi);
 
-  if (ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
+  if (auto *CIdx = dyn_cast<ConstantIntSDNode>(Idx)) {
     unsigned IdxVal = CIdx->getZExtValue();
     unsigned LoNumElts = Lo.getValueType().getVectorNumElements();
     if (IdxVal < LoNumElts)
@@ -1589,7 +1589,7 @@
   GetSplitVector(N->getOperand(0), Lo, Hi);
 
   uint64_t LoElts = Lo.getValueType().getVectorNumElements();
-  uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
+  uint64_t IdxVal = cast<ConstantIntSDNode>(Idx)->getZExtValue();
 
   if (IdxVal < LoElts) {
     assert(IdxVal + SubVT.getVectorNumElements() <= LoElts &&
@@ -1607,8 +1607,8 @@
   SDValue Idx = N->getOperand(1);
   EVT VecVT = Vec.getValueType();
 
-  if (isa<ConstantSDNode>(Idx)) {
-    uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
+  if (isa<ConstantIntSDNode>(Idx)) {
+    uint64_t IdxVal = cast<ConstantIntSDNode>(Idx)->getZExtValue();
     assert(IdxVal < VecVT.getVectorNumElements() && "Invalid vector index!");
 
     SDValue Lo, Hi;
@@ -2789,7 +2789,7 @@
   EVT InVT = InOp.getValueType();
 
   // Check if we can just return the input vector after widening.
-  uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
+  uint64_t IdxVal = cast<ConstantIntSDNode>(Idx)->getZExtValue();
   if (IdxVal == 0 && InVT == WidenVT)
     return InOp;
 
Index: llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
+++ llvm/lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp
@@ -341,7 +341,7 @@
   for (unsigned i = 0, e = SU->getNode()->getNumOperands(); i != e; ++i) {
       const SDValue &Op = SU->getNode()->getOperand(i);
       MVT VT = Op.getNode()->getSimpleValueType(Op.getResNo());
-      if (isa<ConstantSDNode>(Op.getNode()))
+      if (isa<ConstantIntSDNode>(Op.getNode()))
         continue;
 
       if (TLI->isTypeLegal(VT) && TLI->getRegClassFor(VT)
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
@@ -496,7 +496,7 @@
 
       for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
         unsigned Flags =
-          cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
+            cast<ConstantIntSDNode>(Node->getOperand(i))->getZExtValue();
         unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
 
         ++i; // Skip the ID value.
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -296,7 +296,8 @@
 
     unsigned Opcode = Node->getMachineOpcode();
     if (Opcode == TargetOpcode::REG_SEQUENCE) {
-      unsigned DstRCIdx = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
+      unsigned DstRCIdx =
+          cast<ConstantIntSDNode>(Node->getOperand(0))->getZExtValue();
       const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
       RegClass = RC->getID();
       Cost = 1;
@@ -1281,7 +1282,7 @@
 
       for (unsigned i = InlineAsm::Op_FirstOperand; i != NumOps;) {
         unsigned Flags =
-          cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
+            cast<ConstantIntSDNode>(Node->getOperand(i))->getZExtValue();
         unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
 
         ++i; // Skip the ID value.
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -135,7 +135,7 @@
   // constants are.
   SDValue NotZero = N->getOperand(i);
   unsigned EltSize = N->getValueType(0).getScalarSizeInBits();
-  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(NotZero)) {
+  if (auto *CN = dyn_cast<ConstantIntSDNode>(NotZero)) {
     if (CN->getAPIntValue().countTrailingOnes() < EltSize)
       return false;
   } else if (ConstantFPSDNode *CFPN = dyn_cast<ConstantFPSDNode>(NotZero)) {
@@ -174,7 +174,7 @@
     // we care if the resultant vector is all zeros, not whether the individual
     // constants are.
     unsigned EltSize = N->getValueType(0).getScalarSizeInBits();
-    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Op)) {
+    if (auto *CN = dyn_cast<ConstantIntSDNode>(Op)) {
       if (CN->getAPIntValue().countTrailingZeros() < EltSize)
         return false;
     } else if (ConstantFPSDNode *CFPN = dyn_cast<ConstantFPSDNode>(Op)) {
@@ -190,14 +190,14 @@
   return true;
 }
 
-bool ISD::isBuildVectorOfConstantSDNodes(const SDNode *N) {
+bool ISD::isBuildVectorOfConstantIntSDNodes(const SDNode *N) {
   if (N->getOpcode() != ISD::BUILD_VECTOR)
     return false;
 
   for (const SDValue &Op : N->op_values()) {
     if (Op.isUndef())
       continue;
-    if (!isa<ConstantSDNode>(Op))
+    if (!isa<ConstantIntSDNode>(Op))
       return false;
   }
   return true;
@@ -385,7 +385,7 @@
   default: break;  // Normal nodes don't need extra info.
   case ISD::TargetConstant:
   case ISD::Constant: {
-    const ConstantSDNode *C = cast<ConstantSDNode>(N);
+    const auto *C = cast<ConstantIntSDNode>(N);
     ID.AddPointer(C->getConstantIntValue());
     ID.AddBoolean(C->isOpaque());
     break;
@@ -1170,7 +1170,7 @@
       return SDValue(N, 0);
 
   if (!N) {
-    N = newSDNode<ConstantSDNode>(isT, isO, Elt, DL.getDebugLoc(), EltVT);
+    N = newSDNode<ConstantIntSDNode>(isT, isO, Elt, DL.getDebugLoc(), EltVT);
     CSEMap.InsertNode(N, IP);
     InsertNode(N);
   }
@@ -1577,7 +1577,7 @@
         // number of elements match or the value splatted is a zero constant.
         if (SameNumElts)
           return N1;
-        if (auto *C = dyn_cast<ConstantSDNode>(Splat))
+        if (auto *C = dyn_cast<ConstantIntSDNode>(Splat))
           if (C->isNullValue())
             return N1;
       }
@@ -1898,9 +1898,9 @@
     break;
   }
 
-  if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2)) {
+  if (auto *N2C = dyn_cast<ConstantIntSDNode>(N2)) {
     const APInt &C2 = N2C->getAPIntValue();
-    if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1)) {
+    if (auto *N1C = dyn_cast<ConstantIntSDNode>(N1)) {
       const APInt &C1 = N1C->getAPIntValue();
 
       switch (Cond) {
@@ -2009,7 +2009,7 @@
   switch (Op.getOpcode()) {
   case ISD::Constant:
     // We know all of the bits for a constant!
-    KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
+    KnownOne = cast<ConstantIntSDNode>(Op)->getAPIntValue();
     KnownZero = ~KnownOne;
     break;
   case ISD::BUILD_VECTOR:
@@ -2143,7 +2143,7 @@
     break;
   case ISD::SHL:
     // (shl X, C1) & C2 == 0   iff   (X & C2 >>u C1) == 0
-    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+    if (auto *SA = dyn_cast<ConstantIntSDNode>(Op.getOperand(1))) {
       unsigned ShAmt = SA->getZExtValue();
 
       // If the shift count is an invalid immediate, don't do anything.
@@ -2159,7 +2159,7 @@
     break;
   case ISD::SRL:
     // (ushr X, C1) & C2 == 0   iff  (-1 >> C1) & C2 == 0
-    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+    if (auto *SA = dyn_cast<ConstantIntSDNode>(Op.getOperand(1))) {
       unsigned ShAmt = SA->getZExtValue();
 
       // If the shift count is an invalid immediate, don't do anything.
@@ -2175,7 +2175,7 @@
     }
     break;
   case ISD::SRA:
-    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+    if (auto *SA = dyn_cast<ConstantIntSDNode>(Op.getOperand(1))) {
       unsigned ShAmt = SA->getZExtValue();
 
       // If the shift count is an invalid immediate, don't do anything.
@@ -2328,7 +2328,7 @@
     break;
 
   case ISD::SUB: {
-    if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) {
+    if (auto *CLHS = dyn_cast<ConstantIntSDNode>(Op.getOperand(0))) {
       // We know that the top bits of C-X are clear if X contains less bits
       // than C (i.e. no wrap-around can happen).  For example, 20-X is
       // positive if we can prove that X is >= 0 and < 16.
@@ -2385,7 +2385,7 @@
     break;
   }
   case ISD::SREM:
-    if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+    if (auto *Rem = dyn_cast<ConstantIntSDNode>(Op.getOperand(1))) {
       const APInt &RA = Rem->getAPIntValue().abs();
       if (RA.isPowerOf2()) {
         APInt LowBits = RA - 1;
@@ -2409,7 +2409,7 @@
     }
     break;
   case ISD::UREM: {
-    if (ConstantSDNode *Rem = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+    if (auto *Rem = dyn_cast<ConstantIntSDNode>(Op.getOperand(1))) {
       const APInt &RA = Rem->getAPIntValue();
       if (RA.isPowerOf2()) {
         APInt LowBits = (RA - 1);
@@ -2436,7 +2436,7 @@
   case ISD::EXTRACT_ELEMENT: {
     computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
     const unsigned Index =
-      cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
+        cast<ConstantIntSDNode>(Op.getOperand(1))->getZExtValue();
     const unsigned BitWidth = Op.getValueSizeInBits();
 
     // Remove low part of known bits mask
@@ -2515,7 +2515,7 @@
   // A left-shift of a constant one will have exactly one bit set because
   // shifting the bit off the end is undefined.
   if (Val.getOpcode() == ISD::SHL) {
-    auto *C = dyn_cast<ConstantSDNode>(Val.getOperand(0));
+    auto *C = dyn_cast<ConstantIntSDNode>(Val.getOperand(0));
     if (C && C->getAPIntValue() == 1)
       return true;
   }
@@ -2523,7 +2523,7 @@
   // Similarly, a logical right-shift of a constant sign-bit will have exactly
   // one bit set.
   if (Val.getOpcode() == ISD::SRL) {
-    auto *C = dyn_cast<ConstantSDNode>(Val.getOperand(0));
+    auto *C = dyn_cast<ConstantIntSDNode>(Val.getOperand(0));
     if (C && C->getAPIntValue().isSignBit())
       return true;
   }
@@ -2560,7 +2560,7 @@
     return VTBits-Tmp;
 
   case ISD::Constant: {
-    const APInt &Val = cast<ConstantSDNode>(Op)->getAPIntValue();
+    const APInt &Val = cast<ConstantIntSDNode>(Op)->getAPIntValue();
     return Val.getNumSignBits();
   }
 
@@ -2579,13 +2579,13 @@
   case ISD::SRA:
     Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
     // SRA X, C   -> adds C sign bits.
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op.getOperand(1))) {
       Tmp += C->getZExtValue();
       if (Tmp > VTBits) Tmp = VTBits;
     }
     return Tmp;
   case ISD::SHL:
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op.getOperand(1))) {
       // shl destroys sign bits.
       Tmp = ComputeNumSignBits(Op.getOperand(0), Depth+1);
       if (C->getZExtValue() >= VTBits ||      // Bad shift.
@@ -2650,7 +2650,7 @@
     break;
   case ISD::ROTL:
   case ISD::ROTR:
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op.getOperand(1))) {
       unsigned RotAmt = C->getZExtValue() & (VTBits-1);
 
       // Handle rotate right by N like a rotate left by 32-N.
@@ -2670,7 +2670,7 @@
     if (Tmp == 1) return 1;  // Early out.
 
     // Special case decrementing a value (ADD X, -1):
-    if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
+    if (auto *CRHS = dyn_cast<ConstantIntSDNode>(Op.getOperand(1)))
       if (CRHS->isAllOnesValue()) {
         APInt KnownZero, KnownOne;
         computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
@@ -2695,7 +2695,7 @@
     if (Tmp2 == 1) return 1;
 
     // Handle NEG.
-    if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)))
+    if (auto *CLHS = dyn_cast<ConstantIntSDNode>(Op.getOperand(0)))
       if (CLHS->isNullValue()) {
         APInt KnownZero, KnownOne;
         computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
@@ -2728,8 +2728,8 @@
 
     // Get reverse index (starting from 1), Op1 value indexes elements from
     // little end. Sign starts at big end.
-    const int rIndex = Items - 1 -
-      cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
+    const int rIndex =
+        Items - 1 - cast<ConstantIntSDNode>(Op.getOperand(1))->getZExtValue();
 
     // If the sign portion ends in our element the subtraction gives correct
     // result. Otherwise it gives either negative or > bitwidth result
@@ -2803,12 +2803,13 @@
 
 bool SelectionDAG::isBaseWithConstantOffset(SDValue Op) const {
   if ((Op.getOpcode() != ISD::ADD && Op.getOpcode() != ISD::OR) ||
-      !isa<ConstantSDNode>(Op.getOperand(1)))
+      !isa<ConstantIntSDNode>(Op.getOperand(1)))
     return false;
 
   if (Op.getOpcode() == ISD::OR &&
-      !MaskedValueIsZero(Op.getOperand(0),
-                     cast<ConstantSDNode>(Op.getOperand(1))->getAPIntValue()))
+      !MaskedValueIsZero(
+          Op.getOperand(0),
+          cast<ConstantIntSDNode>(Op.getOperand(1))->getAPIntValue()))
     return false;
 
   return true;
@@ -2837,7 +2838,7 @@
   switch (Op.getOpcode()) {
   default: break;
   case ISD::OR:
-    if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
+    if (const auto *C = dyn_cast<ConstantIntSDNode>(Op.getOperand(1)))
       return !C->isNullValue();
     break;
   }
@@ -2930,7 +2931,7 @@
   // doesn't create new constants with different values. Nevertheless, the
   // opaque flag is preserved during folding to prevent future folding with
   // other constants.
-  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand)) {
+  if (auto *C = dyn_cast<ConstantIntSDNode>(Operand)) {
     const APInt &Val = C->getAPIntValue();
     switch (Opcode) {
     default: break;
@@ -3210,7 +3211,7 @@
       return getUNDEF(VT);
     // scalar_to_vector(extract_vector_elt V, 0) -> V, top bits are undefined.
     if (OpOpcode == ISD::EXTRACT_VECTOR_ELT &&
-        isa<ConstantSDNode>(Operand.getOperand(1)) &&
+        isa<ConstantIntSDNode>(Operand.getOperand(1)) &&
         Operand.getConstantOperandVal(1) == 0 &&
         Operand.getOperand(0).getValueType() == VT)
       return Operand.getOperand(0);
@@ -3292,8 +3293,9 @@
 }
 
 SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL,
-                                             EVT VT, const ConstantSDNode *Cst1,
-                                             const ConstantSDNode *Cst2) {
+                                             EVT VT,
+                                             const ConstantIntSDNode *Cst1,
+                                             const ConstantIntSDNode *Cst2) {
   if (Cst1->isOpaque() || Cst2->isOpaque())
     return SDValue();
 
@@ -3311,7 +3313,7 @@
     return SDValue();
   if (!TLI->isOffsetFoldingLegal(GA))
     return SDValue();
-  const ConstantSDNode *Cst2 = dyn_cast<ConstantSDNode>(N2);
+  const auto *Cst2 = dyn_cast<ConstantIntSDNode>(N2);
   if (!Cst2)
     return SDValue();
   int64_t Offset = Cst2->getSExtValue();
@@ -3334,8 +3336,8 @@
     return SDValue();
 
   // Handle the case of two scalars.
-  if (const ConstantSDNode *Scalar1 = dyn_cast<ConstantSDNode>(Cst1)) {
-    if (const ConstantSDNode *Scalar2 = dyn_cast<ConstantSDNode>(Cst2)) {
+  if (const auto *Scalar1 = dyn_cast<ConstantIntSDNode>(Cst1)) {
+    if (const auto *Scalar2 = dyn_cast<ConstantIntSDNode>(Cst2)) {
       SDValue Folded = FoldConstantArithmetic(Opcode, DL, VT, Scalar1, Scalar2);
       assert((!Folded || !VT.isVector()) &&
              "Can't fold vectors ops with scalar operands");
@@ -3362,8 +3364,8 @@
   EVT SVT = VT.getScalarType();
   SmallVector<SDValue, 4> Outputs;
   for (unsigned I = 0, E = BV1->getNumOperands(); I != E; ++I) {
-    ConstantSDNode *V1 = dyn_cast<ConstantSDNode>(BV1->getOperand(I));
-    ConstantSDNode *V2 = dyn_cast<ConstantSDNode>(BV2->getOperand(I));
+    auto *V1 = dyn_cast<ConstantIntSDNode>(BV1->getOperand(I));
+    auto *V2 = dyn_cast<ConstantIntSDNode>(BV2->getOperand(I));
     if (!V1 || !V2) // Not a constant, bail.
       return SDValue();
 
@@ -3487,8 +3489,8 @@
 SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT,
                               SDValue N1, SDValue N2,
                               const SDNodeFlags *Flags) {
-  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
-  ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
+  auto *N1C = dyn_cast<ConstantIntSDNode>(N1);
+  auto *N2C = dyn_cast<ConstantIntSDNode>(N2);
   ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
   ConstantFPSDNode *N2CFP = dyn_cast<ConstantFPSDNode>(N2);
 
@@ -3679,7 +3681,7 @@
       const APInt &Val = N1C->getAPIntValue();
       return SignExtendInReg(Val);
     }
-    if (ISD::isBuildVectorOfConstantSDNodes(N1.getNode())) {
+    if (ISD::isBuildVectorOfConstantIntSDNodes(N1.getNode())) {
       SmallVector<SDValue, 8> Ops;
       for (int i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
         SDValue Op = N1.getOperand(i);
@@ -3687,7 +3689,7 @@
           Ops.push_back(getUNDEF(VT.getScalarType()));
           continue;
         }
-        if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+        if (auto *C = dyn_cast<ConstantIntSDNode>(Op)) {
           APInt Val = C->getAPIntValue();
           Val = Val.zextOrTrunc(VT.getScalarSizeInBits());
           Ops.push_back(SignExtendInReg(Val));
@@ -3743,7 +3745,7 @@
       // if the indices are known different, extract the element from
       // the original vector.
       SDValue N1Op2 = N1.getOperand(2);
-      ConstantSDNode *N1Op2C = dyn_cast<ConstantSDNode>(N1Op2);
+      auto *N1Op2C = dyn_cast<ConstantIntSDNode>(N1Op2);
 
       if (N1Op2C && N2C) {
         if (N1Op2C->getZExtValue() == N2C->getZExtValue()) {
@@ -4002,10 +4004,10 @@
     break;
   }
   case ISD::SELECT:
-    if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1)) {
-     if (N1C->getZExtValue())
-       return N2;             // select true, X, Y -> X
-     return N3;             // select false, X, Y -> Y
+    if (auto *N1C = dyn_cast<ConstantIntSDNode>(N1)) {
+      if (N1C->getZExtValue())
+        return N2; // select true, X, Y -> X
+      return N3;   // select false, X, Y -> Y
     }
 
     if (N2 == N3) return N2;   // select C, X, X -> X
@@ -4023,11 +4025,11 @@
              "Dest and insert subvector source types must match!");
       assert(N2.getSimpleValueType() <= N1.getSimpleValueType() &&
              "Insert subvector must be from smaller vector to larger vector!");
-      if (isa<ConstantSDNode>(Index)) {
+      if (isa<ConstantIntSDNode>(Index)) {
         assert((N2.getValueType().getVectorNumElements() +
-                cast<ConstantSDNode>(Index)->getZExtValue()
-                <= VT.getVectorNumElements())
-               && "Insert subvector overflow!");
+                    cast<ConstantIntSDNode>(Index)->getZExtValue() <=
+                VT.getVectorNumElements()) &&
+               "Insert subvector overflow!");
       }
 
       // Trivial insertion.
@@ -4108,7 +4110,7 @@
   assert(!Value.isUndef());
 
   unsigned NumBits = VT.getScalarSizeInBits();
-  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Value)) {
+  if (auto *C = dyn_cast<ConstantIntSDNode>(Value)) {
     assert(C->getAPIntValue().getBitWidth() == 8);
     APInt Val = APInt::getSplat(NumBits, C->getAPIntValue());
     if (VT.isInteger())
@@ -4200,7 +4202,7 @@
            Src.getOperand(0).getOpcode() == ISD::GlobalAddress &&
            Src.getOperand(1).getOpcode() == ISD::Constant) {
     G = cast<GlobalAddressSDNode>(Src.getOperand(0));
-    SrcDelta = cast<ConstantSDNode>(Src.getOperand(1))->getZExtValue();
+    SrcDelta = cast<ConstantIntSDNode>(Src.getOperand(1))->getZExtValue();
   }
   if (!G)
     return false;
@@ -4559,8 +4561,8 @@
   FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Dst);
   if (FI && !MFI.isFixedObjectIndex(FI->getIndex()))
     DstAlignCanChange = true;
-  bool IsZeroVal =
-    isa<ConstantSDNode>(Src) && cast<ConstantSDNode>(Src)->isNullValue();
+  bool IsZeroVal = isa<ConstantIntSDNode>(Src) &&
+                   cast<ConstantIntSDNode>(Src)->isNullValue();
   if (!FindOptimalMemOpLowering(MemOps, TLI.getMaxStoresPerMemset(OptSize),
                                 Size, (DstAlignCanChange ? 0 : Align), 0,
                                 true, IsZeroVal, false, true,
@@ -4642,7 +4644,7 @@
 
   // Check to see if we should lower the memcpy to loads and stores first.
   // For cases within the target-specified limits, this is the best choice.
-  ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
+  auto *ConstantSize = dyn_cast<ConstantIntSDNode>(Size);
   if (ConstantSize) {
     // Memcpy with size zero? Just return the original chain.
     if (ConstantSize->isNullValue())
@@ -4715,7 +4717,7 @@
 
   // Check to see if we should lower the memmove to loads and stores first.
   // For cases within the target-specified limits, this is the best choice.
-  ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
+  auto *ConstantSize = dyn_cast<ConstantIntSDNode>(Size);
   if (ConstantSize) {
     // Memmove with size zero? Just return the original chain.
     if (ConstantSize->isNullValue())
@@ -4775,7 +4777,7 @@
 
   // Check to see if we should lower the memset to stores first.
   // For cases within the target-specified limits, this is the best choice.
-  ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
+  auto *ConstantSize = dyn_cast<ConstantIntSDNode>(Size);
   if (ConstantSize) {
     // Memset with size zero? Just return the original chain.
     if (ConstantSize->isNullValue())
@@ -5057,14 +5059,14 @@
 
   // If this is (FI+Offset1)+Offset2, we can model it.
   if (Ptr.getOpcode() != ISD::ADD ||
-      !isa<ConstantSDNode>(Ptr.getOperand(1)) ||
+      !isa<ConstantIntSDNode>(Ptr.getOperand(1)) ||
       !isa<FrameIndexSDNode>(Ptr.getOperand(0)))
     return MachinePointerInfo();
 
   int FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex();
   return MachinePointerInfo::getFixedStack(
       DAG.getMachineFunction(), FI,
-      Offset + cast<ConstantSDNode>(Ptr.getOperand(1))->getSExtValue());
+      Offset + cast<ConstantIntSDNode>(Ptr.getOperand(1))->getSExtValue());
 }
 
 /// InferPointerInfo - If the specified ptr/offset is a frame index, infer a
@@ -5074,7 +5076,7 @@
 static MachinePointerInfo InferPointerInfo(SelectionDAG &DAG, SDValue Ptr,
                                            SDValue OffsetOp) {
   // If the 'Offset' value isn't a constant, we can't handle this.
-  if (ConstantSDNode *OffsetNode = dyn_cast<ConstantSDNode>(OffsetOp))
+  if (auto *OffsetNode = dyn_cast<ConstantIntSDNode>(OffsetOp))
     return InferPointerInfo(DAG, Ptr, OffsetNode->getSExtValue());
   if (OffsetOp.isUndef())
     return InferPointerInfo(DAG, Ptr);
@@ -5573,7 +5575,7 @@
         cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1)
       return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0));
     else if (N3.getOpcode() == ISD::AND)
-      if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) {
+      if (auto *AndRHS = dyn_cast<ConstantIntSDNode>(N3.getOperand(1))) {
         // If the and is only masking out bits that cannot effect the shift,
         // eliminate the and.
         unsigned NumBits = VT.getScalarSizeInBits()*2;
@@ -6645,7 +6647,7 @@
 //===----------------------------------------------------------------------===//
 
 bool llvm::isNullConstant(SDValue V) {
-  ConstantSDNode *Const = dyn_cast<ConstantSDNode>(V);
+  auto *Const = dyn_cast<ConstantIntSDNode>(V);
   return Const != nullptr && Const->isNullValue();
 }
 
@@ -6655,12 +6657,12 @@
 }
 
 bool llvm::isAllOnesConstant(SDValue V) {
-  ConstantSDNode *Const = dyn_cast<ConstantSDNode>(V);
+  auto *Const = dyn_cast<ConstantIntSDNode>(V);
   return Const != nullptr && Const->isAllOnesValue();
 }
 
 bool llvm::isOneConstant(SDValue V) {
-  ConstantSDNode *Const = dyn_cast<ConstantSDNode>(V);
+  auto *Const = dyn_cast<ConstantIntSDNode>(V);
   return Const != nullptr && Const->isOne();
 }
 
@@ -6838,7 +6840,7 @@
 
 uint64_t SDNode::getConstantOperandVal(unsigned Num) const {
   assert(Num < NumOperands && "Invalid child # of SDNode!");
-  return cast<ConstantSDNode>(OperandList[Num])->getZExtValue();
+  return cast<ConstantIntSDNode>(OperandList[Num])->getZExtValue();
 }
 
 const SDNodeFlags *SDNode::getFlags() const {
@@ -6952,7 +6954,8 @@
 
   // Handle X + C.
   if (isBaseWithConstantOffset(Loc)) {
-    int64_t LocOffset = cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue();
+    int64_t LocOffset =
+        cast<ConstantIntSDNode>(Loc.getOperand(1))->getSExtValue();
     if (Loc.getOperand(0) == BaseLoc) {
       // If the base location is a simple address with no offset itself, then
       // the second load's first add operand should be the base address.
@@ -6962,7 +6965,7 @@
       // The base location itself has an offset, so subtract that value from the
       // second load's offset before comparing to distance * size.
       int64_t BOffset =
-        cast<ConstantSDNode>(BaseLoc.getOperand(1))->getSExtValue();
+          cast<ConstantIntSDNode>(BaseLoc.getOperand(1))->getSExtValue();
       if (Loc.getOperand(0) == BaseLoc.getOperand(0)) {
         if ((LocOffset - BOffset) == Dist * (int)Bytes)
           return true;
@@ -7112,7 +7115,7 @@
 
     if (OpVal.isUndef())
       SplatUndef |= APInt::getBitsSet(sz, BitPos, BitPos + EltBitSize);
-    else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal))
+    else if (auto *CN = dyn_cast<ConstantIntSDNode>(OpVal))
       SplatValue |= CN->getAPIntValue().zextOrTrunc(EltBitSize).
                     zextOrTrunc(sz) << BitPos;
     else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal))
@@ -7175,9 +7178,9 @@
   return Splatted;
 }
 
-ConstantSDNode *
+ConstantIntSDNode *
 BuildVectorSDNode::getConstantSplatNode(BitVector *UndefElements) const {
-  return dyn_cast_or_null<ConstantSDNode>(getSplatValue(UndefElements));
+  return dyn_cast_or_null<ConstantIntSDNode>(getSplatValue(UndefElements));
 }
 
 ConstantFPSDNode *
@@ -7231,9 +7234,9 @@
 // \brief Returns the SDNode if it is a constant integer BuildVector
 // or constant integer.
 SDNode *SelectionDAG::isConstantIntBuildVectorOrConstantInt(SDValue N) {
-  if (isa<ConstantSDNode>(N))
+  if (isa<ConstantIntSDNode>(N))
     return N.getNode();
-  if (ISD::isBuildVectorOfConstantSDNodes(N.getNode()))
+  if (ISD::isBuildVectorOfConstantIntSDNodes(N.getNode()))
     return N.getNode();
   // Treat a GlobalAddress supporting constant offset folding as a
   // constant integer.
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -1042,7 +1042,7 @@
   // If we already have an SDValue for this value, use it.
   SDValue &N = NodeMap[V];
   if (N.getNode()) {
-    if (isa<ConstantSDNode>(N) || isa<ConstantFPSDNode>(N)) {
+    if (isa<ConstantIntSDNode>(N) || isa<ConstantFPSDNode>(N)) {
       // Remove the debug location from the node as the node is about to be used
       // in a location which may differ from the original debug location.  This
       // is relevant to Constant and ConstantFP nodes because they can appear
@@ -4580,7 +4580,7 @@
   // otherwise we end up lowering to a call to __powidf2 (for example).  When
   // optimizing for size, we only want to do this if the expansion would produce
   // a small number of multiplies, otherwise we do the full expansion.
-  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
+  if (auto *RHSC = dyn_cast<ConstantIntSDNode>(RHS)) {
     // Get the exponent as a positive value.
     unsigned Val = RHSC->getSExtValue();
     if ((int)Val < 0) Val = -Val;
@@ -5059,7 +5059,7 @@
   case Intrinsic::x86_mmx_psrai_w:
   case Intrinsic::x86_mmx_psrai_d: {
     SDValue ShAmt = getValue(I.getArgOperand(1));
-    if (isa<ConstantSDNode>(ShAmt)) {
+    if (isa<ConstantIntSDNode>(ShAmt)) {
       visitTargetIntrinsic(I, Intrinsic);
       return nullptr;
     }
@@ -6692,7 +6692,7 @@
   for (; OperandNo; --OperandNo) {
     // Advance to the next operand.
     unsigned OpFlag =
-        cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
+        cast<ConstantIntSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
     assert((InlineAsm::isRegDefKind(OpFlag) ||
             InlineAsm::isRegDefEarlyClobberKind(OpFlag) ||
             InlineAsm::isMemKind(OpFlag)) &&
@@ -6978,7 +6978,7 @@
         auto CurOp = findMatchingInlineAsmOperand(OpInfo.getMatchedOperand(),
                                                   AsmNodeOperands);
         unsigned OpFlag =
-          cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
+            cast<ConstantIntSDNode>(AsmNodeOperands[CurOp])->getZExtValue();
         if (InlineAsm::isRegDefKind(OpFlag) ||
             InlineAsm::isRegDefEarlyClobberKind(OpFlag)) {
           // Add (OpFlag&0xffff)>>3 registers to MatchedRegs.
@@ -7319,7 +7319,7 @@
                                 SelectionDAGBuilder &Builder) {
   for (unsigned i = StartIdx, e = CS.arg_size(); i != e; ++i) {
     SDValue OpVal = Builder.getValue(CS.getArgument(i));
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(OpVal)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(OpVal)) {
       Ops.push_back(
         Builder.DAG.getTargetConstant(StackMaps::ConstantOp, DL, MVT::i64));
       Ops.push_back(
@@ -7363,11 +7363,10 @@
   // Add the <id> and <numBytes> constants.
   SDValue IDVal = getValue(CI.getOperand(PatchPointOpers::IDPos));
   Ops.push_back(DAG.getTargetConstant(
-                  cast<ConstantSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
+      cast<ConstantIntSDNode>(IDVal)->getZExtValue(), DL, MVT::i64));
   SDValue NBytesVal = getValue(CI.getOperand(PatchPointOpers::NBytesPos));
   Ops.push_back(DAG.getTargetConstant(
-                  cast<ConstantSDNode>(NBytesVal)->getZExtValue(), DL,
-                  MVT::i32));
+      cast<ConstantIntSDNode>(NBytesVal)->getZExtValue(), DL, MVT::i32));
 
   // Push live variables for the stack map.
   addStackMapLiveVars(&CI, 2, DL, Ops, *this);
@@ -7413,7 +7412,7 @@
   SDValue Callee = getValue(CS->getOperand(PatchPointOpers::TargetPos));
 
   // Handle immediate and symbolic callees.
-  if (auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
+  if (auto *ConstCallee = dyn_cast<ConstantIntSDNode>(Callee))
     Callee = DAG.getIntPtrConstant(ConstCallee->getZExtValue(), dl,
                                    /*isTarget=*/true);
   else if (auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
@@ -7423,7 +7422,7 @@
 
   // Get the real number of arguments participating in the call <numArgs>
   SDValue NArgVal = getValue(CS.getArgument(PatchPointOpers::NArgPos));
-  unsigned NumArgs = cast<ConstantSDNode>(NArgVal)->getZExtValue();
+  unsigned NumArgs = cast<ConstantIntSDNode>(NArgVal)->getZExtValue();
 
   // Skip the four meta args: <id>, <numNopBytes>, <target>, <numArgs>
   // Intrinsics include all meta-operands up to but not including CC.
@@ -7458,11 +7457,10 @@
   // Add the <id> and <numBytes> constants.
   SDValue IDVal = getValue(CS->getOperand(PatchPointOpers::IDPos));
   Ops.push_back(DAG.getTargetConstant(
-                  cast<ConstantSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
+      cast<ConstantIntSDNode>(IDVal)->getZExtValue(), dl, MVT::i64));
   SDValue NBytesVal = getValue(CS->getOperand(PatchPointOpers::NBytesPos));
   Ops.push_back(DAG.getTargetConstant(
-                  cast<ConstantSDNode>(NBytesVal)->getZExtValue(), dl,
-                  MVT::i32));
+      cast<ConstantIntSDNode>(NBytesVal)->getZExtValue(), dl, MVT::i32));
 
   // Add the callee.
   Ops.push_back(Callee);
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
@@ -118,7 +118,7 @@
   case ISD::INTRINSIC_VOID:
   case ISD::INTRINSIC_W_CHAIN: {
     unsigned OpNo = getOpcode() == ISD::INTRINSIC_WO_CHAIN ? 0 : 1;
-    unsigned IID = cast<ConstantSDNode>(getOperand(OpNo))->getZExtValue();
+    unsigned IID = cast<ConstantIntSDNode>(getOperand(OpNo))->getZExtValue();
     if (IID < Intrinsic::num_intrinsics)
       return Intrinsic::getName((Intrinsic::ID)IID, None);
     else if (const TargetIntrinsicInfo *TII = G->getTarget().getIntrinsicInfo())
@@ -421,7 +421,7 @@
         OS << Idx;
     }
     OS << ">";
-  } else if (const ConstantSDNode *CSDN = dyn_cast<ConstantSDNode>(this)) {
+  } else if (const auto *CSDN = dyn_cast<ConstantIntSDNode>(this)) {
     OS << '<' << CSDN->getAPIntValue() << '>';
   } else if (const ConstantFPSDNode *CSDN = dyn_cast<ConstantFPSDNode>(this)) {
     if (&CSDN->getValueAPF().getSemantics()==&APFloat::IEEEsingle)
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -1921,7 +1921,7 @@
 /// the dag combiner simplified the 255, we still want to match.  RHS is the
 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value
 /// specified in the .td file (e.g. 255).
-bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
+bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantIntSDNode *RHS,
                                     int64_t DesiredMaskS) const {
   const APInt &ActualMask = RHS->getAPIntValue();
   const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
@@ -1950,7 +1950,7 @@
 /// the dag combiner simplified the 255, we still want to match.  RHS is the
 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value
 /// specified in the .td file (e.g. 255).
-bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
+bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantIntSDNode *RHS,
                                    int64_t DesiredMaskS) const {
   const APInt &ActualMask = RHS->getAPIntValue();
   const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS);
@@ -1997,7 +1997,7 @@
     --e;  // Don't process a glue operand if it is here.
 
   while (i != e) {
-    unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue();
+    unsigned Flags = cast<ConstantIntSDNode>(InOps[i])->getZExtValue();
     if (!InlineAsm::isMemKind(Flags)) {
       // Just skip over this operand, copying the operands verbatim.
       Ops.insert(Ops.end(), InOps.begin()+i,
@@ -2011,10 +2011,10 @@
       if (InlineAsm::isUseOperandTiedToDef(Flags, TiedToOperand)) {
         // We need the constraint ID from the operand this is tied to.
         unsigned CurOp = InlineAsm::Op_FirstOperand;
-        Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
+        Flags = cast<ConstantIntSDNode>(InOps[CurOp])->getZExtValue();
         for (; TiedToOperand; --TiedToOperand) {
           CurOp += InlineAsm::getNumOperandRegisters(Flags)+1;
-          Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue();
+          Flags = cast<ConstantIntSDNode>(InOps[CurOp])->getZExtValue();
         }
       }
 
@@ -2622,7 +2622,7 @@
   if (Val & 128)
     Val = GetVBR(Val, MatcherTable, MatcherIndex);
 
-  ConstantSDNode *C = dyn_cast<ConstantSDNode>(N);
+  auto *C = dyn_cast<ConstantIntSDNode>(N);
   return C && C->getSExtValue() == Val;
 }
 
@@ -2643,7 +2643,7 @@
 
   if (N->getOpcode() != ISD::AND) return false;
 
-  ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
+  auto *C = dyn_cast<ConstantIntSDNode>(N->getOperand(1));
   return C && SDISel.CheckAndMask(N.getOperand(0), C, Val);
 }
 
@@ -2656,7 +2656,7 @@
 
   if (N->getOpcode() != ISD::OR) return false;
 
-  ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
+  auto *C = dyn_cast<ConstantIntSDNode>(N->getOperand(1));
   return C && SDISel.CheckOrMask(N.getOperand(0), C, Val);
 }
 
@@ -3249,7 +3249,8 @@
       SDValue Imm = RecordedNodes[RecNo].first;
 
       if (Imm->getOpcode() == ISD::Constant) {
-        const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue();
+        const ConstantInt *Val =
+            cast<ConstantIntSDNode>(Imm)->getConstantIntValue();
         Imm = CurDAG->getTargetConstant(*Val, SDLoc(NodeToMatch),
                                         Imm.getValueType());
       } else if (Imm->getOpcode() == ISD::ConstantFP) {
@@ -3647,7 +3648,7 @@
   } else {
     bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other;
     unsigned iid =
-      cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue();
+        cast<ConstantIntSDNode>(N->getOperand(HasInputChain))->getZExtValue();
     if (iid < Intrinsic::num_intrinsics)
       Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid, None);
     else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo())
Index: llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
+++ llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
@@ -198,7 +198,7 @@
 
   SDValue Incoming = Builder.getValue(IncomingValue);
 
-  if (isa<ConstantSDNode>(Incoming) || isa<FrameIndexSDNode>(Incoming)) {
+  if (isa<ConstantIntSDNode>(Incoming) || isa<FrameIndexSDNode>(Incoming)) {
     // We won't need to spill this, so no need to check for previously
     // allocated stack slots
     return;
@@ -374,7 +374,7 @@
                                          SelectionDAGBuilder &Builder) {
   SDValue Chain = Builder.getRoot();
 
-  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Incoming)) {
+  if (auto *C = dyn_cast<ConstantIntSDNode>(Incoming)) {
     // If the original value was a constant, make sure it gets recorded as
     // such in the stackmap.  This is required so that the consumer can
     // parse any internal format to the deopt state.  It also handles null
Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -347,7 +347,7 @@
   case ISD::XOR:
   case ISD::AND:
   case ISD::OR: {
-    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
+    auto *C = dyn_cast<ConstantIntSDNode>(Op.getOperand(1));
     if (!C) return false;
 
     if (Op.getOpcode() == ISD::XOR &&
@@ -465,19 +465,19 @@
   switch (Op.getOpcode()) {
   case ISD::Constant:
     // We know all of the bits for a constant!
-    KnownOne = cast<ConstantSDNode>(Op)->getAPIntValue();
+    KnownOne = cast<ConstantIntSDNode>(Op)->getAPIntValue();
     KnownZero = ~KnownOne;
     return false;   // Don't fall through, will infinitely loop.
   case ISD::BUILD_VECTOR:
     // Collect the known bits that are shared by every constant vector element.
     KnownZero = KnownOne = APInt::getAllOnesValue(BitWidth);
     for (SDValue SrcOp : Op->ops()) {
-      if (!isa<ConstantSDNode>(SrcOp)) {
+      if (!isa<ConstantIntSDNode>(SrcOp)) {
         // We can only handle all constant values - bail out with no known bits.
         KnownZero = KnownOne = APInt(BitWidth, 0);
         return false;
       }
-      KnownOne2 = cast<ConstantSDNode>(SrcOp)->getAPIntValue();
+      KnownOne2 = cast<ConstantIntSDNode>(SrcOp)->getAPIntValue();
       KnownZero2 = ~KnownOne2;
 
       // BUILD_VECTOR can implicitly truncate sources, we must handle this.
@@ -500,7 +500,7 @@
     // using the bits from the RHS.  Below, we use knowledge about the RHS to
     // simplify the LHS, here we're using information from the LHS to simplify
     // the RHS.
-    if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+    if (auto *RHSC = dyn_cast<ConstantIntSDNode>(Op.getOperand(1))) {
       APInt LHSZero, LHSOne;
       // Do not increment Depth here; that can cause an infinite loop.
       TLO.DAG.computeKnownBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
@@ -627,7 +627,7 @@
     // If the RHS is a constant, see if we can simplify it.
     // for XOR, we prefer to force bits to 1 if they will make a -1.
     // if we can't force bits, try to shrink constant
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op.getOperand(1))) {
       APInt Expanded = C->getAPIntValue() | (~NewMask);
       // if we can expand it to have all bits set, do it
       if (Expanded.isAllOnesValue()) {
@@ -684,7 +684,7 @@
     KnownZero &= KnownZero2;
     break;
   case ISD::SHL:
-    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+    if (auto *SA = dyn_cast<ConstantIntSDNode>(Op.getOperand(1))) {
       unsigned ShAmt = SA->getZExtValue();
       SDValue InOp = Op.getOperand(0);
 
@@ -696,9 +696,10 @@
       // single shift.  We can do this if the bottom bits (which are shifted
       // out) are never demanded.
       if (InOp.getOpcode() == ISD::SRL &&
-          isa<ConstantSDNode>(InOp.getOperand(1))) {
+          isa<ConstantIntSDNode>(InOp.getOperand(1))) {
         if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) {
-          unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
+          unsigned C1 =
+              cast<ConstantIntSDNode>(InOp.getOperand(1))->getZExtValue();
           unsigned Opc = ISD::SHL;
           int Diff = ShAmt-C1;
           if (Diff < 0) {
@@ -742,12 +743,11 @@
         // (shl (anyext x), c2-c1).  This requires that the bottom c1 bits
         // aren't demanded (as above) and that the shifted upper c1 bits of
         // x aren't demanded.
-        if (InOp.hasOneUse() &&
-            InnerOp.getOpcode() == ISD::SRL &&
+        if (InOp.hasOneUse() && InnerOp.getOpcode() == ISD::SRL &&
             InnerOp.hasOneUse() &&
-            isa<ConstantSDNode>(InnerOp.getOperand(1))) {
-          uint64_t InnerShAmt = cast<ConstantSDNode>(InnerOp.getOperand(1))
-            ->getZExtValue();
+            isa<ConstantIntSDNode>(InnerOp.getOperand(1))) {
+          uint64_t InnerShAmt =
+              cast<ConstantIntSDNode>(InnerOp.getOperand(1))->getZExtValue();
           if (InnerShAmt < ShAmt &&
               InnerShAmt < InnerBits &&
               NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 &&
@@ -771,7 +771,7 @@
     }
     break;
   case ISD::SRL:
-    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+    if (auto *SA = dyn_cast<ConstantIntSDNode>(Op.getOperand(1))) {
       EVT VT = Op.getValueType();
       unsigned ShAmt = SA->getZExtValue();
       unsigned VTSize = VT.getSizeInBits();
@@ -792,9 +792,10 @@
       // single shift.  We can do this if the top bits (which are shifted out)
       // are never demanded.
       if (InOp.getOpcode() == ISD::SHL &&
-          isa<ConstantSDNode>(InOp.getOperand(1))) {
+          isa<ConstantIntSDNode>(InOp.getOperand(1))) {
         if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) {
-          unsigned C1= cast<ConstantSDNode>(InOp.getOperand(1))->getZExtValue();
+          unsigned C1 =
+              cast<ConstantIntSDNode>(InOp.getOperand(1))->getZExtValue();
           unsigned Opc = ISD::SRL;
           int Diff = ShAmt-C1;
           if (Diff < 0) {
@@ -831,7 +832,7 @@
                            TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(),
                                            Op.getOperand(0), Op.getOperand(1)));
 
-    if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+    if (auto *SA = dyn_cast<ConstantIntSDNode>(Op.getOperand(1))) {
       EVT VT = Op.getValueType();
       unsigned ShAmt = SA->getZExtValue();
 
@@ -1081,7 +1082,7 @@
           // Do not turn (vt1 truncate (vt2 srl)) into (vt1 srl) if vt1 is
           // undesirable.
           break;
-        ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(In.getOperand(1));
+        auto *ShAmt = dyn_cast<ConstantIntSDNode>(In.getOperand(1));
         if (!ShAmt)
           break;
         SDValue Shift = In.getOperand(1);
@@ -1187,7 +1188,7 @@
     for (SDNodeIterator I = SDNodeIterator::begin(N),
          E = SDNodeIterator::end(N); I != E; ++I) {
       SDNode *Op = *I;
-      if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
+      if (auto *C = dyn_cast<ConstantIntSDNode>(Op))
         if (C->isOpaque())
           return false;
     }
@@ -1232,7 +1233,7 @@
   if (!N)
     return false;
 
-  const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
+  const auto *CN = dyn_cast<ConstantIntSDNode>(N);
   if (!CN) {
     const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
     if (!BV)
@@ -1272,7 +1273,7 @@
   if (!N)
     return false;
 
-  const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
+  const auto *CN = dyn_cast<ConstantIntSDNode>(N);
   if (!CN) {
     const BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N);
     if (!BV)
@@ -1292,7 +1293,7 @@
   return CN->isNullValue();
 }
 
-bool TargetLowering::isExtendedTrueVal(const ConstantSDNode *N, EVT VT,
+bool TargetLowering::isExtendedTrueVal(const ConstantIntSDNode *N, EVT VT,
                                        bool SExt) const {
   if (VT == MVT::i1)
     return N->isOne();
@@ -1358,7 +1359,7 @@
 
     // Bail out if the compare operand that we want to turn into a zero is
     // already a zero (otherwise, infinite loop).
-    auto *YConst = dyn_cast<ConstantSDNode>(Y);
+    auto *YConst = dyn_cast<ConstantIntSDNode>(Y);
     if (YConst && YConst->isNullValue())
       return SDValue();
 
@@ -1397,12 +1398,12 @@
   // Ensure that the constant occurs on the RHS, and fold constant
   // comparisons.
   ISD::CondCode SwappedCC = ISD::getSetCCSwappedOperands(Cond);
-  if (isa<ConstantSDNode>(N0.getNode()) &&
+  if (isa<ConstantIntSDNode>(N0.getNode()) &&
       (DCI.isBeforeLegalizeOps() ||
        isCondCodeLegal(SwappedCC, N0.getSimpleValueType())))
     return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
 
-  if (auto *N1C = dyn_cast<ConstantSDNode>(N1.getNode())) {
+  if (auto *N1C = dyn_cast<ConstantIntSDNode>(N1.getNode())) {
     const APInt &C1 = N1C->getAPIntValue();
 
     // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
@@ -1411,8 +1412,8 @@
     if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) &&
         N0.getOperand(0).getOpcode() == ISD::CTLZ &&
         N0.getOperand(1).getOpcode() == ISD::Constant) {
-      const APInt &ShAmt
-        = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
+      const APInt &ShAmt =
+          cast<ConstantIntSDNode>(N0.getOperand(1))->getAPIntValue();
       if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
           ShAmt == Log2_32(N0.getValueSizeInBits())) {
         if ((C1 == 0) == (Cond == ISD::SETEQ)) {
@@ -1467,7 +1468,7 @@
         PreExt = N0->getOperand(0);
       } else if (N0->getOpcode() == ISD::AND) {
         // DAGCombine turns costly ZExts into ANDs
-        if (auto *C = dyn_cast<ConstantSDNode>(N0->getOperand(1)))
+        if (auto *C = dyn_cast<ConstantIntSDNode>(N0->getOperand(1)))
           if ((C->getAPIntValue()+1).isPowerOf2()) {
             MinBits = C->getAPIntValue().countTrailingOnes();
             PreExt = N0->getOperand(0);
@@ -1547,13 +1548,11 @@
     // If the LHS is '(and load, const)', the RHS is 0,
     // the test is for equality or unsigned, and all 1 bits of the const are
     // in the same partial word, see if we can shorten the load.
-    if (DCI.isBeforeLegalize() &&
-        !ISD::isSignedIntSetCC(Cond) &&
-        N0.getOpcode() == ISD::AND && C1 == 0 &&
-        N0.getNode()->hasOneUse() &&
+    if (DCI.isBeforeLegalize() && !ISD::isSignedIntSetCC(Cond) &&
+        N0.getOpcode() == ISD::AND && C1 == 0 && N0.getNode()->hasOneUse() &&
         isa<LoadSDNode>(N0.getOperand(0)) &&
         N0.getOperand(0).getNode()->hasOneUse() &&
-        isa<ConstantSDNode>(N0.getOperand(1))) {
+        isa<ConstantIntSDNode>(N0.getOperand(1))) {
       LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
       APInt bestMask;
       unsigned bestWidth = 0, bestOffset = 0;
@@ -1565,7 +1564,7 @@
         if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
           origWidth = Lod->getMemoryVT().getSizeInBits();
         const APInt &Mask =
-          cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
+            cast<ConstantIntSDNode>(N0.getOperand(1))->getAPIntValue();
         for (unsigned width = origWidth / 2; width>=8; width /= 2) {
           APInt newMask = APInt::getLowBitsSet(maskWidth, width);
           for (unsigned offset=0; offset<origWidth/width; offset++) {
@@ -1707,8 +1706,8 @@
            (N0.getOpcode() == ISD::AND &&
             N0.getOperand(0).getOpcode() == ISD::XOR &&
             N0.getOperand(1) == N0.getOperand(0).getOperand(1))) &&
-          isa<ConstantSDNode>(N0.getOperand(1)) &&
-          cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
+          isa<ConstantIntSDNode>(N0.getOperand(1)) &&
+          cast<ConstantIntSDNode>(N0.getOperand(1))->getAPIntValue() == 1) {
         // If this is (X^1) == 0/1, swap the RHS and eliminate the xor.  We
         // can only do this if the top bits are known zero.
         unsigned BitWidth = N0.getValueSizeInBits();
@@ -1748,8 +1747,8 @@
                               Cond);
         }
         if (Op0.getOpcode() == ISD::AND &&
-            isa<ConstantSDNode>(Op0.getOperand(1)) &&
-            cast<ConstantSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
+            isa<ConstantIntSDNode>(Op0.getOperand(1)) &&
+            cast<ConstantIntSDNode>(Op0.getOperand(1))->getAPIntValue() == 1) {
           // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0.
           if (Op0.getValueType().bitsGT(VT))
             Op0 = DAG.getNode(ISD::AND, dl, VT,
@@ -1865,7 +1864,7 @@
          (isTypeLegal(VT) && VT.bitsLE(N0.getValueType()))) &&
         N0.getOpcode() == ISD::AND) {
       auto &DL = DAG.getDataLayout();
-      if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
+      if (auto *AndRHS = dyn_cast<ConstantIntSDNode>(N0.getOperand(1))) {
         EVT ShiftTy = DCI.isBeforeLegalize()
                           ? getPointerTy(DL)
                           : getShiftAmountTy(N0.getValueType(), DL);
@@ -1895,7 +1894,7 @@
       // (X & -256) == 256 -> (X >> 8) == 1
       if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) &&
           N0.getOpcode() == ISD::AND && N0.hasOneUse()) {
-        if (auto *AndRHS = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
+        if (auto *AndRHS = dyn_cast<ConstantIntSDNode>(N0.getOperand(1))) {
           const APInt &AndRHSC = AndRHS->getAPIntValue();
           if ((-AndRHSC).isPowerOf2() && (AndRHSC & C1) == C1) {
             unsigned ShiftBits = AndRHSC.countTrailingZeros();
@@ -2066,8 +2065,8 @@
       // to be careful about increasing register pressure needlessly.
       bool LegalRHSImm = false;
 
-      if (auto *RHSC = dyn_cast<ConstantSDNode>(N1)) {
-        if (auto *LHSR = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
+      if (auto *RHSC = dyn_cast<ConstantIntSDNode>(N1)) {
+        if (auto *LHSR = dyn_cast<ConstantIntSDNode>(N0.getOperand(1))) {
           // Turn (X+C1) == C2 --> X == C2-C1
           if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) {
             return DAG.getSetCC(dl, VT, N0.getOperand(0),
@@ -2090,7 +2089,7 @@
         }
 
         // Turn (C1-X) == C2 --> X == C1-C2
-        if (auto *SUBC = dyn_cast<ConstantSDNode>(N0.getOperand(0))) {
+        if (auto *SUBC = dyn_cast<ConstantIntSDNode>(N0.getOperand(0))) {
           if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) {
             return
               DAG.getSetCC(dl, VT, N0.getOperand(1),
@@ -2231,12 +2230,12 @@
     SDValue N1 = N->getOperand(0);
     SDValue N2 = N->getOperand(1);
     if (isGAPlusOffset(N1.getNode(), GA, Offset)) {
-      if (auto *V = dyn_cast<ConstantSDNode>(N2)) {
+      if (auto *V = dyn_cast<ConstantIntSDNode>(N2)) {
         Offset += V->getSExtValue();
         return true;
       }
     } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) {
-      if (auto *V = dyn_cast<ConstantSDNode>(N1)) {
+      if (auto *V = dyn_cast<ConstantIntSDNode>(N1)) {
         Offset += V->getSExtValue();
         return true;
       }
@@ -2332,15 +2331,15 @@
     // These operands are interested in values of the form (GV+C), where C may
     // be folded in as an offset of GV, or it may be explicitly added.  Also, it
     // is possible and fine if either GV or C are missing.
-    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
+    auto *C = dyn_cast<ConstantIntSDNode>(Op);
     GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op);
 
     // If we have "(add GV, C)", pull out GV/C
     if (Op.getOpcode() == ISD::ADD) {
-      C = dyn_cast<ConstantSDNode>(Op.getOperand(1));
+      C = dyn_cast<ConstantIntSDNode>(Op.getOperand(1));
       GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(0));
       if (!C || !GA) {
-        C = dyn_cast<ConstantSDNode>(Op.getOperand(0));
+        C = dyn_cast<ConstantIntSDNode>(Op.getOperand(0));
         GA = dyn_cast<GlobalAddressSDNode>(Op.getOperand(1));
       }
       if (!C || !GA) {
@@ -3002,7 +3001,7 @@
 
 bool TargetLowering::
 verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const {
-  if (!isa<ConstantSDNode>(Op.getOperand(0))) {
+  if (!isa<ConstantIntSDNode>(Op.getOperand(0))) {
     DAG.getContext()->emitError("argument to '__builtin_return_address' must "
                                 "be a constant integer");
     return true;
@@ -3594,7 +3593,7 @@
     return SDValue();
   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
   SDLoc dl(Op);
-  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+  if (auto *C = dyn_cast<ConstantIntSDNode>(Op.getOperand(1))) {
     if (C->isNullValue() && CC == ISD::SETEQ) {
       EVT VT = Op.getOperand(0).getValueType();
       SDValue Zext = Op.getOperand(0);
Index: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -208,7 +208,7 @@
 /// isIntImmediate - This method tests to see if the node is a constant
 /// operand. If so Imm will receive the 32-bit value.
 static bool isIntImmediate(const SDNode *N, uint64_t &Imm) {
-  if (const ConstantSDNode *C = dyn_cast<const ConstantSDNode>(N)) {
+  if (const ConstantIntSDNode *C = dyn_cast<const ConstantIntSDNode>(N)) {
     Imm = C->getZExtValue();
     return true;
   }
@@ -257,10 +257,10 @@
   // we still need to check whether the operand is actually an immediate
   // here because the ComplexPattern opcode list is only used in
   // root-level opcode matching.
-  if (!isa<ConstantSDNode>(N.getNode()))
+  if (!isa<ConstantIntSDNode>(N.getNode()))
     return false;
 
-  uint64_t Immed = cast<ConstantSDNode>(N.getNode())->getZExtValue();
+  uint64_t Immed = cast<ConstantIntSDNode>(N.getNode())->getZExtValue();
   unsigned ShiftAmt;
 
   if (Immed >> 12 == 0) {
@@ -287,11 +287,11 @@
   // we still need to check whether the operand is actually an immediate
   // here because the ComplexPattern opcode list is only used in
   // root-level opcode matching.
-  if (!isa<ConstantSDNode>(N.getNode()))
+  if (!isa<ConstantIntSDNode>(N.getNode()))
     return false;
 
   // The immediate operand must be a 24-bit zero-extended immediate.
-  uint64_t Immed = cast<ConstantSDNode>(N.getNode())->getZExtValue();
+  uint64_t Immed = cast<ConstantIntSDNode>(N.getNode())->getZExtValue();
 
   // This negation is almost always valid, but "cmp wN, #0" and "cmn wN, #0"
   // have the opposite effect on the C flag, so this pattern mustn't match under
@@ -348,7 +348,7 @@
   if (!AllowROR && ShType == AArch64_AM::ROR)
     return false;
 
-  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
+  if (auto *RHS = dyn_cast<ConstantIntSDNode>(N.getOperand(1))) {
     unsigned BitSize = N.getValueSizeInBits();
     unsigned Val = RHS->getZExtValue() & (BitSize - 1);
     unsigned ShVal = AArch64_AM::getShifterImm(ShType, Val);
@@ -395,7 +395,7 @@
 
     return AArch64_AM::InvalidShiftExtend;
   } else if (N.getOpcode() == ISD::AND) {
-    ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
+    auto *CSD = dyn_cast<ConstantIntSDNode>(N.getOperand(1));
     if (!CSD)
       return AArch64_AM::InvalidShiftExtend;
     uint64_t AndMask = CSD->getZExtValue();
@@ -429,8 +429,8 @@
   if (EV.getOpcode() != ISD::EXTRACT_SUBVECTOR)
     return false;
 
-  ConstantSDNode *DLidx = cast<ConstantSDNode>(DL->getOperand(1).getNode());
-  ConstantSDNode *EVidx = cast<ConstantSDNode>(EV.getOperand(1).getNode());
+  auto *DLidx = cast<ConstantIntSDNode>(DL->getOperand(1).getNode());
+  auto *EVidx = cast<ConstantIntSDNode>(EV.getOperand(1).getNode());
   LaneIdx = DLidx->getSExtValue() + EVidx->getSExtValue();
   LaneOp = EV.getOperand(0);
 
@@ -568,7 +568,7 @@
   AArch64_AM::ShiftExtendType Ext;
 
   if (N.getOpcode() == ISD::SHL) {
-    ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
+    auto *CSD = dyn_cast<ConstantIntSDNode>(N.getOperand(1));
     if (!CSD)
       return false;
     ShiftVal = CSD->getZExtValue();
@@ -646,7 +646,7 @@
   // selected here doesn't support labels/immediates, only base+offset.
 
   if (CurDAG->isBaseWithConstantOffset(N)) {
-    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
+    if (auto *RHS = dyn_cast<ConstantIntSDNode>(N.getOperand(1))) {
       int64_t RHSC = RHS->getSExtValue();
       unsigned Scale = Log2_32(Size);
       if ((RHSC & (Size - 1)) == 0 && RHSC >= -(0x40 << Scale) &&
@@ -705,7 +705,7 @@
   }
 
   if (CurDAG->isBaseWithConstantOffset(N)) {
-    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
+    if (auto *RHS = dyn_cast<ConstantIntSDNode>(N.getOperand(1))) {
       int64_t RHSC = (int64_t)RHS->getZExtValue();
       unsigned Scale = Log2_32(Size);
       if ((RHSC & (Size - 1)) == 0 && RHSC >= 0 && RHSC < (0x1000 << Scale)) {
@@ -744,7 +744,7 @@
                                                  SDValue &OffImm) {
   if (!CurDAG->isBaseWithConstantOffset(N))
     return false;
-  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
+  if (auto *RHS = dyn_cast<ConstantIntSDNode>(N.getOperand(1))) {
     int64_t RHSC = RHS->getSExtValue();
     // If the offset is valid as a scaled immediate, don't match here.
     if ((RHSC & (Size - 1)) == 0 && RHSC >= 0 &&
@@ -781,7 +781,7 @@
                                             bool WantExtend, SDValue &Offset,
                                             SDValue &SignExtend) {
   assert(N.getOpcode() == ISD::SHL && "Invalid opcode.");
-  ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
+  auto *CSD = dyn_cast<ConstantIntSDNode>(N.getOperand(1));
   if (!CSD || (CSD->getZExtValue() & 0x7) != CSD->getZExtValue())
     return false;
 
@@ -821,7 +821,7 @@
 
   // We don't want to match immediate adds here, because they are better lowered
   // to the register-immediate addressing modes.
-  if (isa<ConstantSDNode>(LHS) || isa<ConstantSDNode>(RHS))
+  if (isa<ConstantIntSDNode>(LHS) || isa<ConstantIntSDNode>(RHS))
     return false;
 
   // Check if this particular node is reused in any non-memory related
@@ -928,8 +928,8 @@
   // ADD/SUB:
   //     MOV  X0, WideImmediate
   //     LDR  X2, [BaseReg, X0]
-  if (isa<ConstantSDNode>(RHS)) {
-    int64_t ImmOff = (int64_t)cast<ConstantSDNode>(RHS)->getZExtValue();
+  if (isa<ConstantIntSDNode>(RHS)) {
+    int64_t ImmOff = (int64_t)cast<ConstantIntSDNode>(RHS)->getZExtValue();
     unsigned Scale = Log2_32(Size);
     // Skip the immediate can be selected by load/store addressing mode.
     // Also skip the immediate can be encoded by a single ADD (SUB is also
@@ -1110,7 +1110,7 @@
     return false;
   SDValue Chain = LD->getChain();
   SDValue Base = LD->getBasePtr();
-  ConstantSDNode *OffsetOp = cast<ConstantSDNode>(LD->getOffset());
+  auto *OffsetOp = cast<ConstantIntSDNode>(LD->getOffset());
   int OffsetVal = (int)OffsetOp->getZExtValue();
   SDLoc dl(N);
   SDValue Offset = CurDAG->getTargetConstant(OffsetVal, dl, MVT::i64);
@@ -1279,7 +1279,7 @@
   const EVT ResTys[] = {MVT::Untyped, MVT::Other};
 
   unsigned LaneNo =
-      cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
+      cast<ConstantIntSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
 
   SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64),
                    N->getOperand(NumVecs + 3), N->getOperand(0)};
@@ -1319,7 +1319,7 @@
                         RegSeq->getValueType(0), MVT::Other};
 
   unsigned LaneNo =
-      cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
+      cast<ConstantIntSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
 
   SDValue Ops[] = {RegSeq,
                    CurDAG->getTargetConstant(LaneNo, dl,
@@ -1371,7 +1371,7 @@
   SDValue RegSeq = createQTuple(Regs);
 
   unsigned LaneNo =
-      cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
+      cast<ConstantIntSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
 
   SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64),
                    N->getOperand(NumVecs + 3), N->getOperand(0)};
@@ -1404,7 +1404,7 @@
                         MVT::Other};
 
   unsigned LaneNo =
-      cast<ConstantSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
+      cast<ConstantIntSDNode>(N->getOperand(NumVecs + 1))->getZExtValue();
 
   SDValue Ops[] = {RegSeq, CurDAG->getTargetConstant(LaneNo, dl, MVT::i64),
                    N->getOperand(NumVecs + 2), // Base Register
@@ -1713,8 +1713,8 @@
   case AArch64::UBFMXri:
     Opc = NOpc;
     Opd0 = N->getOperand(0);
-    Immr = cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
-    Imms = cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
+    Immr = cast<ConstantIntSDNode>(N->getOperand(1).getNode())->getZExtValue();
+    Imms = cast<ConstantIntSDNode>(N->getOperand(2).getNode())->getZExtValue();
     return true;
   }
   // Unreachable
@@ -1786,7 +1786,7 @@
 static void getUsefulBitsFromAndWithImmediate(SDValue Op, APInt &UsefulBits,
                                               unsigned Depth) {
   uint64_t Imm =
-      cast<const ConstantSDNode>(Op.getOperand(1).getNode())->getZExtValue();
+      cast<const ConstantIntSDNode>(Op.getOperand(1).getNode())->getZExtValue();
   Imm = AArch64_AM::decodeLogicalImmediate(Imm, UsefulBits.getBitWidth());
   UsefulBits &= APInt(UsefulBits.getBitWidth(), Imm);
   getUsefulBits(Op, UsefulBits, Depth + 1);
@@ -1822,9 +1822,9 @@
 static void getUsefulBitsFromUBFM(SDValue Op, APInt &UsefulBits,
                                   unsigned Depth) {
   uint64_t Imm =
-      cast<const ConstantSDNode>(Op.getOperand(1).getNode())->getZExtValue();
+      cast<const ConstantIntSDNode>(Op.getOperand(1).getNode())->getZExtValue();
   uint64_t MSB =
-      cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
+      cast<const ConstantIntSDNode>(Op.getOperand(2).getNode())->getZExtValue();
 
   getUsefulBitsFromBitfieldMoveOpd(Op, UsefulBits, Imm, MSB, Depth);
 }
@@ -1832,7 +1832,7 @@
 static void getUsefulBitsFromOrWithShiftedReg(SDValue Op, APInt &UsefulBits,
                                               unsigned Depth) {
   uint64_t ShiftTypeAndValue =
-      cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
+      cast<const ConstantIntSDNode>(Op.getOperand(2).getNode())->getZExtValue();
   APInt Mask(UsefulBits);
   Mask.clearAllBits();
   Mask.flipAllBits();
@@ -1860,9 +1860,9 @@
 static void getUsefulBitsFromBFM(SDValue Op, SDValue Orig, APInt &UsefulBits,
                                  unsigned Depth) {
   uint64_t Imm =
-      cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
+      cast<const ConstantIntSDNode>(Op.getOperand(2).getNode())->getZExtValue();
   uint64_t MSB =
-      cast<const ConstantSDNode>(Op.getOperand(3).getNode())->getZExtValue();
+      cast<const ConstantIntSDNode>(Op.getOperand(3).getNode())->getZExtValue();
 
   if (Op.getOperand(1) == Orig)
     return getUsefulBitsFromBitfieldMoveOpd(Op, UsefulBits, Imm, MSB, Depth);
@@ -2486,10 +2486,10 @@
   // the case as it has been ensured by semantic checking.
   auto PMapper = AArch64PState::lookupPStateByName(RegString->getString());;
   if (PMapper) {
-    assert (isa<ConstantSDNode>(N->getOperand(2))
-              && "Expected a constant integer expression.");
+    assert(isa<ConstantIntSDNode>(N->getOperand(2)) &&
+           "Expected a constant integer expression.");
     unsigned Reg = PMapper->Encoding;
-    uint64_t Immed = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
+    uint64_t Immed = cast<ConstantIntSDNode>(N->getOperand(2))->getZExtValue();
     unsigned State;
     if (Reg == AArch64PState::PAN || Reg == AArch64PState::UAO) {
       assert(Immed < 2 && "Bad imm");
@@ -2630,7 +2630,7 @@
     // the rest of the compiler, especially the register allocator and copyi
     // propagation, to reason about, so is preferred when it's possible to
     // use it.
-    ConstantSDNode *LaneNode = cast<ConstantSDNode>(Node->getOperand(1));
+    auto *LaneNode = cast<ConstantIntSDNode>(Node->getOperand(1));
     // Bail and use the default Select() for non-zero lanes.
     if (LaneNode->getZExtValue() != 0)
       break;
@@ -2670,7 +2670,7 @@
   case ISD::Constant: {
     // Materialize zero constants as copies from WZR/XZR.  This allows
     // the coalescer to propagate these into other instructions.
-    ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);
+    auto *ConstNode = cast<ConstantIntSDNode>(Node);
     if (ConstNode->isNullValue()) {
       if (VT == MVT::i32) {
         SDValue New = CurDAG->getCopyFromReg(
@@ -2701,7 +2701,8 @@
     return;
   }
   case ISD::INTRINSIC_W_CHAIN: {
-    unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
+    unsigned IntNo =
+        cast<ConstantIntSDNode>(Node->getOperand(1))->getZExtValue();
     switch (IntNo) {
     default:
       break;
@@ -3045,7 +3046,8 @@
     }
   } break;
   case ISD::INTRINSIC_WO_CHAIN: {
-    unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
+    unsigned IntNo =
+        cast<ConstantIntSDNode>(Node->getOperand(0))->getZExtValue();
     switch (IntNo) {
     default:
       break;
@@ -3088,7 +3090,8 @@
     break;
   }
   case ISD::INTRINSIC_VOID: {
-    unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
+    unsigned IntNo =
+        cast<ConstantIntSDNode>(Node->getOperand(1))->getZExtValue();
     if (Node->getNumOperands() >= 3)
       VT = Node->getOperand(2)->getValueType(0);
     switch (IntNo) {
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -755,7 +755,7 @@
     break;
   }
   case ISD::INTRINSIC_W_CHAIN: {
-    ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
+    auto *CN = cast<ConstantIntSDNode>(Op->getOperand(1));
     Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
     switch (IntID) {
     default: return;
@@ -772,7 +772,7 @@
   }
   case ISD::INTRINSIC_WO_CHAIN:
   case ISD::INTRINSIC_VOID: {
-    unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+    unsigned IntNo = cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
     switch (IntNo) {
     default:
       break;
@@ -1510,7 +1510,7 @@
 static SDValue getAArch64Cmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
                              SDValue &AArch64cc, SelectionDAG &DAG,
                              const SDLoc &dl) {
-  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
+  if (auto *RHSC = dyn_cast<ConstantIntSDNode>(RHS.getNode())) {
     EVT VT = RHS.getValueType();
     uint64_t C = RHSC->getZExtValue();
     if (!isLegalArithImmed(C)) {
@@ -1566,8 +1566,8 @@
   }
   SDValue Cmp;
   AArch64CC::CondCode AArch64CC;
-  if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantSDNode>(RHS)) {
-    const ConstantSDNode *RHSC = cast<ConstantSDNode>(RHS);
+  if ((CC == ISD::SETEQ || CC == ISD::SETNE) && isa<ConstantIntSDNode>(RHS)) {
+    const auto *RHSC = cast<ConstantIntSDNode>(RHS);
 
     // The imm operand of ADDS is an unsigned immediate, in the range 0 to 4095.
     // For the i8 operand, the largest immediate is 255, so this can be easily
@@ -1589,7 +1589,7 @@
         cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
         cast<LoadSDNode>(LHS)->getMemoryVT() == MVT::i16 &&
         LHS.getNode()->hasNUsesOfValue(1, 0)) {
-      int16_t ValueofRHS = cast<ConstantSDNode>(RHS)->getZExtValue();
+      int16_t ValueofRHS = cast<ConstantIntSDNode>(RHS)->getZExtValue();
       if (ValueofRHS < 0 && isLegalArithImmed(-ValueofRHS)) {
         SDValue SExt =
             DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, LHS.getValueType(), LHS,
@@ -1766,8 +1766,8 @@
   if (LHS.getValueType() != MVT::i32 && LHS.getValueType() != MVT::i64)
     return Op;
 
-  ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
-  ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
+  auto *CFVal = dyn_cast<ConstantIntSDNode>(FVal);
+  auto *CTVal = dyn_cast<ConstantIntSDNode>(TVal);
 
   // The values aren't constants, this isn't the pattern we're looking for.
   if (!CFVal || !CTVal)
@@ -1866,9 +1866,9 @@
 // 4: bool isDataCache
 static SDValue LowerPREFETCH(SDValue Op, SelectionDAG &DAG) {
   SDLoc DL(Op);
-  unsigned IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
-  unsigned Locality = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
-  unsigned IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
+  unsigned IsWrite = cast<ConstantIntSDNode>(Op.getOperand(2))->getZExtValue();
+  unsigned Locality = cast<ConstantIntSDNode>(Op.getOperand(3))->getZExtValue();
+  unsigned IsData = cast<ConstantIntSDNode>(Op.getOperand(4))->getZExtValue();
 
   bool IsStream = !Locality;
   // When the locality number is set
@@ -2133,7 +2133,7 @@
     return false;
 
   for (const SDValue &Elt : N->op_values()) {
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Elt)) {
       unsigned EltSize = VT.getScalarSizeInBits();
       unsigned HalfSize = EltSize / 2;
       if (isSigned) {
@@ -2166,7 +2166,7 @@
   MVT TruncVT = MVT::getIntegerVT(EltSize);
   SmallVector<SDValue, 8> Ops;
   for (unsigned i = 0; i != NumElts; ++i) {
-    ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
+    auto *C = cast<ConstantIntSDNode>(N->getOperand(i));
     const APInt &CInt = C->getAPIntValue();
     // Element types smaller than 32 bits are not legal, so use i32 elements.
     // The values are implicitly truncated so sext vs. zext doesn't matter.
@@ -2284,7 +2284,7 @@
 
 SDValue AArch64TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
                                                      SelectionDAG &DAG) const {
-  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned IntNo = cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
   SDLoc dl(Op);
   switch (IntNo) {
   default: return SDValue();    // Don't custom lower most intrinsics.
@@ -3681,7 +3681,7 @@
 
     // If the RHS of the comparison is zero, we can potentially fold this
     // to a specialized branch.
-    const ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS);
+    const auto *RHSC = dyn_cast<ConstantIntSDNode>(RHS);
     if (RHSC && RHSC->getZExtValue() == 0) {
       if (CC == ISD::SETEQ) {
         // See if we can use a TBZ to fold in an AND as well.
@@ -3689,7 +3689,7 @@
         // out of bounds, a late MI-layer pass rewrites branches.
         // 403.gcc is an example that hits this case.
         if (LHS.getOpcode() == ISD::AND &&
-            isa<ConstantSDNode>(LHS.getOperand(1)) &&
+            isa<ConstantIntSDNode>(LHS.getOperand(1)) &&
             isPowerOf2_64(LHS.getConstantOperandVal(1))) {
           SDValue Test = LHS.getOperand(0);
           uint64_t Mask = LHS.getConstantOperandVal(1);
@@ -3705,7 +3705,7 @@
         // out of bounds, a late MI-layer pass rewrites branches.
         // 403.gcc is an example that hits this case.
         if (LHS.getOpcode() == ISD::AND &&
-            isa<ConstantSDNode>(LHS.getOperand(1)) &&
+            isa<ConstantIntSDNode>(LHS.getOperand(1)) &&
             isPowerOf2_64(LHS.getConstantOperandVal(1))) {
           SDValue Test = LHS.getOperand(0);
           uint64_t Mask = LHS.getConstantOperandVal(1);
@@ -3972,8 +3972,8 @@
 
     // If both the TVal and the FVal are constants, see if we can swap them in
     // order to for a CSINV or CSINC out of them.
-    ConstantSDNode *CFVal = dyn_cast<ConstantSDNode>(FVal);
-    ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);
+    auto *CFVal = dyn_cast<ConstantIntSDNode>(FVal);
+    auto *CTVal = dyn_cast<ConstantIntSDNode>(TVal);
 
     if (CTVal && CFVal && CTVal->isAllOnesValue() && CFVal->isNullValue()) {
       std::swap(TVal, FVal);
@@ -4054,7 +4054,7 @@
     // a register.  However, don't perform this optimization if the known value
     // is one, zero or negative one.  We can always materialize these values
     // using CSINC, CSEL and CSINV with wzr/xzr as the FVal, respectively.
-    ConstantSDNode *RHSVal = dyn_cast<ConstantSDNode>(RHS);
+    auto *RHSVal = dyn_cast<ConstantIntSDNode>(RHS);
     if (Opcode == AArch64ISD::CSEL && RHSVal && !RHSVal->isOne() &&
         !RHSVal->isNullValue() && !RHSVal->isAllOnesValue()) {
       AArch64CC::CondCode AArch64CC = changeIntCCToAArch64CC(CC);
@@ -4413,7 +4413,7 @@
 
   EVT VT = Op.getValueType();
   SDLoc DL(Op);
-  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned Depth = cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
   SDValue FrameAddr =
       DAG.getCopyFromReg(DAG.getEntryNode(), DL, AArch64::FP, VT);
   while (Depth--)
@@ -4443,7 +4443,7 @@
 
   EVT VT = Op.getValueType();
   SDLoc DL(Op);
-  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned Depth = cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
   if (Depth) {
     SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
     SDValue Offset = DAG.getConstant(8, DL, getPointerTy(DAG.getDataLayout()));
@@ -4784,7 +4784,7 @@
   case 'L':
   case 'M':
   case 'N':
-    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
+    auto *C = dyn_cast<ConstantIntSDNode>(Op);
     if (!C)
       return;
 
@@ -4959,7 +4959,7 @@
     if (V.isUndef())
       continue;
     else if (V.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
-             !isa<ConstantSDNode>(V.getOperand(1))) {
+             !isa<ConstantIntSDNode>(V.getOperand(1))) {
       // A shuffle can only come from building a vector from various
       // elements of other vectors, provided their indices are constant.
       return SDValue();
@@ -4972,7 +4972,7 @@
       Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
 
     // Update the minimum and maximum lane number seen.
-    unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
+    unsigned EltNo = cast<ConstantIntSDNode>(V.getOperand(1))->getZExtValue();
     Source->MinElt = std::min(Source->MinElt, EltNo);
     Source->MaxElt = std::max(Source->MaxElt, EltNo);
   }
@@ -5084,7 +5084,7 @@
       continue;
 
     auto Src = find(Sources, Entry.getOperand(0));
-    int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
+    int EltNo = cast<ConstantIntSDNode>(Entry.getOperand(1))->getSExtValue();
 
     // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
     // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
@@ -5601,7 +5601,7 @@
     // Test if V1 is a BUILD_VECTOR and the lane being referenced is a non-
     // constant. If so, we can just reference the lane's definition directly.
     if (V1.getOpcode() == ISD::BUILD_VECTOR &&
-        !isa<ConstantSDNode>(V1.getOperand(Lane)))
+        !isa<ConstantIntSDNode>(V1.getOperand(Lane)))
       return DAG.getNode(AArch64ISD::DUP, dl, VT, V1.getOperand(Lane));
 
     // Otherwise, duplicate from the lane of the input vector.
@@ -5611,7 +5611,7 @@
     // to make a vector of the same size as this SHUFFLE. We can ignore the
     // extract entirely, and canonicalise the concat using WidenVector.
     if (V1.getOpcode() == ISD::EXTRACT_SUBVECTOR) {
-      Lane += cast<ConstantSDNode>(V1.getOperand(1))->getZExtValue();
+      Lane += cast<ConstantIntSDNode>(V1.getOperand(1))->getZExtValue();
       V1 = V1.getOperand(0);
     } else if (V1.getOpcode() == ISD::CONCAT_VECTORS) {
       unsigned Idx = Lane >= (int)VT.getVectorNumElements() / 2;
@@ -5848,13 +5848,13 @@
   BuildVectorSDNode *Bvec = dyn_cast<BuildVectorSDNode>(PotentialBVec);
   if (!Bvec)
     return false;
-  ConstantSDNode *FirstElt = dyn_cast<ConstantSDNode>(Bvec->getOperand(0));
+  auto *FirstElt = dyn_cast<ConstantIntSDNode>(Bvec->getOperand(0));
   if (!FirstElt)
     return false;
   EVT VT = Bvec->getValueType(0);
   unsigned NumElts = VT.getVectorNumElements();
   for (unsigned i = 1; i < NumElts; ++i)
-    if (dyn_cast<ConstantSDNode>(Bvec->getOperand(i)) != FirstElt)
+    if (dyn_cast<ConstantIntSDNode>(Bvec->getOperand(i)) != FirstElt)
       return false;
   ConstVal = FirstElt->getZExtValue();
   return true;
@@ -5866,7 +5866,7 @@
   default:
     return Intrinsic::not_intrinsic;
   case ISD::INTRINSIC_WO_CHAIN: {
-    unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
+    unsigned IID = cast<ConstantIntSDNode>(N->getOperand(0))->getZExtValue();
     if (IID < Intrinsic::num_intrinsics)
       return IID;
     return Intrinsic::not_intrinsic;
@@ -5901,7 +5901,7 @@
   bool IsShiftRight = ShiftOpc == AArch64ISD::VLSHR;
 
   // Is the shift amount constant?
-  ConstantSDNode *C2node = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
+  auto *C2node = dyn_cast<ConstantIntSDNode>(Shift.getOperand(1));
   if (!C2node)
     return SDValue();
 
@@ -6054,7 +6054,7 @@
 
   SmallVector<SDValue, 16> Ops;
   for (SDValue Lane : Op->ops()) {
-    if (auto *CstLane = dyn_cast<ConstantSDNode>(Lane)) {
+    if (auto *CstLane = dyn_cast<ConstantIntSDNode>(Lane)) {
       APInt LowBits(EltTy.getSizeInBits(),
                     CstLane->getZExtValue());
       Lane = DAG.getConstant(LowBits.getZExtValue(), dl, MVT::i32);
@@ -6310,10 +6310,10 @@
       continue;
     if (i > 0)
       isOnlyLowElement = false;
-    if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
+    if (!isa<ConstantFPSDNode>(V) && !isa<ConstantIntSDNode>(V))
       isConstant = false;
 
-    if (isa<ConstantSDNode>(V) || isa<ConstantFPSDNode>(V)) {
+    if (isa<ConstantIntSDNode>(V) || isa<ConstantFPSDNode>(V)) {
       ++NumConstantLanes;
       if (!ConstantValue.getNode())
         ConstantValue = V;
@@ -6379,7 +6379,7 @@
     for (unsigned i = 0; i < NumElts; ++i) {
       SDValue V = Op.getOperand(i);
       SDValue LaneIdx = DAG.getConstant(i, dl, MVT::i64);
-      if (!isa<ConstantSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
+      if (!isa<ConstantIntSDNode>(V) && !isa<ConstantFPSDNode>(V)) {
         // Note that type legalization likely mucked about with the VT of the
         // source operand, so we may have to convert it here before inserting.
         Val = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Val, V, LaneIdx);
@@ -6446,7 +6446,7 @@
 
   // Check for non-constant or out of range lane.
   EVT VT = Op.getOperand(0).getValueType();
-  ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(2));
+  auto *CI = dyn_cast<ConstantIntSDNode>(Op.getOperand(2));
   if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
     return SDValue();
 
@@ -6480,7 +6480,7 @@
 
   // Check for non-constant or out of range lane.
   EVT VT = Op.getOperand(0).getValueType();
-  ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Op.getOperand(1));
+  auto *CI = dyn_cast<ConstantIntSDNode>(Op.getOperand(1));
   if (!CI || CI->getZExtValue() >= VT.getVectorNumElements())
     return SDValue();
 
@@ -6518,7 +6518,7 @@
   if (!VT.isVector())
     return SDValue();
 
-  ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
+  auto *Cst = dyn_cast<ConstantIntSDNode>(Op.getOperand(1));
   if (!Cst)
     return SDValue();
   unsigned Val = Cst->getZExtValue();
@@ -7377,11 +7377,10 @@
     // If N is unsigned bit extraction: ((x >> C) & mask), then do not combine
     // it with shift to let it be lowered to UBFX.
   if (N->getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
-      isa<ConstantSDNode>(N->getOperand(1))) {
+      isa<ConstantIntSDNode>(N->getOperand(1))) {
     uint64_t TruncMask = N->getConstantOperandVal(1);
-    if (isMask_64(TruncMask) &&
-      N->getOperand(0).getOpcode() == ISD::SRL &&
-      isa<ConstantSDNode>(N->getOperand(0)->getOperand(1)))
+    if (isMask_64(TruncMask) && N->getOperand(0).getOpcode() == ISD::SRL &&
+        isa<ConstantIntSDNode>(N->getOperand(0)->getOperand(1)))
       return false;
   }
   return true;
@@ -7429,7 +7428,7 @@
     return SDValue();
 
   // The shift should be smearing the sign bit across each vector element.
-  auto *ShiftAmt = dyn_cast<ConstantSDNode>(Shift.getOperand(1));
+  auto *ShiftAmt = dyn_cast<ConstantIntSDNode>(Shift.getOperand(1));
   EVT ShiftEltTy = Shift.getValueType().getVectorElementType();
   if (!ShiftAmt || ShiftAmt->getZExtValue() != ShiftEltTy.getSizeInBits() - 1)
     return SDValue();
@@ -7450,7 +7449,7 @@
   if (VT.isInteger() && N->getOpcode() == ISD::XOR &&
       N0.getOpcode() == ISD::ADD && N0.getOperand(1) == N1 &&
       N1.getOpcode() == ISD::SRA && N1.getOperand(0) == N0.getOperand(0))
-    if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
+    if (auto *Y1C = dyn_cast<ConstantIntSDNode>(N1.getOperand(1)))
       if (Y1C->getAPIntValue() == VT.getSizeInBits() - 1) {
         SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT),
                                   N0.getOperand(0));
@@ -7534,7 +7533,7 @@
   // future CPUs have a cheaper MADD instruction, this may need to be
   // gated on a subtarget feature. For Cyclone, 32-bit MADD is 4 cycles and
   // 64-bit is 5 cycles, so this is always a win.
-  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
+  if (auto *C = dyn_cast<ConstantIntSDNode>(N->getOperand(1))) {
     const APInt &Value = C->getAPIntValue();
     EVT VT = N->getValueType(0);
     SDLoc DL(N);
@@ -7819,7 +7818,7 @@
   else
     return false;
 
-  if (!isa<ConstantSDNode>(N.getOperand(1)))
+  if (!isa<ConstantIntSDNode>(N.getOperand(1)))
     return false;
 
   ShiftAmount = N->getConstantOperandVal(1);
@@ -7902,8 +7901,8 @@
 
       bool FoundMatch = true;
       for (unsigned k = 0; k < VT.getVectorNumElements(); ++k) {
-        ConstantSDNode *CN0 = dyn_cast<ConstantSDNode>(BVN0->getOperand(k));
-        ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(BVN1->getOperand(k));
+        auto *CN0 = dyn_cast<ConstantIntSDNode>(BVN0->getOperand(k));
+        auto *CN1 = dyn_cast<ConstantIntSDNode>(BVN1->getOperand(k));
         if (!CN0 || !CN1 ||
             CN0->getZExtValue() != (BitMask & ~CN1->getZExtValue())) {
           FoundMatch = false;
@@ -7952,7 +7951,7 @@
     SDLoc DL(N);
     SDValue N1 = N->getOperand(1);
     SDValue N00 = N0.getOperand(0);
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(N1)) {
       uint64_t ShiftAmt = C->getZExtValue();
       if (VT == MVT::i32 && ShiftAmt == 16 &&
           DAG.MaskedValueIsZero(N00, APInt::getHighBitsSet(32, 16)))
@@ -7994,7 +7993,7 @@
       !(Op0->isMachineOpcode() &&
         Op0->getMachineOpcode() == AArch64::EXTRACT_SUBREG))
     return SDValue();
-  uint64_t idx = cast<ConstantSDNode>(Op0->getOperand(1))->getZExtValue();
+  uint64_t idx = cast<ConstantIntSDNode>(Op0->getOperand(1))->getZExtValue();
   if (Op0->getOpcode() == ISD::EXTRACT_SUBVECTOR) {
     if (Op0->getValueType(0).getVectorNumElements() != idx && idx != 0)
       return SDValue();
@@ -8270,13 +8269,13 @@
   SetCCInfo.Info.AArch64.Cmp = &Op.getOperand(3);
   SetCCInfo.IsAArch64 = true;
   SetCCInfo.Info.AArch64.CC = static_cast<AArch64CC::CondCode>(
-      cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
+      cast<ConstantIntSDNode>(Op.getOperand(2))->getZExtValue());
 
   // Check that the operands matches the constraints:
   // (1) Both operands must be constants.
   // (2) One must be 1 and the other must be 0.
-  ConstantSDNode *TValue = dyn_cast<ConstantSDNode>(Op.getOperand(0));
-  ConstantSDNode *FValue = dyn_cast<ConstantSDNode>(Op.getOperand(1));
+  auto *TValue = dyn_cast<ConstantIntSDNode>(Op.getOperand(0));
+  auto *FValue = dyn_cast<ConstantIntSDNode>(Op.getOperand(1));
 
   // Check (1).
   if (!TValue || !FValue)
@@ -8449,7 +8448,7 @@
       return SDValue();
 
     ShiftAmount = SplatValue.getSExtValue();
-  } else if (ConstantSDNode *CVN = dyn_cast<ConstantSDNode>(N->getOperand(2))) {
+  } else if (auto *CVN = dyn_cast<ConstantIntSDNode>(N->getOperand(2))) {
     ShiftAmount = CVN->getSExtValue();
   } else
     return SDValue();
@@ -8502,7 +8501,7 @@
   if (AndN.getOpcode() != ISD::AND)
     return SDValue();
 
-  ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(AndN.getOperand(1));
+  auto *CMask = dyn_cast<ConstantIntSDNode>(AndN.getOperand(1));
   if (!CMask || CMask->getZExtValue() != Mask)
     return SDValue();
 
@@ -8852,7 +8851,7 @@
 
     // If the increment is a constant, it must match the memory ref size.
     SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
-    if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
+    if (auto *CInc = dyn_cast<ConstantIntSDNode>(Inc.getNode())) {
       uint32_t IncVal = CInc->getZExtValue();
       unsigned NumBytes = VT.getScalarSizeInBits() / 8;
       if (IncVal != NumBytes)
@@ -9219,7 +9218,7 @@
     bool IsDupOp = false;
     unsigned NewOpc = 0;
     unsigned NumVecs = 0;
-    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
+    unsigned IntNo = cast<ConstantIntSDNode>(N->getOperand(1))->getZExtValue();
     switch (IntNo) {
     default: llvm_unreachable("unexpected intrinsic for Neon base update");
     case Intrinsic::aarch64_neon_ld2:       NewOpc = AArch64ISD::LD2post;
@@ -9274,7 +9273,7 @@
 
     // If the increment is a constant, it must match the memory ref size.
     SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
-    if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
+    if (auto *CInc = dyn_cast<ConstantIntSDNode>(Inc.getNode())) {
       uint32_t IncVal = CInc->getZExtValue();
       unsigned NumBytes = NumVecs * VecTy.getSizeInBits() / 8;
       if (IsLaneOp || IsDupOp)
@@ -9358,7 +9357,7 @@
   }
   case ISD::Constant:
   case ISD::TargetConstant: {
-    return std::abs(cast<ConstantSDNode>(V.getNode())->getSExtValue()) <
+    return std::abs(cast<ConstantIntSDNode>(V.getNode())->getSExtValue()) <
            1LL << (width - 1);
   }
   }
@@ -9508,7 +9507,7 @@
                            TargetLowering::DAGCombinerInfo &DCI,
                            SelectionDAG &DAG, unsigned CCIndex,
                            unsigned CmpIndex) {
-  unsigned CC = cast<ConstantSDNode>(N->getOperand(CCIndex))->getSExtValue();
+  unsigned CC = cast<ConstantIntSDNode>(N->getOperand(CCIndex))->getSExtValue();
   SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
   unsigned CondOpcode = SubsNode->getOpcode();
 
@@ -9524,7 +9523,7 @@
   if (AndNode->getOpcode() != ISD::AND)
     return SDValue();
 
-  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(AndNode->getOperand(1))) {
+  if (auto *CN = dyn_cast<ConstantIntSDNode>(AndNode->getOperand(1))) {
     uint32_t CNV = CN->getZExtValue();
     if (CNV == 255)
       MaskBits = 8;
@@ -9549,8 +9548,8 @@
   // The mask is present and the provenance of all the values is a smaller type,
   // lets see if the mask is superfluous.
 
-  if (!isa<ConstantSDNode>(AddInputValue2.getNode()) ||
-      !isa<ConstantSDNode>(SubsInputValue.getNode()))
+  if (!isa<ConstantIntSDNode>(AddInputValue2.getNode()) ||
+      !isa<ConstantIntSDNode>(SubsInputValue.getNode()))
     return SDValue();
 
   ISD::LoadExtType ExtType;
@@ -9560,9 +9559,10 @@
       !checkValueWidth(AddInputValue1, MaskBits, ExtType) )
     return SDValue();
 
-  if(!isEquivalentMaskless(CC, MaskBits, ExtType,
-                cast<ConstantSDNode>(AddInputValue2.getNode())->getSExtValue(),
-                cast<ConstantSDNode>(SubsInputValue.getNode())->getSExtValue()))
+  if (!isEquivalentMaskless(
+          CC, MaskBits, ExtType,
+          cast<ConstantIntSDNode>(AddInputValue2.getNode())->getSExtValue(),
+          cast<ConstantIntSDNode>(SubsInputValue.getNode())->getSExtValue()))
     return SDValue();
 
   // The AND is not necessary, remove it.
@@ -9588,8 +9588,8 @@
   SDValue CCVal = N->getOperand(2);
   SDValue Cmp = N->getOperand(3);
 
-  assert(isa<ConstantSDNode>(CCVal) && "Expected a ConstantSDNode here!");
-  unsigned CC = cast<ConstantSDNode>(CCVal)->getZExtValue();
+  assert(isa<ConstantIntSDNode>(CCVal) && "Expected a ConstantIntSDNode here!");
+  unsigned CC = cast<ConstantIntSDNode>(CCVal)->getZExtValue();
   if (CC != AArch64CC::EQ && CC != AArch64CC::NE)
     return SDValue();
 
@@ -9657,7 +9657,7 @@
   if (Op->getNumOperands() != 2)
     return Op;
 
-  auto *C = dyn_cast<ConstantSDNode>(Op->getOperand(1));
+  auto *C = dyn_cast<ConstantIntSDNode>(Op->getOperand(1));
   if (!C)
     return Op;
 
@@ -9707,7 +9707,7 @@
 static SDValue performTBZCombine(SDNode *N,
                                  TargetLowering::DAGCombinerInfo &DCI,
                                  SelectionDAG &DAG) {
-  unsigned Bit = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
+  unsigned Bit = cast<ConstantIntSDNode>(N->getOperand(2))->getZExtValue();
   bool Invert = false;
   SDValue TestSrc = N->getOperand(1);
   SDValue NewTestSrc = getTestBitOperand(TestSrc, Bit, Invert, DAG);
@@ -9898,7 +9898,7 @@
     return performAcrossLaneAddReductionCombine(N, DAG, Subtarget);
   case ISD::INTRINSIC_VOID:
   case ISD::INTRINSIC_W_CHAIN:
-    switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
+    switch (cast<ConstantIntSDNode>(N->getOperand(1))->getZExtValue()) {
     case Intrinsic::aarch64_neon_ld2:
     case Intrinsic::aarch64_neon_ld3:
     case Intrinsic::aarch64_neon_ld4:
@@ -9984,7 +9984,7 @@
   Base = Op->getOperand(0);
   // All of the indexed addressing mode instructions take a signed
   // 9 bit immediate offset.
-  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
+  if (auto *RHS = dyn_cast<ConstantIntSDNode>(Op->getOperand(1))) {
     int64_t RHSC = (int64_t)RHS->getZExtValue();
     if (RHSC >= 256 || RHSC <= -256)
       return false;
Index: llvm/lib/Target/AArch64/AArch64InstrFormats.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -448,11 +448,11 @@
 
 // Crazy immediate formats used by 32-bit and 64-bit logical immediate
 // instructions for splatting repeating bit patterns across the immediate.
-def logical_imm32_XFORM : SDNodeXForm<imm, [{
+def logical_imm32_XFORM : ConstIntSDNodeXForm<[{
   uint64_t enc = AArch64_AM::encodeLogicalImmediate(N->getZExtValue(), 32);
   return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
 }]>;
-def logical_imm64_XFORM : SDNodeXForm<imm, [{
+def logical_imm64_XFORM : ConstIntSDNodeXForm<[{
   uint64_t enc = AArch64_AM::encodeLogicalImmediate(N->getZExtValue(), 64);
   return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
 }]>;
@@ -2315,7 +2315,7 @@
   let Inst{4-0}   = Rd;
 }
 
-def inv_cond_XFORM : SDNodeXForm<imm, [{
+def inv_cond_XFORM : ConstIntSDNodeXForm<[{
   AArch64CC::CondCode CC = static_cast<AArch64CC::CondCode>(N->getZExtValue());
   return CurDAG->getTargetConstant(AArch64CC::getInvertedCondCode(CC), SDLoc(N),
                                    MVT::i32);
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -538,7 +538,7 @@
          Imm64 <= std::numeric_limits<int32_t>::max();
 }]>;
 
-def trunc_imm : SDNodeXForm<imm, [{
+def trunc_imm : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i32);
 }]>;
 
@@ -1003,56 +1003,56 @@
 defm UBFM : BitfieldImm<0b10, "ubfm">;
 }
 
-def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
+def i32shift_a : Operand<i64>, ConstIntSDNodeXForm<[{
   uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
   return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
 }]>;
 
-def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
+def i32shift_b : Operand<i64>, ConstIntSDNodeXForm<[{
   uint64_t enc = 31 - N->getZExtValue();
   return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
 }]>;
 
 // min(7, 31 - shift_amt)
-def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
+def i32shift_sext_i8 : Operand<i64>, ConstIntSDNodeXForm<[{
   uint64_t enc = 31 - N->getZExtValue();
   enc = enc > 7 ? 7 : enc;
   return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
 }]>;
 
 // min(15, 31 - shift_amt)
-def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
+def i32shift_sext_i16 : Operand<i64>, ConstIntSDNodeXForm<[{
   uint64_t enc = 31 - N->getZExtValue();
   enc = enc > 15 ? 15 : enc;
   return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
 }]>;
 
-def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
+def i64shift_a : Operand<i64>, ConstIntSDNodeXForm<[{
   uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
   return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
 }]>;
 
-def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
+def i64shift_b : Operand<i64>, ConstIntSDNodeXForm<[{
   uint64_t enc = 63 - N->getZExtValue();
   return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
 }]>;
 
 // min(7, 63 - shift_amt)
-def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
+def i64shift_sext_i8 : Operand<i64>, ConstIntSDNodeXForm<[{
   uint64_t enc = 63 - N->getZExtValue();
   enc = enc > 7 ? 7 : enc;
   return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
 }]>;
 
 // min(15, 63 - shift_amt)
-def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
+def i64shift_sext_i16 : Operand<i64>, ConstIntSDNodeXForm<[{
   uint64_t enc = 63 - N->getZExtValue();
   enc = enc > 15 ? 15 : enc;
   return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
 }]>;
 
 // min(31, 63 - shift_amt)
-def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
+def i64shift_sext_i32 : Operand<i64>, ConstIntSDNodeXForm<[{
   uint64_t enc = 63 - N->getZExtValue();
   enc = enc > 31 ? 31 : enc;
   return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i64);
@@ -3828,13 +3828,13 @@
 // If there's an (AArch64dup (vector_extract ...) ...), we can use a duplane
 // instruction even if the types don't match: we just have to remap the lane
 // carefully. N.b. this trick only applies to truncations.
-def VecIndex_x2 : SDNodeXForm<imm, [{
+def VecIndex_x2 : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(2 * N->getZExtValue(), SDLoc(N), MVT::i64);
 }]>;
-def VecIndex_x4 : SDNodeXForm<imm, [{
+def VecIndex_x4 : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(4 * N->getZExtValue(), SDLoc(N), MVT::i64);
 }]>;
-def VecIndex_x8 : SDNodeXForm<imm, [{
+def VecIndex_x8 : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(8 * N->getZExtValue(), SDLoc(N), MVT::i64);
 }]>;
 
Index: llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64SelectionDAGInfo.cpp
@@ -21,8 +21,8 @@
     SDValue Size, unsigned Align, bool isVolatile,
     MachinePointerInfo DstPtrInfo) const {
   // Check to see if there is a specialized entry-point for memory zeroing.
-  ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
-  ConstantSDNode *SizeValue = dyn_cast<ConstantSDNode>(Size);
+  auto *V = dyn_cast<ConstantIntSDNode>(Src);
+  auto *SizeValue = dyn_cast<ConstantIntSDNode>(Size);
   const AArch64Subtarget &STI =
       DAG.getMachineFunction().getSubtarget<AArch64Subtarget>();
   const char *bzeroEntry =
Index: llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -168,7 +168,7 @@
   const SIInstrInfo *TII
     = static_cast<const SISubtarget *>(Subtarget)->getInstrInfo();
 
-  if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(N))
+  if (const auto *C = dyn_cast<ConstantIntSDNode>(N))
     return TII->isInlineConstant(C->getAPIntValue());
 
   if (const ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N))
@@ -200,12 +200,12 @@
     return Subtarget->getRegisterInfo()->getRegClass(RegClass);
   }
   case AMDGPU::REG_SEQUENCE: {
-    unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
+    unsigned RCID = cast<ConstantIntSDNode>(N->getOperand(0))->getZExtValue();
     const TargetRegisterClass *SuperRC =
         Subtarget->getRegisterInfo()->getRegClass(RCID);
 
     SDValue SubRegOp = N->getOperand(OpNo + 1);
-    unsigned SubRegIdx = cast<ConstantSDNode>(SubRegOp)->getZExtValue();
+    unsigned SubRegIdx = cast<ConstantIntSDNode>(SubRegOp)->getZExtValue();
     return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC,
                                                               SubRegIdx);
   }
@@ -390,7 +390,7 @@
     if (ConstantFPSDNode *FP = dyn_cast<ConstantFPSDNode>(N))
       Imm = FP->getValueAPF().bitcastToAPInt().getZExtValue();
     else {
-      ConstantSDNode *C = cast<ConstantSDNode>(N);
+      auto *C = cast<ConstantIntSDNode>(N);
       Imm = C->getZExtValue();
     }
 
@@ -429,11 +429,11 @@
 
     // TODO: Technically we could try to pattern match scalar bitshifts of
     // dynamic values, but it's probably not useful.
-    ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
+    auto *Offset = dyn_cast<ConstantIntSDNode>(N->getOperand(1));
     if (!Offset)
       break;
 
-    ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
+    auto *Width = dyn_cast<ConstantIntSDNode>(N->getOperand(2));
     if (!Width)
       break;
 
@@ -504,7 +504,7 @@
 
 bool AMDGPUDAGToDAGISel::SelectGlobalValueConstantOffset(SDValue Addr,
                                                          SDValue& IntPtr) {
-  if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Addr)) {
+  if (auto *Cst = dyn_cast<ConstantIntSDNode>(Addr)) {
     IntPtr = CurDAG->getIntPtrConstant(Cst->getZExtValue() / 4, SDLoc(Addr),
                                        true);
     return true;
@@ -514,7 +514,7 @@
 
 bool AMDGPUDAGToDAGISel::SelectGlobalValueVariableOffset(SDValue Addr,
     SDValue& BaseReg, SDValue &Offset) {
-  if (!isa<ConstantSDNode>(Addr)) {
+  if (!isa<ConstantIntSDNode>(Addr)) {
     BaseReg = Addr;
     Offset = CurDAG->getIntPtrConstant(0, SDLoc(Addr), true);
     return true;
@@ -524,19 +524,19 @@
 
 bool AMDGPUDAGToDAGISel::SelectADDRVTX_READ(SDValue Addr, SDValue &Base,
                                            SDValue &Offset) {
-  ConstantSDNode *IMMOffset;
+  ConstantIntSDNode *IMMOffset;
 
-  if (Addr.getOpcode() == ISD::ADD
-      && (IMMOffset = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
-      && isInt<16>(IMMOffset->getZExtValue())) {
+  if (Addr.getOpcode() == ISD::ADD &&
+      (IMMOffset = dyn_cast<ConstantIntSDNode>(Addr.getOperand(1))) &&
+      isInt<16>(IMMOffset->getZExtValue())) {
 
-      Base = Addr.getOperand(0);
-      Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr),
-                                         MVT::i32);
-      return true;
-  // If the pointer address is constant, we can move it to the offset field.
-  } else if ((IMMOffset = dyn_cast<ConstantSDNode>(Addr))
-             && isInt<16>(IMMOffset->getZExtValue())) {
+    Base = Addr.getOperand(0);
+    Offset = CurDAG->getTargetConstant(IMMOffset->getZExtValue(), SDLoc(Addr),
+                                       MVT::i32);
+    return true;
+    // If the pointer address is constant, we can move it to the offset field.
+  } else if ((IMMOffset = dyn_cast<ConstantIntSDNode>(Addr)) &&
+             isInt<16>(IMMOffset->getZExtValue())) {
     Base = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
                                   SDLoc(CurDAG->getEntryNode()),
                                   AMDGPU::ZERO, MVT::i32);
@@ -553,14 +553,14 @@
 
 bool AMDGPUDAGToDAGISel::SelectADDRIndirect(SDValue Addr, SDValue &Base,
                                             SDValue &Offset) {
-  ConstantSDNode *C;
+  ConstantIntSDNode *C;
   SDLoc DL(Addr);
 
-  if ((C = dyn_cast<ConstantSDNode>(Addr))) {
+  if ((C = dyn_cast<ConstantIntSDNode>(Addr))) {
     Base = CurDAG->getRegister(AMDGPU::INDIRECT_BASE_ADDR, MVT::i32);
     Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
   } else if ((Addr.getOpcode() == ISD::ADD || Addr.getOpcode() == ISD::OR) &&
-            (C = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
+             (C = dyn_cast<ConstantIntSDNode>(Addr.getOperand(1)))) {
     Base = Addr.getOperand(0);
     Offset = CurDAG->getTargetConstant(C->getZExtValue(), DL, MVT::i32);
   } else {
@@ -655,7 +655,7 @@
   if (CurDAG->isBaseWithConstantOffset(Addr)) {
     SDValue N0 = Addr.getOperand(0);
     SDValue N1 = Addr.getOperand(1);
-    ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
+    auto *C1 = cast<ConstantIntSDNode>(N1);
     if (isDSOffsetLegal(N0, C1->getSExtValue(), 16)) {
       // (add n0, c0)
       Base = N0;
@@ -664,7 +664,7 @@
     }
   } else if (Addr.getOpcode() == ISD::SUB) {
     // sub C, x -> add (sub 0, x), C
-    if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Addr.getOperand(0))) {
+    if (const auto *C = dyn_cast<ConstantIntSDNode>(Addr.getOperand(0))) {
       int64_t ByteOffset = C->getSExtValue();
       if (isUInt<16>(ByteOffset)) {
         SDValue Zero = CurDAG->getTargetConstant(0, DL, MVT::i32);
@@ -686,7 +686,7 @@
         }
       }
     }
-  } else if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
+  } else if (const auto *CAddr = dyn_cast<ConstantIntSDNode>(Addr)) {
     // If we have a constant address, prefer to put the constant into the
     // offset. This can save moves to load the constant address since multiple
     // operations can share the zero base address register, and enables merging
@@ -719,7 +719,7 @@
   if (CurDAG->isBaseWithConstantOffset(Addr)) {
     SDValue N0 = Addr.getOperand(0);
     SDValue N1 = Addr.getOperand(1);
-    ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
+    auto *C1 = cast<ConstantIntSDNode>(N1);
     unsigned DWordOffset0 = C1->getZExtValue() / 4;
     unsigned DWordOffset1 = DWordOffset0 + 1;
     // (add n0, c0)
@@ -731,7 +731,7 @@
     }
   } else if (Addr.getOpcode() == ISD::SUB) {
     // sub C, x -> add (sub 0, x), C
-    if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Addr.getOperand(0))) {
+    if (const auto *C = dyn_cast<ConstantIntSDNode>(Addr.getOperand(0))) {
       unsigned DWordOffset0 = C->getZExtValue() / 4;
       unsigned DWordOffset1 = DWordOffset0 + 1;
 
@@ -757,7 +757,7 @@
         }
       }
     }
-  } else if (const ConstantSDNode *CAddr = dyn_cast<ConstantSDNode>(Addr)) {
+  } else if (const auto *CAddr = dyn_cast<ConstantIntSDNode>(Addr)) {
     unsigned DWordOffset0 = CAddr->getZExtValue() / 4;
     unsigned DWordOffset1 = DWordOffset0 + 1;
     assert(4 * DWordOffset0 == CAddr->getZExtValue());
@@ -784,7 +784,7 @@
   return true;
 }
 
-static bool isLegalMUBUFImmOffset(const ConstantSDNode *Imm) {
+static bool isLegalMUBUFImmOffset(const ConstantIntSDNode *Imm) {
   return isUInt<12>(Imm->getZExtValue());
 }
 
@@ -814,7 +814,7 @@
   if (CurDAG->isBaseWithConstantOffset(Addr)) {
     SDValue N0 = Addr.getOperand(0);
     SDValue N1 = Addr.getOperand(1);
-    ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
+    auto *C1 = cast<ConstantIntSDNode>(N1);
 
     if (N0.getOpcode() == ISD::ADD) {
       // (add (add N2, N3), C1) -> addr64
@@ -878,7 +878,7 @@
               GLC, SLC, TFE))
     return false;
 
-  ConstantSDNode *C = cast<ConstantSDNode>(Addr64);
+  auto *C = cast<ConstantIntSDNode>(Addr64);
   if (C->getSExtValue()) {
     SDLoc DL(Addr);
 
@@ -925,7 +925,7 @@
     SDValue N1 = Addr.getOperand(1);
 
     // Offsets in vaddr must be positive.
-    ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
+    auto *C1 = cast<ConstantIntSDNode>(N1);
     if (isLegalMUBUFImmOffset(C1)) {
       VAddr = foldFrameIndex(N0);
       ImmOffset = CurDAG->getTargetConstant(C1->getZExtValue(), DL, MVT::i16);
@@ -951,9 +951,9 @@
               GLC, SLC, TFE))
     return false;
 
-  if (!cast<ConstantSDNode>(Offen)->getSExtValue() &&
-      !cast<ConstantSDNode>(Idxen)->getSExtValue() &&
-      !cast<ConstantSDNode>(Addr64)->getSExtValue()) {
+  if (!cast<ConstantIntSDNode>(Offen)->getSExtValue() &&
+      !cast<ConstantIntSDNode>(Idxen)->getSExtValue() &&
+      !cast<ConstantIntSDNode>(Addr64)->getSExtValue()) {
     uint64_t Rsrc = TII->getDefaultRsrcDataFormat() |
                     APInt::getAllOnesValue(32).getZExtValue(); // Size
     SDLoc DL(Addr);
@@ -986,7 +986,7 @@
                                              SDValue &SOffset,
                                              SDValue &ImmOffset) const {
   SDLoc DL(Constant);
-  uint32_t Imm = cast<ConstantSDNode>(Constant)->getZExtValue();
+  uint32_t Imm = cast<ConstantIntSDNode>(Constant)->getZExtValue();
   uint32_t Overflow = 0;
 
   if (Imm >= 4096) {
@@ -1031,7 +1031,7 @@
                                                     SDValue &ImmOffset) const {
   SDLoc DL(Offset);
 
-  if (!isa<ConstantSDNode>(Offset))
+  if (!isa<ConstantIntSDNode>(Offset))
     return false;
 
   return SelectMUBUFConstant(Offset, SOffset, ImmOffset);
@@ -1044,7 +1044,7 @@
   SDLoc DL(Offset);
 
   // Don't generate an unnecessary voffset for constant offsets.
-  if (isa<ConstantSDNode>(Offset)) {
+  if (isa<ConstantIntSDNode>(Offset)) {
     SDValue Tmp1, Tmp2;
 
     // When necessary, use a voffset in <= CI anyway to work around a hardware
@@ -1057,7 +1057,7 @@
   if (CurDAG->isBaseWithConstantOffset(Offset)) {
     SDValue N0 = Offset.getOperand(0);
     SDValue N1 = Offset.getOperand(1);
-    if (cast<ConstantSDNode>(N1)->getSExtValue() >= 0 &&
+    if (cast<ConstantIntSDNode>(N1)->getSExtValue() >= 0 &&
         SelectMUBUFConstant(N1, SOffset, ImmOffset)) {
       VOffset = N0;
       return true;
@@ -1094,7 +1094,7 @@
                                           SDValue &Offset, bool &Imm) const {
 
   // FIXME: Handle non-constant offsets.
-  ConstantSDNode *C = dyn_cast<ConstantSDNode>(ByteOffsetNode);
+  auto *C = dyn_cast<ConstantIntSDNode>(ByteOffsetNode);
   if (!C)
     return false;
 
@@ -1160,14 +1160,14 @@
   if (!SelectSMRD(Addr, SBase, Offset, Imm))
     return false;
 
-  return !Imm && isa<ConstantSDNode>(Offset);
+  return !Imm && isa<ConstantIntSDNode>(Offset);
 }
 
 bool AMDGPUDAGToDAGISel::SelectSMRDSgpr(SDValue Addr, SDValue &SBase,
                                         SDValue &Offset) const {
   bool Imm;
   return SelectSMRD(Addr, SBase, Offset, Imm) && !Imm &&
-         !isa<ConstantSDNode>(Offset);
+         !isa<ConstantIntSDNode>(Offset);
 }
 
 bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm(SDValue Addr,
@@ -1185,14 +1185,14 @@
   if (!SelectSMRDOffset(Addr, Offset, Imm))
     return false;
 
-  return !Imm && isa<ConstantSDNode>(Offset);
+  return !Imm && isa<ConstantIntSDNode>(Offset);
 }
 
 bool AMDGPUDAGToDAGISel::SelectSMRDBufferSgpr(SDValue Addr,
                                               SDValue &Offset) const {
   bool Imm;
   return SelectSMRDOffset(Addr, Offset, Imm) && !Imm &&
-         !isa<ConstantSDNode>(Offset);
+         !isa<ConstantIntSDNode>(Offset);
 }
 
 bool AMDGPUDAGToDAGISel::SelectMOVRELOffset(SDValue Index,
@@ -1203,7 +1203,7 @@
   if (CurDAG->isBaseWithConstantOffset(Index)) {
     SDValue N0 = Index.getOperand(0);
     SDValue N1 = Index.getOperand(1);
-    ConstantSDNode *C1 = cast<ConstantSDNode>(N1);
+    auto *C1 = cast<ConstantIntSDNode>(N1);
 
     // (add n0, c0)
     Base = N0;
@@ -1211,7 +1211,7 @@
     return true;
   }
 
-  if (isa<ConstantSDNode>(Index))
+  if (isa<ConstantIntSDNode>(Index))
     return false;
 
   Base = Index;
@@ -1237,8 +1237,8 @@
   // Predicate: 0 < b <= c < 32
 
   const SDValue &Shl = N->getOperand(0);
-  ConstantSDNode *B = dyn_cast<ConstantSDNode>(Shl->getOperand(1));
-  ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
+  auto *B = dyn_cast<ConstantIntSDNode>(Shl->getOperand(1));
+  auto *C = dyn_cast<ConstantIntSDNode>(N->getOperand(1));
 
   if (B && C) {
     uint32_t BVal = B->getZExtValue();
@@ -1263,8 +1263,8 @@
       // "(a srl b) & mask" ---> "BFE_U32 a, b, popcount(mask)"
       // Predicate: isMask(mask)
       const SDValue &Srl = N->getOperand(0);
-      ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(Srl.getOperand(1));
-      ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(N->getOperand(1));
+      auto *Shift = dyn_cast<ConstantIntSDNode>(Srl.getOperand(1));
+      auto *Mask = dyn_cast<ConstantIntSDNode>(N->getOperand(1));
 
       if (Shift && Mask) {
         uint32_t ShiftVal = Shift->getZExtValue();
@@ -1285,8 +1285,8 @@
       // "(a & mask) srl b)" ---> "BFE_U32 a, b, popcount(mask >> b)"
       // Predicate: isMask(mask >> b)
       const SDValue &And = N->getOperand(0);
-      ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(N->getOperand(1));
-      ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(And->getOperand(1));
+      auto *Shift = dyn_cast<ConstantIntSDNode>(N->getOperand(1));
+      auto *Mask = dyn_cast<ConstantIntSDNode>(And->getOperand(1));
 
       if (Shift && Mask) {
         uint32_t ShiftVal = Shift->getZExtValue();
@@ -1318,7 +1318,7 @@
     if (Src.getOpcode() != ISD::SRL)
       break;
 
-    const ConstantSDNode *Amt = dyn_cast<ConstantSDNode>(Src.getOperand(1));
+    const auto *Amt = dyn_cast<ConstantIntSDNode>(Src.getOperand(1));
     if (!Amt)
       break;
 
@@ -1481,7 +1481,7 @@
 bool AMDGPUDAGToDAGISel::SelectVOP3NoMods(SDValue In, SDValue &Src,
                                          SDValue &SrcMods) const {
   bool Res = SelectVOP3Mods(In, Src, SrcMods);
-  return Res && cast<ConstantSDNode>(SrcMods)->isNullValue();
+  return Res && cast<ConstantIntSDNode>(SrcMods)->isNullValue();
 }
 
 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0(SDValue In, SDValue &Src,
@@ -1500,9 +1500,9 @@
                                            SDValue &Omod) const {
   bool Res = SelectVOP3Mods0(In, Src, SrcMods, Clamp, Omod);
 
-  return Res && cast<ConstantSDNode>(SrcMods)->isNullValue() &&
-                cast<ConstantSDNode>(Clamp)->isNullValue() &&
-                cast<ConstantSDNode>(Omod)->isNullValue();
+  return Res && cast<ConstantIntSDNode>(SrcMods)->isNullValue() &&
+         cast<ConstantIntSDNode>(Clamp)->isNullValue() &&
+         cast<ConstantIntSDNode>(Omod)->isNullValue();
 }
 
 bool AMDGPUDAGToDAGISel::SelectVOP3Mods0Clamp(SDValue In, SDValue &Src,
Index: llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
+++ llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
@@ -883,7 +883,7 @@
                                                      SelectionDAG &DAG) const {
 
   SmallVector<SDValue, 8> Args;
-  unsigned Start = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
+  unsigned Start = cast<ConstantIntSDNode>(Op.getOperand(1))->getZExtValue();
   EVT VT = Op.getValueType();
   DAG.ExtractVectorElements(Op.getOperand(0), Args, Start,
                             VT.getVectorNumElements());
@@ -893,7 +893,8 @@
 
 SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
     SelectionDAG &DAG) const {
-  unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned IntrinsicID =
+      cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
   SDLoc DL(Op);
   EVT VT = Op.getValueType();
 
@@ -2222,7 +2223,7 @@
   // On some subtargets, 64-bit shift is a quarter rate instruction. In the
   // common case, splitting this into a move and a 32-bit shift is faster and
   // the same code size.
-  const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
+  const auto *RHS = dyn_cast<ConstantIntSDNode>(N->getOperand(1));
   if (!RHS)
     return SDValue();
 
@@ -2251,7 +2252,7 @@
   if (N->getValueType(0) != MVT::i64)
     return SDValue();
 
-  const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
+  const auto *RHS = dyn_cast<ConstantIntSDNode>(N->getOperand(1));
   if (!RHS)
     return SDValue();
 
@@ -2286,7 +2287,7 @@
   if (N->getValueType(0) != MVT::i64)
     return SDValue();
 
-  const ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
+  const auto *RHS = dyn_cast<ConstantIntSDNode>(N->getOperand(1));
   if (!RHS)
     return SDValue();
 
@@ -2444,7 +2445,7 @@
 }
 
 static bool isNegativeOne(SDValue Val) {
-  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val))
+  if (auto *C = dyn_cast<ConstantIntSDNode>(Val))
     return C->isAllOnesValue();
   return false;
 }
@@ -2484,7 +2485,7 @@
 SDValue AMDGPUTargetLowering::performCtlzCombine(const SDLoc &SL, SDValue Cond,
                                                  SDValue LHS, SDValue RHS,
                                                  DAGCombinerInfo &DCI) const {
-  ConstantSDNode *CmpRhs = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
+  auto *CmpRhs = dyn_cast<ConstantIntSDNode>(Cond.getOperand(1));
   if (!CmpRhs || !CmpRhs->isNullValue())
     return SDValue();
 
@@ -2582,7 +2583,7 @@
     // v2i32 (bitcast i64:k) -> build_vector lo_32(k), hi_32(k)
     // TODO: Generalize and move to DAGCombiner
     SDValue Src = N->getOperand(0);
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Src)) {
       assert(Src.getValueType() == MVT::i64);
       SDLoc SL(N);
       uint64_t CVal = C->getZExtValue();
@@ -2647,7 +2648,7 @@
   case AMDGPUISD::BFE_U32: {
     assert(!N->getValueType(0).isVector() &&
            "Vector handling of BFE not implemented");
-    ConstantSDNode *Width = dyn_cast<ConstantSDNode>(N->getOperand(2));
+    auto *Width = dyn_cast<ConstantIntSDNode>(N->getOperand(2));
     if (!Width)
       break;
 
@@ -2655,7 +2656,7 @@
     if (WidthVal == 0)
       return DAG.getConstant(0, DL, MVT::i32);
 
-    ConstantSDNode *Offset = dyn_cast<ConstantSDNode>(N->getOperand(1));
+    auto *Offset = dyn_cast<ConstantIntSDNode>(N->getOperand(1));
     if (!Offset)
       break;
 
@@ -2687,7 +2688,7 @@
       return DAG.getZeroExtendInReg(BitsFrom, DL, SmallVT);
     }
 
-    if (ConstantSDNode *CVal = dyn_cast<ConstantSDNode>(BitsFrom)) {
+    if (auto *CVal = dyn_cast<ConstantIntSDNode>(BitsFrom)) {
       if (Signed) {
         return constantFoldBFE<int32_t>(DAG,
                                         CVal->getSExtValue(),
@@ -2925,7 +2926,7 @@
 
   case AMDGPUISD::BFE_I32:
   case AMDGPUISD::BFE_U32: {
-    ConstantSDNode *CWidth = dyn_cast<ConstantSDNode>(Op.getOperand(2));
+    auto *CWidth = dyn_cast<ConstantIntSDNode>(Op.getOperand(2));
     if (!CWidth)
       return;
 
@@ -2946,7 +2947,7 @@
   unsigned Depth) const {
   switch (Op.getOpcode()) {
   case AMDGPUISD::BFE_I32: {
-    ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
+    auto *Width = dyn_cast<ConstantIntSDNode>(Op.getOperand(2));
     if (!Width)
       return 1;
 
@@ -2960,7 +2961,7 @@
   }
 
   case AMDGPUISD::BFE_U32: {
-    ConstantSDNode *Width = dyn_cast<ConstantSDNode>(Op.getOperand(2));
+    auto *Width = dyn_cast<ConstantIntSDNode>(Op.getOperand(2));
     return Width ? 32 - (Width->getZExtValue() & 0x1f) : 1;
   }
 
Index: llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -556,7 +556,7 @@
   return isMask_32(Imm);
 }]>;
 
-def IMMPopCount : SDNodeXForm<imm, [{
+def IMMPopCount : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(countPopulation(N->getZExtValue()), SDLoc(N),
                                    MVT::i32);
 }]>;
Index: llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
+++ llvm/lib/Target/AMDGPU/R600ISelLowering.cpp
@@ -429,7 +429,7 @@
   case ISD::INTRINSIC_VOID: {
     SDValue Chain = Op.getOperand(0);
     unsigned IntrinsicID =
-                         cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
+        cast<ConstantIntSDNode>(Op.getOperand(1))->getZExtValue();
     switch (IntrinsicID) {
     case AMDGPUIntrinsic::r600_store_swizzle: {
       SDLoc DL(Op);
@@ -454,7 +454,7 @@
   }
   case ISD::INTRINSIC_WO_CHAIN: {
     unsigned IntrinsicID =
-                         cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+        cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
     EVT VT = Op.getValueType();
     SDLoc DL(Op);
     switch(IntrinsicID) {
@@ -642,7 +642,7 @@
   SDValue Vector = Op.getOperand(0);
   SDValue Index = Op.getOperand(1);
 
-  if (isa<ConstantSDNode>(Index) ||
+  if (isa<ConstantIntSDNode>(Index) ||
       Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
     return Op;
 
@@ -658,7 +658,7 @@
   SDValue Value = Op.getOperand(1);
   SDValue Index = Op.getOperand(2);
 
-  if (isa<ConstantSDNode>(Index) ||
+  if (isa<ConstantIntSDNode>(Index) ||
       Vector.getOpcode() == AMDGPUISD::BUILD_VERTICAL_VECTOR)
     return Op;
 
@@ -846,7 +846,7 @@
 }
 
 bool R600TargetLowering::isZero(SDValue Op) const {
-  if(ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
+  if (auto *Cst = dyn_cast<ConstantIntSDNode>(Op)) {
     return Cst->isNullValue();
   } else if(ConstantFPSDNode *CstFP = dyn_cast<ConstantFPSDNode>(Op)){
     return CstFP->isZero();
@@ -1363,7 +1363,7 @@
     SDValue Result;
     if (isa<ConstantExpr>(LoadNode->getMemOperand()->getValue()) ||
         isa<Constant>(LoadNode->getMemOperand()->getValue()) ||
-        isa<ConstantSDNode>(Ptr)) {
+        isa<ConstantIntSDNode>(Ptr)) {
       SDValue Slots[4];
       for (unsigned i = 0; i < 4; i++) {
         // We want Const position encoded with the following formula :
@@ -1661,8 +1661,8 @@
   for (unsigned i = 0; i < 4; i++) {
     RemapSwizzle[i] = i;
     if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
-      unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
-          ->getZExtValue();
+      unsigned Idx = dyn_cast<ConstantIntSDNode>(NewBldVec[i].getOperand(1))
+                         ->getZExtValue();
       if (i == Idx)
         isUnmovable[Idx] = true;
     }
@@ -1670,8 +1670,8 @@
 
   for (unsigned i = 0; i < 4; i++) {
     if (NewBldVec[i].getOpcode() == ISD::EXTRACT_VECTOR_ELT) {
-      unsigned Idx = dyn_cast<ConstantSDNode>(NewBldVec[i].getOperand(1))
-          ->getZExtValue();
+      unsigned Idx = dyn_cast<ConstantIntSDNode>(NewBldVec[i].getOperand(1))
+                         ->getZExtValue();
       if (isUnmovable[Idx])
         continue;
       // Swap i and Idx
@@ -1694,7 +1694,7 @@
 
   BuildVector = CompactSwizzlableVector(DAG, BuildVector, SwizzleRemap);
   for (unsigned i = 0; i < 4; i++) {
-    unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue();
+    unsigned Idx = cast<ConstantIntSDNode>(Swz[i])->getZExtValue();
     if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
       Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32);
   }
@@ -1702,7 +1702,7 @@
   SwizzleRemap.clear();
   BuildVector = ReorganizeVector(DAG, BuildVector, SwizzleRemap);
   for (unsigned i = 0; i < 4; i++) {
-    unsigned Idx = cast<ConstantSDNode>(Swz[i])->getZExtValue();
+    unsigned Idx = cast<ConstantIntSDNode>(Swz[i])->getZExtValue();
     if (SwizzleRemap.find(Idx) != SwizzleRemap.end())
       Swz[i] = DAG.getConstant(SwizzleRemap[Idx], DL, MVT::i32);
   }
@@ -1778,9 +1778,9 @@
       return SDValue();
 
     // Check that we know which element is being inserted
-    if (!isa<ConstantSDNode>(EltNo))
+    if (!isa<ConstantIntSDNode>(EltNo))
       return SDValue();
-    unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
+    unsigned Elt = cast<ConstantIntSDNode>(EltNo)->getZExtValue();
 
     // Check that the operand is a BUILD_VECTOR (or UNDEF, which can essentially
     // be converted to a BUILD_VECTOR).  Fill in the Ops vector with the
@@ -1817,7 +1817,7 @@
   case ISD::EXTRACT_VECTOR_ELT: {
     SDValue Arg = N->getOperand(0);
     if (Arg.getOpcode() == ISD::BUILD_VECTOR) {
-      if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
+      if (auto *Const = dyn_cast<ConstantIntSDNode>(N->getOperand(1))) {
         unsigned Element = Const->getZExtValue();
         return Arg->getOperand(Element);
       }
@@ -1826,7 +1826,7 @@
         Arg.getOperand(0).getOpcode() == ISD::BUILD_VECTOR &&
         (Arg.getOperand(0).getValueType().getVectorNumElements() ==
          Arg.getValueType().getVectorNumElements())) {
-      if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
+      if (auto *Const = dyn_cast<ConstantIntSDNode>(N->getOperand(1))) {
         unsigned Element = Const->getZExtValue();
         return DAG.getNode(ISD::BITCAST, DL, N->getVTList(),
                            Arg->getOperand(0).getOperand(Element));
@@ -1993,14 +1993,14 @@
       if (RegisterSDNode *Reg =
           dyn_cast<RegisterSDNode>(ParentNode->getOperand(OtherSrcIdx))) {
         if (Reg->getReg() == AMDGPU::ALU_CONST) {
-          ConstantSDNode *Cst
-            = cast<ConstantSDNode>(ParentNode->getOperand(OtherSelIdx));
+          auto *Cst =
+              cast<ConstantIntSDNode>(ParentNode->getOperand(OtherSelIdx));
           Consts.push_back(Cst->getZExtValue());
         }
       }
     }
 
-    ConstantSDNode *Cst = cast<ConstantSDNode>(CstOffset);
+    auto *Cst = cast<ConstantIntSDNode>(CstOffset);
     Consts.push_back(Cst->getZExtValue());
     if (!TII->fitsConstReadLimitations(Consts)) {
       return false;
@@ -2012,7 +2012,7 @@
   }
   case AMDGPU::MOV_IMM_GLOBAL_ADDR:
     // Check if the Imm slot is used. Taken from below.
-    if (cast<ConstantSDNode>(Imm)->getZExtValue())
+    if (cast<ConstantIntSDNode>(Imm)->getZExtValue())
       return false;
     Imm = Src.getOperand(0);
     Src = DAG.getRegister(AMDGPU::ALU_LITERAL_X, MVT::i32);
@@ -2036,7 +2036,7 @@
         ImmValue = FPC->getValueAPF().bitcastToAPInt().getZExtValue();
       }
     } else {
-      ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src.getOperand(0));
+      auto *C = dyn_cast<ConstantIntSDNode>(Src.getOperand(0));
       uint64_t Value = C->getZExtValue();
       if (Value == 0) {
         ImmReg = AMDGPU::ZERO;
@@ -2053,7 +2053,7 @@
     if (ImmReg == AMDGPU::ALU_LITERAL_X) {
       if (!Imm.getNode())
         return false;
-      ConstantSDNode *C = dyn_cast<ConstantSDNode>(Imm);
+      auto *C = dyn_cast<ConstantIntSDNode>(Imm);
       assert(C);
       if (C->getZExtValue())
         return false;
Index: llvm/lib/Target/AMDGPU/SIISelLowering.h
===================================================================
--- llvm/lib/Target/AMDGPU/SIISelLowering.h
+++ llvm/lib/Target/AMDGPU/SIISelLowering.h
@@ -60,7 +60,7 @@
 
   SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL,
                                    unsigned Opc, SDValue LHS,
-                                   const ConstantSDNode *CRHS) const;
+                                   const ConstantIntSDNode *CRHS) const;
 
   SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
   SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
Index: llvm/lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -1615,7 +1615,7 @@
 
 bool SITargetLowering::isCFIntrinsic(const SDNode *Intr) const {
   if (Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
-    switch (cast<ConstantSDNode>(Intr->getOperand(1))->getZExtValue()) {
+    switch (cast<ConstantIntSDNode>(Intr->getOperand(1))->getZExtValue()) {
     case AMDGPUIntrinsic::amdgcn_if:
     case AMDGPUIntrinsic::amdgcn_else:
     case AMDGPUIntrinsic::amdgcn_end_cf:
@@ -1627,7 +1627,7 @@
   }
 
   if (Intr->getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
-    switch (cast<ConstantSDNode>(Intr->getOperand(0))->getZExtValue()) {
+    switch (cast<ConstantIntSDNode>(Intr->getOperand(0))->getZExtValue()) {
     case AMDGPUIntrinsic::amdgcn_break:
     case AMDGPUIntrinsic::amdgcn_if_break:
     case AMDGPUIntrinsic::amdgcn_else_break:
@@ -1988,7 +1988,8 @@
 
   EVT VT = Op.getValueType();
   SDLoc DL(Op);
-  unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned IntrinsicID =
+      cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
 
   // TODO: Should this propagate fast-math-flags?
 
@@ -2231,7 +2232,7 @@
                        Op.getOperand(1), Op.getOperand(2));
   case Intrinsic::amdgcn_div_scale: {
     // 3rd parameter required to be a constant.
-    const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
+    const auto *Param = dyn_cast<ConstantIntSDNode>(Op.getOperand(3));
     if (!Param)
       return DAG.getUNDEF(VT);
 
@@ -2251,7 +2252,7 @@
                        Denominator, Numerator);
   }
   case Intrinsic::amdgcn_icmp: {
-    const auto *CD = dyn_cast<ConstantSDNode>(Op.getOperand(3));
+    const auto *CD = dyn_cast<ConstantIntSDNode>(Op.getOperand(3));
     int CondCode = CD->getSExtValue();
 
     if (CondCode < ICmpInst::Predicate::FIRST_ICMP_PREDICATE ||
@@ -2264,7 +2265,7 @@
                        Op.getOperand(2), DAG.getCondCode(CCOpcode));
   }
   case Intrinsic::amdgcn_fcmp: {
-    const auto *CD = dyn_cast<ConstantSDNode>(Op.getOperand(3));
+    const auto *CD = dyn_cast<ConstantIntSDNode>(Op.getOperand(3));
     int CondCode = CD->getSExtValue();
 
     if (CondCode <= FCmpInst::Predicate::FCMP_FALSE ||
@@ -2289,7 +2290,7 @@
 
 SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
                                                  SelectionDAG &DAG) const {
-  unsigned IntrID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
+  unsigned IntrID = cast<ConstantIntSDNode>(Op.getOperand(1))->getZExtValue();
   switch (IntrID) {
   case Intrinsic::amdgcn_atomic_inc:
   case Intrinsic::amdgcn_atomic_dec: {
@@ -2315,7 +2316,8 @@
   MachineFunction &MF = DAG.getMachineFunction();
   SDLoc DL(Op);
   SDValue Chain = Op.getOperand(0);
-  unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
+  unsigned IntrinsicID =
+      cast<ConstantIntSDNode>(Op.getOperand(1))->getZExtValue();
 
   switch (IntrinsicID) {
   case AMDGPUIntrinsic::SI_sendmsg: {
@@ -2877,11 +2879,11 @@
   if (N0.getOpcode() != ISD::ADD)
     return SDValue();
 
-  const ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(N1);
+  const auto *CN1 = dyn_cast<ConstantIntSDNode>(N1);
   if (!CN1)
     return SDValue();
 
-  const ConstantSDNode *CAdd = dyn_cast<ConstantSDNode>(N0.getOperand(1));
+  const auto *CAdd = dyn_cast<ConstantIntSDNode>(N0.getOperand(1));
   if (!CAdd)
     return SDValue();
 
@@ -2913,10 +2915,8 @@
 // this way.  TODO: We won't want this for SALU especially if it is an inline
 // immediate.
 SDValue SITargetLowering::splitBinaryBitConstantOp(
-  DAGCombinerInfo &DCI,
-  const SDLoc &SL,
-  unsigned Opc, SDValue LHS,
-  const ConstantSDNode *CRHS) const {
+    DAGCombinerInfo &DCI, const SDLoc &SL, unsigned Opc, SDValue LHS,
+    const ConstantIntSDNode *CRHS) const {
   uint64_t Val = CRHS->getZExtValue();
   uint32_t ValLo = Lo_32(Val);
   uint32_t ValHi = Hi_32(Val);
@@ -2946,7 +2946,7 @@
 
 
   if (VT == MVT::i64) {
-    const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS);
+    const auto *CRHS = dyn_cast<ConstantIntSDNode>(RHS);
     if (CRHS) {
       if (SDValue Split
           = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::AND, LHS, CRHS))
@@ -3012,8 +3012,8 @@
       if (Src != RHS.getOperand(0))
         return SDValue();
 
-      const ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(LHS.getOperand(1));
-      const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS.getOperand(1));
+      const auto *CLHS = dyn_cast<ConstantIntSDNode>(LHS.getOperand(1));
+      const auto *CRHS = dyn_cast<ConstantIntSDNode>(RHS.getOperand(1));
       if (!CLHS || !CRHS)
         return SDValue();
 
@@ -3059,7 +3059,7 @@
     }
   }
 
-  const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
+  const auto *CRHS = dyn_cast<ConstantIntSDNode>(N->getOperand(1));
   if (CRHS) {
     if (SDValue Split
           = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::OR, LHS, CRHS))
@@ -3078,7 +3078,7 @@
   SDValue LHS = N->getOperand(0);
   SDValue RHS = N->getOperand(1);
 
-  const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS);
+  const auto *CRHS = dyn_cast<ConstantIntSDNode>(RHS);
   if (CRHS) {
     if (SDValue Split
           = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::XOR, LHS, CRHS))
@@ -3094,7 +3094,7 @@
   SDValue Mask = N->getOperand(1);
 
   // fp_class x, 0 -> false
-  if (const ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(Mask)) {
+  if (const auto *CMask = dyn_cast<ConstantIntSDNode>(Mask)) {
     if (CMask->isNullValue())
       return DAG.getConstant(0, SDLoc(N), MVT::i1);
   }
@@ -3166,11 +3166,11 @@
 
 static SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
                                         SDValue Op0, SDValue Op1, bool Signed) {
-  ConstantSDNode *K1 = dyn_cast<ConstantSDNode>(Op1);
+  auto *K1 = dyn_cast<ConstantIntSDNode>(Op1);
   if (!K1)
     return SDValue();
 
-  ConstantSDNode *K0 = dyn_cast<ConstantSDNode>(Op0.getOperand(1));
+  auto *K0 = dyn_cast<ConstantIntSDNode>(Op0.getOperand(1));
   if (!K0)
     return SDValue();
 
@@ -3350,7 +3350,7 @@
       // cvt_f32_ubyte1 (srl x, 16) -> cvt_f32_ubyte3 x
       // cvt_f32_ubyte0 (srl x, 8) -> cvt_f32_ubyte1 x
 
-      if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src.getOperand(1))) {
+      if (const auto *C = dyn_cast<ConstantIntSDNode>(Src.getOperand(1))) {
         unsigned SrcOffset = C->getZExtValue() + 8 * Offset;
         if (SrcOffset < 32 && SrcOffset % 8 == 0) {
           return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0 + SrcOffset / 8, DL,
Index: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -131,8 +131,8 @@
         AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::data1) != -1)
       return false;
 
-    Offset0 = cast<ConstantSDNode>(Load0->getOperand(2))->getZExtValue();
-    Offset1 = cast<ConstantSDNode>(Load1->getOperand(2))->getZExtValue();
+    Offset0 = cast<ConstantIntSDNode>(Load0->getOperand(2))->getZExtValue();
+    Offset1 = cast<ConstantIntSDNode>(Load1->getOperand(2))->getZExtValue();
     return true;
   }
 
@@ -143,10 +143,8 @@
     if (Load0->getOperand(0) != Load1->getOperand(0))
       return false;
 
-    const ConstantSDNode *Load0Offset =
-        dyn_cast<ConstantSDNode>(Load0->getOperand(1));
-    const ConstantSDNode *Load1Offset =
-        dyn_cast<ConstantSDNode>(Load1->getOperand(1));
+    const auto *Load0Offset = dyn_cast<ConstantIntSDNode>(Load0->getOperand(1));
+    const auto *Load1Offset = dyn_cast<ConstantIntSDNode>(Load1->getOperand(1));
 
     if (!Load0Offset || !Load1Offset)
       return false;
@@ -186,11 +184,11 @@
     SDValue Off1 = Load1->getOperand(OffIdx1);
 
     // The offset might be a FrameIndexSDNode.
-    if (!isa<ConstantSDNode>(Off0) || !isa<ConstantSDNode>(Off1))
+    if (!isa<ConstantIntSDNode>(Off0) || !isa<ConstantIntSDNode>(Off1))
       return false;
 
-    Offset0 = cast<ConstantSDNode>(Off0)->getZExtValue();
-    Offset1 = cast<ConstantSDNode>(Off1)->getZExtValue();
+    Offset0 = cast<ConstantIntSDNode>(Off0)->getZExtValue();
+    Offset1 = cast<ConstantIntSDNode>(Off1)->getZExtValue();
     return true;
   }
 
Index: llvm/lib/Target/AMDGPU/SIInstrInfo.td
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.td
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.td
@@ -212,23 +212,23 @@
 
 defm si_atomic_cmp_swap : AtomicCmpSwapLocal <si_atomic_cmp_swap_glue>;
 
-def as_i1imm : SDNodeXForm<imm, [{
+def as_i1imm : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i1);
 }]>;
 
-def as_i8imm : SDNodeXForm<imm, [{
+def as_i8imm : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i8);
 }]>;
 
-def as_i16imm : SDNodeXForm<imm, [{
+def as_i16imm : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
 }]>;
 
-def as_i32imm: SDNodeXForm<imm, [{
+def as_i32imm: ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
 }]>;
 
-def as_i64imm: SDNodeXForm<imm, [{
+def as_i64imm: ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
 }]>;
 
Index: llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -1610,10 +1610,10 @@
     return false;
 
   // Determine the offsets.
-  if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
-      isa<ConstantSDNode>(Load2->getOperand(1))) {
-    Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
-    Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
+  if (isa<ConstantIntSDNode>(Load1->getOperand(1)) &&
+      isa<ConstantIntSDNode>(Load2->getOperand(1))) {
+    Offset1 = cast<ConstantIntSDNode>(Load1->getOperand(1))->getSExtValue();
+    Offset2 = cast<ConstantIntSDNode>(Load2->getOperand(1))->getSExtValue();
     return true;
   }
 
@@ -3833,7 +3833,7 @@
     case ARM::LDRrs:
     case ARM::LDRBrs: {
       unsigned ShOpVal =
-        cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
+          cast<ConstantIntSDNode>(DefNode->getOperand(2))->getZExtValue();
       unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
       if (ShImm == 0 ||
           (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
@@ -3846,7 +3846,7 @@
     case ARM::t2LDRSHs: {
       // Thumb2 mode: lsl only.
       unsigned ShAmt =
-        cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
+          cast<ConstantIntSDNode>(DefNode->getOperand(2))->getZExtValue();
       if (ShAmt == 0 || ShAmt == 2)
         --Latency;
       break;
@@ -3860,7 +3860,7 @@
     case ARM::LDRrs:
     case ARM::LDRBrs: {
       unsigned ShOpVal =
-        cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
+          cast<ConstantIntSDNode>(DefNode->getOperand(2))->getZExtValue();
       unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
       if (ShImm == 0 ||
           ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
Index: llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -125,7 +125,7 @@
   }
 
   bool SelectCMOVPred(SDValue N, SDValue &Pred, SDValue &Reg) {
-    const ConstantSDNode *CN = cast<ConstantSDNode>(N);
+    const auto *CN = cast<ConstantIntSDNode>(N);
     Pred = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(N), MVT::i32);
     Reg = CurDAG->getRegister(ARM::CPSR, MVT::i32);
     return true;
@@ -291,7 +291,7 @@
 /// operand. If so Imm will receive the 32-bit value.
 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
   if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
-    Imm = cast<ConstantSDNode>(N)->getZExtValue();
+    Imm = cast<ConstantIntSDNode>(N)->getZExtValue();
     return true;
   }
   return false;
@@ -321,7 +321,7 @@
   assert(Scale > 0 && "Invalid scale!");
 
   // Check that this is a constant.
-  const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Node);
+  const auto *C = dyn_cast<ConstantIntSDNode>(Node);
   if (!C)
     return false;
 
@@ -503,7 +503,7 @@
   // will make other uses incorrect, so don't.
   if (!N.hasOneUse()) return false;
   // Check if the multiply is by a constant
-  ConstantSDNode *MulConst = dyn_cast<ConstantSDNode>(N.getOperand(1));
+  auto *MulConst = dyn_cast<ConstantIntSDNode>(N.getOperand(1));
   if (!MulConst) return false;
   // If the constant is used in more than one place then modifying it will mean
   // we need to materialize two constants instead of one, which is a bad idea.
@@ -562,7 +562,7 @@
 
   BaseReg = N.getOperand(0);
   unsigned ShImmVal = 0;
-  ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
+  auto *RHS = dyn_cast<ConstantIntSDNode>(N.getOperand(1));
   if (!RHS) return false;
   ShImmVal = RHS->getZExtValue() & 31;
   Opc = CurDAG->getTargetConstant(ARM_AM::getSORegOpc(ShOpcVal, ShImmVal),
@@ -586,7 +586,7 @@
 
   BaseReg = N.getOperand(0);
   unsigned ShImmVal = 0;
-  ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
+  auto *RHS = dyn_cast<ConstantIntSDNode>(N.getOperand(1));
   if (RHS) return false;
 
   ShReg = N.getOperand(1);
@@ -626,7 +626,7 @@
     return true;
   }
 
-  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
+  if (auto *RHS = dyn_cast<ConstantIntSDNode>(N.getOperand(1))) {
     int RHSC = (int)RHS->getSExtValue();
     if (N.getOpcode() == ISD::SUB)
       RHSC = -RHSC;
@@ -655,7 +655,7 @@
                                       SDValue &Opc) {
   if (N.getOpcode() == ISD::MUL &&
       ((!Subtarget->isLikeA9() && !Subtarget->isSwift()) || N.hasOneUse())) {
-    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
+    if (auto *RHS = dyn_cast<ConstantIntSDNode>(N.getOperand(1))) {
       // X * [3,5,9] -> X + X * [2,4,8] etc.
       int RHSC = (int)RHS->getZExtValue();
       if (RHSC & 1) {
@@ -702,8 +702,7 @@
   if (ShOpcVal != ARM_AM::no_shift) {
     // Check to see if the RHS of the shift is a constant, if not, we can't fold
     // it.
-    if (ConstantSDNode *Sh =
-           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
+    if (auto *Sh = dyn_cast<ConstantIntSDNode>(N.getOperand(1).getOperand(1))) {
       ShAmt = Sh->getZExtValue();
       if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
         Offset = N.getOperand(1).getOperand(0);
@@ -724,8 +723,8 @@
     if (ShOpcVal != ARM_AM::no_shift) {
       // Check to see if the RHS of the shift is a constant, if not, we can't
       // fold it.
-      if (ConstantSDNode *Sh =
-          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
+      if (auto *Sh =
+              dyn_cast<ConstantIntSDNode>(N.getOperand(0).getOperand(1))) {
         ShAmt = Sh->getZExtValue();
         if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
           Offset = N.getOperand(0).getOperand(0);
@@ -766,7 +765,7 @@
                                                      SDValue &Opc) {
   if (N.getOpcode() == ISD::MUL &&
       (!(Subtarget->isLikeA9() || Subtarget->isSwift()) || N.hasOneUse())) {
-    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
+    if (auto *RHS = dyn_cast<ConstantIntSDNode>(N.getOperand(1))) {
       // X * [3,5,9] -> X + X * [2,4,8] etc.
       int RHSC = (int)RHS->getZExtValue();
       if (RHSC & 1) {
@@ -856,8 +855,7 @@
   if (ShOpcVal != ARM_AM::no_shift) {
     // Check to see if the RHS of the shift is a constant, if not, we can't fold
     // it.
-    if (ConstantSDNode *Sh =
-           dyn_cast<ConstantSDNode>(N.getOperand(1).getOperand(1))) {
+    if (auto *Sh = dyn_cast<ConstantIntSDNode>(N.getOperand(1).getOperand(1))) {
       ShAmt = Sh->getZExtValue();
       if (isShifterOpProfitable(Offset, ShOpcVal, ShAmt))
         Offset = N.getOperand(1).getOperand(0);
@@ -878,8 +876,8 @@
     if (ShOpcVal != ARM_AM::no_shift) {
       // Check to see if the RHS of the shift is a constant, if not, we can't
       // fold it.
-      if (ConstantSDNode *Sh =
-          dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
+      if (auto *Sh =
+              dyn_cast<ConstantIntSDNode>(N.getOperand(0).getOperand(1))) {
         ShAmt = Sh->getZExtValue();
         if (isShifterOpProfitable(N.getOperand(0), ShOpcVal, ShAmt)) {
           Offset = N.getOperand(0).getOperand(0);
@@ -917,7 +915,7 @@
   if (ShOpcVal != ARM_AM::no_shift) {
     // Check to see if the RHS of the shift is a constant, if not, we can't fold
     // it.
-    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
+    if (auto *Sh = dyn_cast<ConstantIntSDNode>(N.getOperand(1))) {
       ShAmt = Sh->getZExtValue();
       if (isShifterOpProfitable(N, ShOpcVal, ShAmt))
         Offset = N.getOperand(0);
@@ -1138,7 +1136,7 @@
   if (AM != ISD::POST_INC)
     return false;
   Offset = N;
-  if (ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N)) {
+  if (auto *NC = dyn_cast<ConstantIntSDNode>(N)) {
     if (NC->getZExtValue() * 8 == LdSt->getMemoryVT().getSizeInBits())
       Offset = CurDAG->getRegister(0, MVT::i32);
   }
@@ -1150,8 +1148,8 @@
   if (N.getOpcode() == ARMISD::PIC_ADD && N.hasOneUse()) {
     Offset = N.getOperand(0);
     SDValue N1 = N.getOperand(1);
-    Label = CurDAG->getTargetConstant(cast<ConstantSDNode>(N1)->getZExtValue(),
-                                      SDLoc(N), MVT::i32);
+    Label = CurDAG->getTargetConstant(
+        cast<ConstantIntSDNode>(N1)->getZExtValue(), SDLoc(N), MVT::i32);
     return true;
   }
 
@@ -1166,7 +1164,7 @@
 bool ARMDAGToDAGISel::SelectThumbAddrModeRR(SDValue N,
                                             SDValue &Base, SDValue &Offset){
   if (N.getOpcode() != ISD::ADD && !CurDAG->isBaseWithConstantOffset(N)) {
-    ConstantSDNode *NC = dyn_cast<ConstantSDNode>(N);
+    auto *NC = dyn_cast<ConstantIntSDNode>(N);
     if (!NC || !NC->isNullValue())
       return false;
 
@@ -1307,7 +1305,7 @@
     return true;
   }
 
-  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
+  if (auto *RHS = dyn_cast<ConstantIntSDNode>(N.getOperand(1))) {
     if (SelectT2AddrModeImm8(N, Base, OffImm))
       // Let t2LDRi8 handle (R - imm8).
       return false;
@@ -1341,7 +1339,7 @@
       !CurDAG->isBaseWithConstantOffset(N))
     return false;
 
-  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
+  if (auto *RHS = dyn_cast<ConstantIntSDNode>(N.getOperand(1))) {
     int RHSC = (int)RHS->getSExtValue();
     if (N.getOpcode() == ISD::SUB)
       RHSC = -RHSC;
@@ -1386,7 +1384,7 @@
     return false;
 
   // Leave (R + imm12) for t2LDRi12, (R - imm8) for t2LDRi8.
-  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
+  if (auto *RHS = dyn_cast<ConstantIntSDNode>(N.getOperand(1))) {
     int RHSC = (int)RHS->getZExtValue();
     if (RHSC >= 0 && RHSC < 0x1000) // 12 bits (unsigned)
       return false;
@@ -1410,7 +1408,7 @@
   if (ShOpcVal == ARM_AM::lsl) {
     // Check to see if the RHS of the shift is a constant, if not, we can't fold
     // it.
-    if (ConstantSDNode *Sh = dyn_cast<ConstantSDNode>(OffReg.getOperand(1))) {
+    if (auto *Sh = dyn_cast<ConstantIntSDNode>(OffReg.getOperand(1))) {
       ShAmt = Sh->getZExtValue();
       if (ShAmt < 4 && isShifterOpProfitable(OffReg, ShOpcVal, ShAmt))
         OffReg = OffReg.getOperand(0);
@@ -1446,7 +1444,7 @@
   if (N.getOpcode() != ISD::ADD || !CurDAG->isBaseWithConstantOffset(N))
     return true;
 
-  ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1));
+  auto *RHS = dyn_cast<ConstantIntSDNode>(N.getOperand(1));
   if (!RHS)
     return true;
 
@@ -1565,7 +1563,7 @@
       AM != ISD::POST_INC || LoadedVT.getSimpleVT().SimpleTy != MVT::i32)
     return false;
 
-  auto *COffs = dyn_cast<ConstantSDNode>(LD->getOffset());
+  auto *COffs = dyn_cast<ConstantIntSDNode>(LD->getOffset());
   if (!COffs || COffs->getZExtValue() != 4)
     return false;
 
@@ -1733,7 +1731,7 @@
   if (!is64BitVector && NumVecs < 3)
     NumRegs *= 2;
 
-  unsigned Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
+  unsigned Alignment = cast<ConstantIntSDNode>(Align)->getZExtValue();
   if (Alignment >= 32 && NumRegs == 4)
     Alignment = 32;
   else if (Alignment >= 16 && (NumRegs == 2 || NumRegs == 4))
@@ -1915,13 +1913,13 @@
       SDValue Inc = N->getOperand(AddrOpIdx + 1);
       // FIXME: VLD1/VLD2 fixed increment doesn't need Reg0. Remove the reg0
       // case entirely when the rest are updated to that form, too.
-      if ((NumVecs <= 2) && !isa<ConstantSDNode>(Inc.getNode()))
+      if ((NumVecs <= 2) && !isa<ConstantIntSDNode>(Inc.getNode()))
         Opc = getVLDSTRegisterUpdateOpcode(Opc);
       // FIXME: We use a VLD1 for v1i64 even if the pseudo says vld2/3/4, so
       // check for that explicitly too. Horribly hacky, but temporary.
       if ((NumVecs > 2 && !isVLDfixed(Opc)) ||
-          !isa<ConstantSDNode>(Inc.getNode()))
-        Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
+          !isa<ConstantIntSDNode>(Inc.getNode()))
+        Ops.push_back(isa<ConstantIntSDNode>(Inc.getNode()) ? Reg0 : Inc);
     }
     Ops.push_back(Pred);
     Ops.push_back(Reg0);
@@ -1947,7 +1945,7 @@
     Ops.push_back(Align);
     if (isUpdating) {
       SDValue Inc = N->getOperand(AddrOpIdx + 1);
-      assert(isa<ConstantSDNode>(Inc.getNode()) &&
+      assert(isa<ConstantIntSDNode>(Inc.getNode()) &&
              "only constant post-increment update allowed for VLD3/4");
       (void)Inc;
       Ops.push_back(Reg0);
@@ -2069,11 +2067,11 @@
       SDValue Inc = N->getOperand(AddrOpIdx + 1);
       // FIXME: VST1/VST2 fixed increment doesn't need Reg0. Remove the reg0
       // case entirely when the rest are updated to that form, too.
-      if (NumVecs <= 2 && !isa<ConstantSDNode>(Inc.getNode()))
+      if (NumVecs <= 2 && !isa<ConstantIntSDNode>(Inc.getNode()))
         Opc = getVLDSTRegisterUpdateOpcode(Opc);
       // FIXME: We use a VST1 for v1i64 even if the pseudo says vld2/3/4, so
       // check for that explicitly too. Horribly hacky, but temporary.
-      if  (!isa<ConstantSDNode>(Inc.getNode()))
+      if (!isa<ConstantIntSDNode>(Inc.getNode()))
         Ops.push_back(Inc);
       else if (NumVecs > 2 && !isVSTfixed(Opc))
         Ops.push_back(Reg0);
@@ -2117,7 +2115,7 @@
   Ops.push_back(Align);
   if (isUpdating) {
     SDValue Inc = N->getOperand(AddrOpIdx + 1);
-    assert(isa<ConstantSDNode>(Inc.getNode()) &&
+    assert(isa<ConstantIntSDNode>(Inc.getNode()) &&
            "only constant post-increment update allowed for VST3/4");
     (void)Inc;
     Ops.push_back(Reg0);
@@ -2150,13 +2148,13 @@
 
   SDValue Chain = N->getOperand(0);
   unsigned Lane =
-    cast<ConstantSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
+      cast<ConstantIntSDNode>(N->getOperand(Vec0Idx + NumVecs))->getZExtValue();
   EVT VT = N->getOperand(Vec0Idx).getValueType();
   bool is64BitVector = VT.is64BitVector();
 
   unsigned Alignment = 0;
   if (NumVecs != 3) {
-    Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
+    Alignment = cast<ConstantIntSDNode>(Align)->getZExtValue();
     unsigned NumBytes = NumVecs * VT.getScalarSizeInBits() / 8;
     if (Alignment > NumBytes)
       Alignment = NumBytes;
@@ -2203,7 +2201,7 @@
   Ops.push_back(Align);
   if (isUpdating) {
     SDValue Inc = N->getOperand(AddrOpIdx + 1);
-    Ops.push_back(isa<ConstantSDNode>(Inc.getNode()) ? Reg0 : Inc);
+    Ops.push_back(isa<ConstantIntSDNode>(Inc.getNode()) ? Reg0 : Inc);
   }
 
   SDValue SuperReg;
@@ -2271,7 +2269,7 @@
 
   unsigned Alignment = 0;
   if (NumVecs != 3) {
-    Alignment = cast<ConstantSDNode>(Align)->getZExtValue();
+    Alignment = cast<ConstantIntSDNode>(Align)->getZExtValue();
     unsigned NumBytes = NumVecs * VT.getScalarSizeInBits() / 8;
     if (Alignment > NumBytes)
       Alignment = NumBytes;
@@ -2304,7 +2302,7 @@
     // fixed-stride update instructions don't have an explicit writeback
     // operand. It's implicit in the opcode itself.
     SDValue Inc = N->getOperand(2);
-    if (!isa<ConstantSDNode>(Inc.getNode()))
+    if (!isa<ConstantIntSDNode>(Inc.getNode()))
       Ops.push_back(Inc);
     // FIXME: VLD3 and VLD4 haven't been updated to that form yet.
     else if (NumVecs > 2)
@@ -2521,7 +2519,7 @@
   SDValue ADDSrc1 = XORSrc0.getOperand(1);
   SDValue SRASrc0 = XORSrc1.getOperand(0);
   SDValue SRASrc1 = XORSrc1.getOperand(1);
-  ConstantSDNode *SRAConstant =  dyn_cast<ConstantSDNode>(SRASrc1);
+  auto *SRAConstant = dyn_cast<ConstantIntSDNode>(SRASrc1);
   EVT XType = SRASrc0.getValueType();
   unsigned Size = XType.getSizeInBits() - 1;
 
@@ -2554,7 +2552,7 @@
   if (SignExt.getOpcode() != ISD::SRA)
     return false;
 
-  ConstantSDNode *SRASrc1 = dyn_cast<ConstantSDNode>(SignExt.getOperand(1));
+  auto *SRASrc1 = dyn_cast<ConstantIntSDNode>(SignExt.getOperand(1));
   if (!SRASrc1 || SRASrc1->getZExtValue() != 16)
     return false;
 
@@ -2563,7 +2561,7 @@
   // The sign extend operand for SM*WB could be generated by a shl and ashr.
   if (Op0.getOpcode() == ISD::SHL) {
     SDValue SHL = Op0;
-    ConstantSDNode *SHLSrc1 = dyn_cast<ConstantSDNode>(SHL.getOperand(1));
+    auto *SHLSrc1 = dyn_cast<ConstantIntSDNode>(SHL.getOperand(1));
     if (!SHLSrc1 || SHLSrc1->getZExtValue() != 16)
       return false;
 
@@ -2593,8 +2591,8 @@
       return false;
   }
 
-  ConstantSDNode *SRLSrc1 = dyn_cast<ConstantSDNode>(SRL.getOperand(1));
-  ConstantSDNode *SHLSrc1 = dyn_cast<ConstantSDNode>(SHL.getOperand(1));
+  auto *SRLSrc1 = dyn_cast<ConstantIntSDNode>(SRL.getOperand(1));
+  auto *SHLSrc1 = dyn_cast<ConstantIntSDNode>(SHL.getOperand(1));
   if (!SRLSrc1 || !SHLSrc1 || SRLSrc1->getZExtValue() != 16 ||
       SHLSrc1->getZExtValue() != 16)
     return false;
@@ -2742,7 +2740,7 @@
     // Other cases are autogenerated.
     break;
   case ISD::Constant: {
-    unsigned Val = cast<ConstantSDNode>(N)->getZExtValue();
+    unsigned Val = cast<ConstantIntSDNode>(N)->getZExtValue();
     // If we can't materialize the constant we need to use a literal pool
     if (ConstantMaterializationCost(Val) > 2) {
       SDValue CPIdx = CurDAG->getTargetConstantPool(
@@ -2810,7 +2808,7 @@
   case ISD::MUL:
     if (Subtarget->isThumb1Only())
       break;
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(N->getOperand(1))) {
       unsigned RHSV = C->getZExtValue();
       if (!RHSV) break;
       if (isPowerOf2_32(RHSV-1)) {  // 2^n+1?
@@ -2861,7 +2859,7 @@
     // If an immediate is used in an AND node, it is possible that the immediate
     // can be more optimally materialized when negated. If this is the case we
     // can negate the immediate and use a BIC instead.
-    auto *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1));
+    auto *N1C = dyn_cast<ConstantIntSDNode>(N->getOperand(1));
     if (N1C && N1C->hasOneUse() && Subtarget->isThumb()) {
       uint32_t Imm = (uint32_t) N1C->getZExtValue();
 
@@ -2914,12 +2912,12 @@
     if (!Opc)
       break;
     SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
-    N1C = dyn_cast<ConstantSDNode>(N1);
+    N1C = dyn_cast<ConstantIntSDNode>(N1);
     if (!N1C)
       break;
     if (N0.getOpcode() == ISD::OR && N0.getNode()->hasOneUse()) {
       SDValue N2 = N0.getOperand(1);
-      ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
+      auto *N2C = dyn_cast<ConstantIntSDNode>(N2);
       if (!N2C)
         break;
       unsigned N1CVal = N1C->getZExtValue();
@@ -3000,8 +2998,8 @@
 
       if (Adde.getOperand(2).getNode() == Addc.getNode()) {
 
-        ConstantSDNode *Op0 = dyn_cast<ConstantSDNode>(Adde.getOperand(0));
-        ConstantSDNode *Op1 = dyn_cast<ConstantSDNode>(Adde.getOperand(1));
+        auto *Op0 = dyn_cast<ConstantIntSDNode>(Adde.getOperand(0));
+        auto *Op1 = dyn_cast<ConstantIntSDNode>(Adde.getOperand(1));
 
         if (Op0 && Op1 && Op0->getZExtValue() == 0 && Op1->getZExtValue() == 0)
         {
@@ -3074,7 +3072,7 @@
 
     SDValue SmulLoHi = N->getOperand(1);
     SDValue Subc = N->getOperand(2);
-    auto *Zero = dyn_cast<ConstantSDNode>(Subc.getOperand(0));
+    auto *Zero = dyn_cast<ConstantIntSDNode>(Subc.getOperand(0));
 
     if (!Zero || Zero->getZExtValue() != 0 ||
         Subc.getOperand(1) != SmulLoHi.getValue(0) ||
@@ -3125,9 +3123,8 @@
     assert(N2.getOpcode() == ISD::Constant);
     assert(N3.getOpcode() == ISD::Register);
 
-    SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
-                               cast<ConstantSDNode>(N2)->getZExtValue()), dl,
-                               MVT::i32);
+    SDValue Tmp2 = CurDAG->getTargetConstant(
+        ((unsigned)cast<ConstantIntSDNode>(N2)->getZExtValue()), dl, MVT::i32);
     SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
     SDNode *ResNode = CurDAG->getMachineNode(Opc, dl, MVT::Other,
                                              MVT::Glue, Ops);
@@ -3148,7 +3145,7 @@
     //   The CMPZ #0 is useless and will be peepholed away but we need to keep it
     //   for its glue output.
     SDValue X = N->getOperand(0);
-    auto *C = dyn_cast<ConstantSDNode>(N->getOperand(1).getNode());
+    auto *C = dyn_cast<ConstantIntSDNode>(N->getOperand(1).getNode());
     if (C && C->getSExtValue() < 0 && Subtarget->isThumb()) {
       int64_t Addend = -C->getSExtValue();
 
@@ -3487,7 +3484,7 @@
 
   case ISD::INTRINSIC_VOID:
   case ISD::INTRINSIC_W_CHAIN: {
-    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
+    unsigned IntNo = cast<ConstantIntSDNode>(N->getOperand(1))->getZExtValue();
     switch (IntNo) {
     default:
       break;
@@ -3504,9 +3501,15 @@
         Opc = (IntNo == Intrinsic::arm_mrrc ? ARM::MRRC : ARM::MRRC2);
 
       SmallVector<SDValue, 5> Ops;
-      Ops.push_back(getI32Imm(cast<ConstantSDNode>(N->getOperand(2))->getZExtValue(), dl)); /* coproc */
-      Ops.push_back(getI32Imm(cast<ConstantSDNode>(N->getOperand(3))->getZExtValue(), dl)); /* opc */
-      Ops.push_back(getI32Imm(cast<ConstantSDNode>(N->getOperand(4))->getZExtValue(), dl)); /* CRm */
+      Ops.push_back(
+          getI32Imm(cast<ConstantIntSDNode>(N->getOperand(2))->getZExtValue(),
+                    dl)); /* coproc */
+      Ops.push_back(
+          getI32Imm(cast<ConstantIntSDNode>(N->getOperand(3))->getZExtValue(),
+                    dl)); /* opc */
+      Ops.push_back(
+          getI32Imm(cast<ConstantIntSDNode>(N->getOperand(4))->getZExtValue(),
+                    dl)); /* CRm */
 
       // The mrrc2 instruction in ARM doesn't allow predicates, the top 4 bits of the encoded
       // instruction will always be '1111' but it is possible in assembly language to specify
@@ -3785,7 +3788,7 @@
   }
 
   case ISD::INTRINSIC_WO_CHAIN: {
-    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
+    unsigned IntNo = cast<ConstantIntSDNode>(N->getOperand(0))->getZExtValue();
     switch (IntNo) {
     default:
       break;
@@ -4330,7 +4333,7 @@
     if (i < InlineAsm::Op_FirstOperand)
       continue;
 
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(i))) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(N->getOperand(i))) {
       Flag = C->getZExtValue();
       Kind = InlineAsm::getKind(Flag);
     }
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -3292,7 +3292,7 @@
 SDValue
 ARMTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
                                           const ARMSubtarget *Subtarget) const {
-  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned IntNo = cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
   SDLoc dl(Op);
   switch (IntNo) {
   default: return SDValue();    // Don't custom lower most intrinsics.
@@ -3382,7 +3382,7 @@
                        DAG.getConstant(0, dl, MVT::i32));
   }
 
-  ConstantSDNode *OrdN = cast<ConstantSDNode>(Op.getOperand(1));
+  auto *OrdN = cast<ConstantIntSDNode>(Op.getOperand(1));
   AtomicOrdering Ord = static_cast<AtomicOrdering>(OrdN->getZExtValue());
   ARM_MB::MemBOpt Domain = ARM_MB::ISH;
   if (Subtarget->isMClass()) {
@@ -3410,13 +3410,14 @@
     return Op.getOperand(0);
 
   SDLoc dl(Op);
-  unsigned isRead = ~cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() & 1;
+  unsigned isRead =
+      ~cast<ConstantIntSDNode>(Op.getOperand(2))->getZExtValue() & 1;
   if (!isRead &&
       (!Subtarget->hasV7Ops() || !Subtarget->hasMPExtension()))
     // ARMv7 with MP extension has PLDW.
     return Op.getOperand(0);
 
-  unsigned isData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
+  unsigned isData = cast<ConstantIntSDNode>(Op.getOperand(4))->getZExtValue();
   if (Subtarget->isThumb()) {
     // Invert the bits.
     isRead = ~isRead & 1;
@@ -3789,7 +3790,7 @@
 SDValue ARMTargetLowering::getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
                                      SDValue &ARMcc, SelectionDAG &DAG,
                                      const SDLoc &dl) const {
-  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
+  if (auto *RHSC = dyn_cast<ConstantIntSDNode>(RHS.getNode())) {
     unsigned C = RHSC->getZExtValue();
     if (!isLegalICmpImmediate(C)) {
       // Constant does not fit, try adjusting it by one?
@@ -3973,10 +3974,8 @@
   //   (select (cmov 0, 1, cond), t, f) -> (cmov f, t, cond)
   //
   if (Cond.getOpcode() == ARMISD::CMOV && Cond.hasOneUse()) {
-    const ConstantSDNode *CMOVTrue =
-      dyn_cast<ConstantSDNode>(Cond.getOperand(0));
-    const ConstantSDNode *CMOVFalse =
-      dyn_cast<ConstantSDNode>(Cond.getOperand(1));
+    const auto *CMOVTrue = dyn_cast<ConstantIntSDNode>(Cond.getOperand(0));
+    const auto *CMOVFalse = dyn_cast<ConstantIntSDNode>(Cond.getOperand(1));
 
     if (CMOVTrue && CMOVFalse) {
       unsigned CMOVTrueVal = CMOVTrue->getZExtValue();
@@ -4143,7 +4142,7 @@
   SDValue FalseVal1 = Op.getOperand(3);
   ISD::CondCode CC1 = cast<CondCodeSDNode>(Op.getOperand(4))->get();
 
-  const SDValue Op2 = isa<ConstantSDNode>(TrueVal1) ? FalseVal1 : TrueVal1;
+  const SDValue Op2 = isa<ConstantIntSDNode>(TrueVal1) ? FalseVal1 : TrueVal1;
   if (Op2.getOpcode() != ISD::SELECT_CC)
     return false;
 
@@ -4155,13 +4154,13 @@
 
   // Find out which are the constants and which are the variables
   // in each conditional
-  SDValue *K1 = isa<ConstantSDNode>(LHS1) ? &LHS1 : isa<ConstantSDNode>(RHS1)
-                                                        ? &RHS1
-                                                        : NULL;
-  SDValue *K2 = isa<ConstantSDNode>(LHS2) ? &LHS2 : isa<ConstantSDNode>(RHS2)
-                                                        ? &RHS2
-                                                        : NULL;
-  SDValue K2Tmp = isa<ConstantSDNode>(TrueVal2) ? TrueVal2 : FalseVal2;
+  SDValue *K1 = isa<ConstantIntSDNode>(LHS1)
+                    ? &LHS1
+                    : isa<ConstantIntSDNode>(RHS1) ? &RHS1 : NULL;
+  SDValue *K2 = isa<ConstantIntSDNode>(LHS2)
+                    ? &LHS2
+                    : isa<ConstantIntSDNode>(RHS2) ? &RHS2 : NULL;
+  SDValue K2Tmp = isa<ConstantIntSDNode>(TrueVal2) ? TrueVal2 : FalseVal2;
   SDValue V1Tmp = (K1 && *K1 == LHS1) ? RHS1 : LHS1;
   SDValue V2Tmp = (K2 && *K2 == LHS2) ? RHS2 : LHS2;
   SDValue V2 = (K2Tmp == TrueVal2) ? FalseVal2 : TrueVal2;
@@ -4198,8 +4197,8 @@
   // Check that the constant in the lower-bound check is
   // the opposite of the constant in the upper-bound check
   // in 1's complement.
-  int64_t Val1 = cast<ConstantSDNode>(*K1)->getSExtValue();
-  int64_t Val2 = cast<ConstantSDNode>(*K2)->getSExtValue();
+  int64_t Val1 = cast<ConstantIntSDNode>(*K1)->getSExtValue();
+  int64_t Val2 = cast<ConstantIntSDNode>(*K2)->getSExtValue();
   int64_t PosVal = std::max(Val1, Val2);
 
   if (((Val1 > Val2 && UpperCheckOp == &Op) ||
@@ -4693,7 +4692,7 @@
 
   EVT VT = Op.getValueType();
   SDLoc dl(Op);
-  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned Depth = cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
   if (Depth) {
     SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
     SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
@@ -4716,7 +4715,7 @@
 
   EVT VT = Op.getValueType();
   SDLoc dl(Op);  // FIXME probably not meaningful
-  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned Depth = cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
   unsigned FrameReg = ARI.getFrameRegister(MF);
   SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT);
   while (Depth--)
@@ -4783,7 +4782,7 @@
   // If the index is not constant, we will introduce an additional
   // multiply that will stick.
   // Give up in that case.
-  ConstantSDNode *Index = dyn_cast<ConstantSDNode>(Op.getOperand(1));
+  auto *Index = dyn_cast<ConstantIntSDNode>(Op.getOperand(1));
   if (!Index)
     return SDValue();
   unsigned DstNumElt = DstVT.getVectorNumElements();
@@ -5991,9 +5990,9 @@
 static SDValue IsSingleInstrConstant(SDValue N, SelectionDAG &DAG,
                                      const ARMSubtarget *ST, const SDLoc &dl) {
   uint64_t Val;
-  if (!isa<ConstantSDNode>(N))
+  if (!isa<ConstantIntSDNode>(N))
     return SDValue();
-  Val = cast<ConstantSDNode>(N)->getZExtValue();
+  Val = cast<ConstantIntSDNode>(N)->getZExtValue();
 
   if (ST->isThumb1Only()) {
     if (Val <= 255 || ~Val <= 255)
@@ -6074,7 +6073,7 @@
       continue;
     if (i > 0)
       isOnlyLowElement = false;
-    if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V))
+    if (!isa<ConstantFPSDNode>(V) && !isa<ConstantIntSDNode>(V))
       isConstant = false;
 
     ValueCounts.insert(std::make_pair(V, 0));
@@ -6112,9 +6111,9 @@
       // just use VDUPLANE. We can only do this if the lane being extracted
       // is at a constant index, as the VDUP from lane instructions only have
       // constant-index forms.
-      ConstantSDNode *constIndex;
+      ConstantIntSDNode *constIndex;
       if (Value->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
-          (constIndex = dyn_cast<ConstantSDNode>(Value->getOperand(1)))) {
+          (constIndex = dyn_cast<ConstantIntSDNode>(Value->getOperand(1)))) {
         // We need to create a new undef vector to use for the VDUPLANE if the
         // size of the vector from which we get the value is different than the
         // size of the vector that we need to create. We will insert the element
@@ -6255,7 +6254,7 @@
       // A shuffle can only come from building a vector from various
       // elements of other vectors.
       return SDValue();
-    } else if (!isa<ConstantSDNode>(V.getOperand(1))) {
+    } else if (!isa<ConstantIntSDNode>(V.getOperand(1))) {
       // Furthermore, shuffles require a constant mask, whereas extractelts
       // accept variable indices.
       return SDValue();
@@ -6268,7 +6267,7 @@
       Source = Sources.insert(Sources.end(), ShuffleSourceInfo(SourceVec));
 
     // Update the minimum and maximum lane number seen.
-    unsigned EltNo = cast<ConstantSDNode>(V.getOperand(1))->getZExtValue();
+    unsigned EltNo = cast<ConstantIntSDNode>(V.getOperand(1))->getZExtValue();
     Source->MinElt = std::min(Source->MinElt, EltNo);
     Source->MaxElt = std::max(Source->MaxElt, EltNo);
   }
@@ -6380,7 +6379,7 @@
       continue;
 
     auto Src = find(Sources, Entry.getOperand(0));
-    int EltNo = cast<ConstantSDNode>(Entry.getOperand(1))->getSExtValue();
+    int EltNo = cast<ConstantIntSDNode>(Entry.getOperand(1))->getSExtValue();
 
     // EXTRACT_VECTOR_ELT performs an implicit any_ext; BUILD_VECTOR an implicit
     // trunc. So only std::min(SrcBits, DestBits) actually get defined in this
@@ -6605,7 +6604,7 @@
       // (and probably will turn into a SCALAR_TO_VECTOR once legalization
       // reaches it).
       if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
-          !isa<ConstantSDNode>(V1.getOperand(0))) {
+          !isa<ConstantIntSDNode>(V1.getOperand(0))) {
         bool IsScalarToVector = true;
         for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i)
           if (!V1.getOperand(i).isUndef()) {
@@ -6751,7 +6750,7 @@
 static SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
   // INSERT_VECTOR_ELT is legal only for immediate indexes.
   SDValue Lane = Op.getOperand(2);
-  if (!isa<ConstantSDNode>(Lane))
+  if (!isa<ConstantIntSDNode>(Lane))
     return SDValue();
 
   return Op;
@@ -6760,7 +6759,7 @@
 static SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
   // EXTRACT_VECTOR_ELT is legal only for immediate indexes.
   SDValue Lane = Op.getOperand(1);
-  if (!isa<ConstantSDNode>(Lane))
+  if (!isa<ConstantIntSDNode>(Lane))
     return SDValue();
 
   SDValue Vec = Op.getOperand(0);
@@ -6806,10 +6805,10 @@
       return false;
     unsigned LoElt = DAG.getDataLayout().isBigEndian() ? 1 : 0;
     unsigned HiElt = 1 - LoElt;
-    ConstantSDNode *Lo0 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt));
-    ConstantSDNode *Hi0 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt));
-    ConstantSDNode *Lo1 = dyn_cast<ConstantSDNode>(BVN->getOperand(LoElt+2));
-    ConstantSDNode *Hi1 = dyn_cast<ConstantSDNode>(BVN->getOperand(HiElt+2));
+    auto *Lo0 = dyn_cast<ConstantIntSDNode>(BVN->getOperand(LoElt));
+    auto *Hi0 = dyn_cast<ConstantIntSDNode>(BVN->getOperand(HiElt));
+    auto *Lo1 = dyn_cast<ConstantIntSDNode>(BVN->getOperand(LoElt + 2));
+    auto *Hi1 = dyn_cast<ConstantIntSDNode>(BVN->getOperand(HiElt + 2));
     if (!Lo0 || !Hi0 || !Lo1 || !Hi1)
       return false;
     if (isSigned) {
@@ -6828,7 +6827,7 @@
 
   for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
     SDNode *Elt = N->getOperand(i).getNode();
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Elt)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Elt)) {
       unsigned EltSize = VT.getScalarSizeInBits();
       unsigned HalfSize = EltSize / 2;
       if (isSigned) {
@@ -6962,7 +6961,7 @@
   SmallVector<SDValue, 8> Ops;
   SDLoc dl(N);
   for (unsigned i = 0; i != NumElts; ++i) {
-    ConstantSDNode *C = cast<ConstantSDNode>(N->getOperand(i));
+    auto *C = cast<ConstantIntSDNode>(N->getOperand(i));
     const APInt &CInt = C->getAPIntValue();
     // Element types smaller than 32 bits are not legal, so use i32 elements.
     // The values are implicitly truncated so sext vs. zext doesn't matter.
@@ -9146,8 +9145,8 @@
         return SDValue();
 
       // Second is the constant, verify its correct.
-      ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(ExtVec0->getOperand(1));
-      ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(ExtVec1->getOperand(1));
+      auto *C0 = dyn_cast<ConstantIntSDNode>(ExtVec0->getOperand(1));
+      auto *C1 = dyn_cast<ConstantIntSDNode>(ExtVec1->getOperand(1));
 
       // For the constant, we want to see all the even or all the odd.
       if (!C0 || !C1 || C0->getZExtValue() != nextIndex
@@ -9374,7 +9373,7 @@
 
   // The ADDC should be glued to an ADDE node, which uses the same UMLAL as
   // the ADDC as well as Zero.
-  auto *Zero = dyn_cast<ConstantSDNode>(UmlalNode->getOperand(3));
+  auto *Zero = dyn_cast<ConstantIntSDNode>(UmlalNode->getOperand(3));
 
   if (!Zero || Zero->getZExtValue() != 0)
     return SDValue();
@@ -9537,7 +9536,7 @@
   if (VT != MVT::i32)
     return SDValue();
 
-  ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
+  auto *C = dyn_cast<ConstantIntSDNode>(N->getOperand(1));
   if (!C)
     return SDValue();
 
@@ -9753,7 +9752,7 @@
   // actually a bitfield set. If the mask is 0xffff, we can do better
   // via a movt instruction, so don't use BFI in that case.
   SDValue MaskOp = N0.getOperand(1);
-  ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(MaskOp);
+  auto *MaskC = dyn_cast<ConstantIntSDNode>(MaskOp);
   if (!MaskC)
     return SDValue();
   unsigned Mask = MaskC->getZExtValue();
@@ -9761,7 +9760,7 @@
     return SDValue();
   SDValue Res;
   // Case (1): or (and A, mask), val => ARMbfi A, val, mask
-  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
+  auto *N1C = dyn_cast<ConstantIntSDNode>(N1);
   if (N1C) {
     unsigned Val = N1C->getZExtValue();
     if ((Val & ~Mask) != Val)
@@ -9780,7 +9779,7 @@
     }
   } else if (N1.getOpcode() == ISD::AND) {
     // case (2) or (and A, mask), (and B, mask2) => ARMbfi A, (lsr B, amt), mask
-    ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
+    auto *N11C = dyn_cast<ConstantIntSDNode>(N1.getOperand(1));
     if (!N11C)
       return SDValue();
     unsigned Mask2 = N11C->getZExtValue();
@@ -9823,12 +9822,13 @@
   }
 
   if (DAG.MaskedValueIsZero(N1, MaskC->getAPIntValue()) &&
-      N00.getOpcode() == ISD::SHL && isa<ConstantSDNode>(N00.getOperand(1)) &&
+      N00.getOpcode() == ISD::SHL &&
+      isa<ConstantIntSDNode>(N00.getOperand(1)) &&
       ARM::isBitFieldInvertedMask(~Mask)) {
     // Case (3): or (and (shl A, #shamt), mask), B => ARMbfi B, A, ~mask
     // where lsb(mask) == #shamt and masked bits of B are known zero.
     SDValue ShAmt = N00.getOperand(1);
-    unsigned ShAmtC = cast<ConstantSDNode>(ShAmt)->getZExtValue();
+    unsigned ShAmtC = cast<ConstantIntSDNode>(ShAmt)->getZExtValue();
     unsigned LSB = countTrailingZeros(Mask);
     if (ShAmtC != LSB)
       return SDValue();
@@ -9868,14 +9868,14 @@
   assert(N->getOpcode() == ARMISD::BFI);
 
   SDValue From = N->getOperand(1);
-  ToMask = ~cast<ConstantSDNode>(N->getOperand(2))->getAPIntValue();
+  ToMask = ~cast<ConstantIntSDNode>(N->getOperand(2))->getAPIntValue();
   FromMask = APInt::getLowBitsSet(ToMask.getBitWidth(), ToMask.countPopulation());
 
   // If the Base came from a SHR #C, we can deduce that it is really testing bit
   // #C in the base of the SHR.
   if (From->getOpcode() == ISD::SRL &&
-      isa<ConstantSDNode>(From->getOperand(1))) {
-    APInt Shift = cast<ConstantSDNode>(From->getOperand(1))->getAPIntValue();
+      isa<ConstantIntSDNode>(From->getOperand(1))) {
+    APInt Shift = cast<ConstantIntSDNode>(From->getOperand(1))->getAPIntValue();
     assert(Shift.getLimitedValue() < 32 && "Shift too large!");
     FromMask <<= Shift.getLimitedValue(31);
     From = From->getOperand(0);
@@ -9943,10 +9943,11 @@
   if (N1.getOpcode() == ISD::AND) {
     // (bfi A, (and B, Mask1), Mask2) -> (bfi A, B, Mask2) iff
     // the bits being cleared by the AND are not demanded by the BFI.
-    ConstantSDNode *N11C = dyn_cast<ConstantSDNode>(N1.getOperand(1));
+    auto *N11C = dyn_cast<ConstantIntSDNode>(N1.getOperand(1));
     if (!N11C)
       return SDValue();
-    unsigned InvMask = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
+    unsigned InvMask =
+        cast<ConstantIntSDNode>(N->getOperand(2))->getZExtValue();
     unsigned LSB = countTrailingZeros(~InvMask);
     unsigned Width = (32 - countLeadingZeros(~InvMask)) - LSB;
     assert(Width <
@@ -10146,7 +10147,7 @@
       // Assume only bit cast to i32 will go away.
       if (Elt->getOperand(0).getValueType() == MVT::i32)
         ++NumOfBitCastedElts;
-    } else if (Elt.isUndef() || isa<ConstantSDNode>(Elt))
+    } else if (Elt.isUndef() || isa<ConstantIntSDNode>(Elt))
       // Constants are statically casted, thus do not count them as
       // relevant operands.
       --NumOfRelevantElts;
@@ -10306,7 +10307,8 @@
     unsigned NewOpc = 0;
     unsigned NumVecs = 0;
     if (isIntrinsic) {
-      unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
+      unsigned IntNo =
+          cast<ConstantIntSDNode>(N->getOperand(1))->getZExtValue();
       switch (IntNo) {
       default: llvm_unreachable("unexpected intrinsic for Neon base update");
       case Intrinsic::arm_neon_vld1:     NewOpc = ARMISD::VLD1_UPD;
@@ -10369,7 +10371,7 @@
 
     // If the increment is a constant, it must match the memory ref size.
     SDValue Inc = User->getOperand(User->getOperand(0) == Addr ? 1 : 0);
-    if (ConstantSDNode *CInc = dyn_cast<ConstantSDNode>(Inc.getNode())) {
+    if (auto *CInc = dyn_cast<ConstantIntSDNode>(Inc.getNode())) {
       uint64_t IncVal = CInc->getZExtValue();
       if (IncVal != NumBytes)
         continue;
@@ -10506,7 +10508,7 @@
     return false;
   unsigned NumVecs = 0;
   unsigned NewOpc = 0;
-  unsigned IntNo = cast<ConstantSDNode>(VLD->getOperand(1))->getZExtValue();
+  unsigned IntNo = cast<ConstantIntSDNode>(VLD->getOperand(1))->getZExtValue();
   if (IntNo == Intrinsic::arm_neon_vld2lane) {
     NumVecs = 2;
     NewOpc = ARMISD::VLD2DUP;
@@ -10523,7 +10525,7 @@
   // First check that all the vldN-lane uses are VDUPLANEs and that the lane
   // numbers match the load.
   unsigned VLDLaneNo =
-    cast<ConstantSDNode>(VLD->getOperand(NumVecs+3))->getZExtValue();
+      cast<ConstantIntSDNode>(VLD->getOperand(NumVecs + 3))->getZExtValue();
   for (SDNode::use_iterator UI = VLD->use_begin(), UE = VLD->use_end();
        UI != UE; ++UI) {
     // Ignore uses of the chain result.
@@ -10531,7 +10533,8 @@
       continue;
     SDNode *User = *UI;
     if (User->getOpcode() != ARMISD::VDUPLANE ||
-        VLDLaneNo != cast<ConstantSDNode>(User->getOperand(1))->getZExtValue())
+        VLDLaneNo !=
+            cast<ConstantIntSDNode>(User->getOperand(1))->getZExtValue())
       return false;
   }
 
@@ -10591,7 +10594,7 @@
   // Make sure the VMOV element size is not bigger than the VDUPLANE elements.
   unsigned EltSize = Op.getScalarValueSizeInBits();
   // The canonical VMOV for a zero vector uses a 32-bit element size.
-  unsigned Imm = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned Imm = cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
   unsigned EltBits;
   if (ARM_AM::decodeNEONModImm(Imm, EltBits) == 0)
     EltSize = 8;
@@ -10931,7 +10934,7 @@
 
 /// PerformIntrinsicCombine - ARM-specific DAG combining for intrinsics.
 static SDValue PerformIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
-  unsigned IntNo = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
+  unsigned IntNo = cast<ConstantIntSDNode>(N->getOperand(0))->getZExtValue();
   switch (IntNo) {
   default:
     // Don't do anything for most intrinsics.
@@ -11084,7 +11087,7 @@
     // Canonicalize (srl (bswap x), 16) to (rotr (bswap x), 16) if the high
     // 16-bits of x is zero. This optimizes rev + lsr 16 to rev16.
     SDValue N1 = N->getOperand(1);
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N1)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(N1)) {
       SDValue N0 = N->getOperand(0);
       if (C->getZExtValue() == 16 && N0.getOpcode() == ISD::BSWAP &&
           DAG.MaskedValueIsZero(N0.getOperand(0),
@@ -11142,10 +11145,8 @@
     EVT EltVT = N0.getValueType();
     const TargetLowering &TLI = DAG.getTargetLoweringInfo();
 
-    if (VT == MVT::i32 &&
-        (EltVT == MVT::i8 || EltVT == MVT::i16) &&
-        TLI.isTypeLegal(Vec.getValueType()) &&
-        isa<ConstantSDNode>(Lane)) {
+    if (VT == MVT::i32 && (EltVT == MVT::i8 || EltVT == MVT::i16) &&
+        TLI.isTypeLegal(Vec.getValueType()) && isa<ConstantIntSDNode>(Lane)) {
 
       unsigned Opc = 0;
       switch (N->getOpcode()) {
@@ -11174,7 +11175,7 @@
 
     // The operand to BFI is already a mask suitable for removing the bits it
     // sets.
-    ConstantSDNode *CI = cast<ConstantSDNode>(Op.getOperand(2));
+    auto *CI = cast<ConstantIntSDNode>(Op.getOperand(2));
     const APInt &Mask = CI->getAPIntValue();
     KnownZero &= Mask;
     KnownOne &= Mask;
@@ -11209,7 +11210,7 @@
 
   SDValue Op0 = CMOV->getOperand(0);
   SDValue Op1 = CMOV->getOperand(1);
-  auto CCNode = cast<ConstantSDNode>(CMOV->getOperand(2));
+  auto CCNode = cast<ConstantIntSDNode>(CMOV->getOperand(2));
   auto CC = CCNode->getAPIntValue().getLimitedValue();
   SDValue CmpZ = CMOV->getOperand(4);
 
@@ -11221,7 +11222,7 @@
   SDValue And = CmpZ->getOperand(0);
   if (And->getOpcode() != ISD::AND)
     return SDValue();
-  ConstantSDNode *AndC = dyn_cast<ConstantSDNode>(And->getOperand(1));
+  auto *AndC = dyn_cast<ConstantIntSDNode>(And->getOperand(1));
   if (!AndC || !AndC->getAPIntValue().isPowerOf2())
     return SDValue();
   SDValue X = And->getOperand(0);
@@ -11237,7 +11238,7 @@
   if (Op1->getOpcode() != ISD::OR)
     return SDValue();
 
-  ConstantSDNode *OrC = dyn_cast<ConstantSDNode>(Op1->getOperand(1));
+  auto *OrC = dyn_cast<ConstantIntSDNode>(Op1->getOperand(1));
   if (!OrC)
     return SDValue();
   SDValue Y = Op1->getOperand(0);
@@ -11300,17 +11301,19 @@
   SDValue BB = N->getOperand(1);
   SDValue ARMcc = N->getOperand(2);
   ARMCC::CondCodes CC =
-    (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
+      (ARMCC::CondCodes)cast<ConstantIntSDNode>(ARMcc)->getZExtValue();
 
   // (brcond Chain BB ne CPSR (cmpz (and (cmov 0 1 CC CPSR Cmp) 1) 0))
   // -> (brcond Chain BB CC CPSR Cmp)
   if (CC == ARMCC::NE && LHS.getOpcode() == ISD::AND && LHS->hasOneUse() &&
       LHS->getOperand(0)->getOpcode() == ARMISD::CMOV &&
       LHS->getOperand(0)->hasOneUse()) {
-    auto *LHS00C = dyn_cast<ConstantSDNode>(LHS->getOperand(0)->getOperand(0));
-    auto *LHS01C = dyn_cast<ConstantSDNode>(LHS->getOperand(0)->getOperand(1));
-    auto *LHS1C = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
-    auto *RHSC = dyn_cast<ConstantSDNode>(RHS);
+    auto *LHS00C =
+        dyn_cast<ConstantIntSDNode>(LHS->getOperand(0)->getOperand(0));
+    auto *LHS01C =
+        dyn_cast<ConstantIntSDNode>(LHS->getOperand(0)->getOperand(1));
+    auto *LHS1C = dyn_cast<ConstantIntSDNode>(LHS->getOperand(1));
+    auto *RHSC = dyn_cast<ConstantIntSDNode>(RHS);
     if ((LHS00C && LHS00C->getZExtValue() == 0) &&
         (LHS01C && LHS01C->getZExtValue() == 1) &&
         (LHS1C && LHS1C->getZExtValue() == 1) &&
@@ -11340,7 +11343,7 @@
   SDValue TrueVal = N->getOperand(1);
   SDValue ARMcc = N->getOperand(2);
   ARMCC::CondCodes CC =
-    (ARMCC::CondCodes)cast<ConstantSDNode>(ARMcc)->getZExtValue();
+      (ARMCC::CondCodes)cast<ConstantIntSDNode>(ARMcc)->getZExtValue();
 
   // BFI is only available on V6T2+.
   if (!Subtarget->isThumb1Only() && Subtarget->hasV6T2Ops()) {
@@ -11380,9 +11383,9 @@
   // (cmov F T ne CPSR (cmpz (cmov 0 1 CC CPSR Cmp) 0))
   // -> (cmov F T CC CPSR Cmp)
   if (CC == ARMCC::NE && LHS.getOpcode() == ARMISD::CMOV && LHS->hasOneUse()) {
-    auto *LHS0C = dyn_cast<ConstantSDNode>(LHS->getOperand(0));
-    auto *LHS1C = dyn_cast<ConstantSDNode>(LHS->getOperand(1));
-    auto *RHSC = dyn_cast<ConstantSDNode>(RHS);
+    auto *LHS0C = dyn_cast<ConstantIntSDNode>(LHS->getOperand(0));
+    auto *LHS1C = dyn_cast<ConstantIntSDNode>(LHS->getOperand(1));
+    auto *RHSC = dyn_cast<ConstantIntSDNode>(RHS);
     if ((LHS0C && LHS0C->getZExtValue() == 0) &&
         (LHS1C && LHS1C->getZExtValue() == 1) &&
         (RHSC && RHSC->getZExtValue() == 0)) {
@@ -11452,7 +11455,7 @@
     return PerformARMBUILD_VECTORCombine(N, DCI);
   case ISD::INTRINSIC_VOID:
   case ISD::INTRINSIC_W_CHAIN:
-    switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
+    switch (cast<ConstantIntSDNode>(N->getOperand(1))->getZExtValue()) {
     case Intrinsic::arm_neon_vld1:
     case Intrinsic::arm_neon_vld2:
     case Intrinsic::arm_neon_vld3:
@@ -11844,7 +11847,7 @@
   if (VT == MVT::i16 || ((VT == MVT::i8 || VT == MVT::i1) && isSEXTLoad)) {
     // AddressingMode 3
     Base = Ptr->getOperand(0);
-    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
+    if (auto *RHS = dyn_cast<ConstantIntSDNode>(Ptr->getOperand(1))) {
       int RHSC = (int)RHS->getZExtValue();
       if (RHSC < 0 && RHSC > -256) {
         assert(Ptr->getOpcode() == ISD::ADD);
@@ -11858,7 +11861,7 @@
     return true;
   } else if (VT == MVT::i32 || VT == MVT::i8 || VT == MVT::i1) {
     // AddressingMode 2
-    if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
+    if (auto *RHS = dyn_cast<ConstantIntSDNode>(Ptr->getOperand(1))) {
       int RHSC = (int)RHS->getZExtValue();
       if (RHSC < 0 && RHSC > -0x1000) {
         assert(Ptr->getOpcode() == ISD::ADD);
@@ -11901,7 +11904,7 @@
     return false;
 
   Base = Ptr->getOperand(0);
-  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Ptr->getOperand(1))) {
+  if (auto *RHS = dyn_cast<ConstantIntSDNode>(Ptr->getOperand(1))) {
     int RHSC = (int)RHS->getZExtValue();
     if (RHSC < 0 && RHSC > -0x100) { // 8 bits.
       assert(Ptr->getOpcode() == ISD::ADD);
@@ -11986,7 +11989,7 @@
     assert(Op->getValueType(0) == MVT::i32 && "Non-i32 post-inc op?!");
     if (Op->getOpcode() != ISD::ADD || !isNonExt)
       return false;
-    auto *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1));
+    auto *RHS = dyn_cast<ConstantIntSDNode>(Op->getOperand(1));
     if (!RHS || RHS->getZExtValue() != 4)
       return false;
     
@@ -12053,7 +12056,7 @@
     return;
   }
   case ISD::INTRINSIC_W_CHAIN: {
-    ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(1));
+    auto *CN = cast<ConstantIntSDNode>(Op->getOperand(1));
     Intrinsic::ID IntID = static_cast<Intrinsic::ID>(CN->getZExtValue());
     switch (IntID) {
     default: return;
@@ -12252,7 +12255,7 @@
   case 'j':
   case 'I': case 'J': case 'K': case 'L':
   case 'M': case 'N': case 'O':
-    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
+    auto *C = dyn_cast<ConstantIntSDNode>(Op);
     if (!C)
       return;
 
Index: llvm/lib/Target/ARM/ARMInstrInfo.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrInfo.td
+++ llvm/lib/Target/ARM/ARMInstrInfo.td
@@ -342,12 +342,12 @@
 //
 
 // imm_neg_XFORM - Return the negation of an i32 immediate value.
-def imm_neg_XFORM : SDNodeXForm<imm, [{
+def imm_neg_XFORM : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(-(int)N->getZExtValue(), SDLoc(N), MVT::i32);
 }]>;
 
 // imm_not_XFORM - Return the complement of a i32 immediate value.
-def imm_not_XFORM : SDNodeXForm<imm, [{
+def imm_not_XFORM : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32);
 }]>;
 
@@ -366,11 +366,11 @@
   if (N->getOperand(0).getOpcode() != ISD::SHL)
     return false;
 
-  auto *ShiftVal = dyn_cast<ConstantSDNode>(N->getOperand(1));
+  auto *ShiftVal = dyn_cast<ConstantIntSDNode>(N->getOperand(1));
   if (!ShiftVal || ShiftVal->getZExtValue() != 16)
     return false;
 
-  ShiftVal = dyn_cast<ConstantSDNode>(N->getOperand(0)->getOperand(1));
+  ShiftVal = dyn_cast<ConstantIntSDNode>(N->getOperand(0)->getOperand(1));
   if (!ShiftVal || ShiftVal->getZExtValue() != 16)
     return false;
 
@@ -378,7 +378,7 @@
 }]>;
 
 /// Split a 32-bit immediate into two 16 bit parts.
-def hi16 : SDNodeXForm<imm, [{
+def hi16 : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant((uint32_t)N->getZExtValue() >> 16, SDLoc(N),
                                    MVT::i32);
 }]>;
@@ -518,7 +518,7 @@
 }
 
 // rot_imm: An integer that encodes a rotate amount. Must be 8, 16, or 24.
-def rot_imm_XFORM: SDNodeXForm<imm, [{
+def rot_imm_XFORM: ConstIntSDNodeXForm<[{
   switch (N->getZExtValue()){
   default: llvm_unreachable(nullptr);
   case 0:  return CurDAG->getTargetConstant(0, SDLoc(N), MVT::i32);
@@ -801,7 +801,7 @@
   let ParserMatchClass = BitfieldAsmOperand;
 }
 
-def imm1_32_XFORM: SDNodeXForm<imm, [{
+def imm1_32_XFORM: ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
                                    MVT::i32);
 }]>;
@@ -812,7 +812,7 @@
   let ParserMatchClass = Imm1_32AsmOperand;
 }
 
-def imm1_16_XFORM: SDNodeXForm<imm, [{
+def imm1_16_XFORM: ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant((int)N->getZExtValue() - 1, SDLoc(N),
                                    MVT::i32);
 }]>;
Index: llvm/lib/Target/ARM/ARMInstrNEON.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrNEON.td
+++ llvm/lib/Target/ARM/ARMInstrNEON.td
@@ -588,14 +588,14 @@
 def NEONvmullu    : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
 
 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
-  ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
+  auto *ConstVal = cast<ConstantIntSDNode>(N->getOperand(0));
   unsigned EltBits = 0;
   uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
   return (EltBits == 32 && EltVal == 0);
 }]>;
 
 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
-  ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
+  auto *ConstVal = cast<ConstantIntSDNode>(N->getOperand(0));
   unsigned EltBits = 0;
   uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
   return (EltBits == 8 && EltVal == 0xff);
@@ -2386,42 +2386,42 @@
 //===----------------------------------------------------------------------===//
 
 // Extract D sub-registers of Q registers.
-def DSubReg_i8_reg  : SDNodeXForm<imm, [{
+def DSubReg_i8_reg  : ConstIntSDNodeXForm<[{
   assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
   return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, SDLoc(N),
                                    MVT::i32);
 }]>;
-def DSubReg_i16_reg : SDNodeXForm<imm, [{
+def DSubReg_i16_reg : ConstIntSDNodeXForm<[{
   assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
   return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, SDLoc(N),
                                    MVT::i32);
 }]>;
-def DSubReg_i32_reg : SDNodeXForm<imm, [{
+def DSubReg_i32_reg : ConstIntSDNodeXForm<[{
   assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
   return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, SDLoc(N),
                                    MVT::i32);
 }]>;
-def DSubReg_f64_reg : SDNodeXForm<imm, [{
+def DSubReg_f64_reg : ConstIntSDNodeXForm<[{
   assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
   return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), SDLoc(N),
                                    MVT::i32);
 }]>;
 
 // Extract S sub-registers of Q/D registers.
-def SSubReg_f32_reg : SDNodeXForm<imm, [{
+def SSubReg_f32_reg : ConstIntSDNodeXForm<[{
   assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
   return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), SDLoc(N),
                                    MVT::i32);
 }]>;
 
 // Translate lane numbers from Q registers to D subregs.
-def SubReg_i8_lane  : SDNodeXForm<imm, [{
+def SubReg_i8_lane  : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(N->getZExtValue() & 7, SDLoc(N), MVT::i32);
 }]>;
-def SubReg_i16_lane : SDNodeXForm<imm, [{
+def SubReg_i16_lane : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(N->getZExtValue() & 3, SDLoc(N), MVT::i32);
 }]>;
-def SubReg_i32_lane : SDNodeXForm<imm, [{
+def SubReg_i32_lane : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(N->getZExtValue() & 1, SDLoc(N), MVT::i32);
 }]>;
 
Index: llvm/lib/Target/ARM/ARMInstrThumb.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrThumb.td
+++ llvm/lib/Target/ARM/ARMInstrThumb.td
@@ -15,7 +15,7 @@
 // Thumb specific DAG Nodes.
 //
 
-def imm_sr_XFORM: SDNodeXForm<imm, [{
+def imm_sr_XFORM: ConstIntSDNodeXForm<[{
   unsigned Imm = N->getZExtValue();
   return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), SDLoc(N), MVT::i32);
 }]>;
@@ -27,7 +27,7 @@
   let ParserMatchClass = ThumbSRImmAsmOperand;
 }
 
-def imm_comp_XFORM : SDNodeXForm<imm, [{
+def imm_comp_XFORM : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), SDLoc(N),
                                    MVT::i32);
 }]>;
@@ -56,12 +56,12 @@
   return ARM_AM::isThumbImmShiftedVal((unsigned)Imm);
 }]>;
 
-def thumb_immshifted_val : SDNodeXForm<imm, [{
+def thumb_immshifted_val : ConstIntSDNodeXForm<[{
   unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
   return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);
 }]>;
 
-def thumb_immshifted_shamt : SDNodeXForm<imm, [{
+def thumb_immshifted_shamt : ConstIntSDNodeXForm<[{
   unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
   return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);
 }]>;
@@ -70,7 +70,7 @@
   return Imm >= 256 && Imm < 511;
 }]>;
 
-def thumb_imm256_510_addend : SDNodeXForm<imm, [{
+def thumb_imm256_510_addend : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(N->getZExtValue() - 255, SDLoc(N), MVT::i32);
 }]>;
 
Index: llvm/lib/Target/ARM/ARMInstrThumb2.td
===================================================================
--- llvm/lib/Target/ARM/ARMInstrThumb2.td
+++ llvm/lib/Target/ARM/ARMInstrThumb2.td
@@ -53,13 +53,13 @@
 }
 
 // t2_so_imm_not_XFORM - Return the complement of a t2_so_imm value
-def t2_so_imm_not_XFORM : SDNodeXForm<imm, [{
+def t2_so_imm_not_XFORM : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), SDLoc(N),
                                    MVT::i32);
 }]>;
 
 // t2_so_imm_neg_XFORM - Return the negation of a t2_so_imm value
-def t2_so_imm_neg_XFORM : SDNodeXForm<imm, [{
+def t2_so_imm_neg_XFORM : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(-((int)N->getZExtValue()), SDLoc(N),
                                    MVT::i32);
 }]>;
@@ -67,7 +67,7 @@
 // so_imm_notSext_XFORM - Return a so_imm value packed into the format
 // described for so_imm_notSext def below, with sign extension from 16
 // bits.
-def t2_so_imm_notSext16_XFORM : SDNodeXForm<imm, [{
+def t2_so_imm_notSext16_XFORM : ConstIntSDNodeXForm<[{
   APInt apIntN = N->getAPIntValue();
   unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
   return CurDAG->getTargetConstant(~N16bitSignExt, SDLoc(N), MVT::i32);
@@ -100,7 +100,9 @@
 // t2_so_imm_notSext - match an immediate that is a complement of a t2_so_imm
 // if the upper 16 bits are zero.
 def t2_so_imm_notSext : Operand<i32>, PatLeaf<(imm), [{
-    APInt apIntN = N->getAPIntValue();
+    auto *CN = dyn_cast<ConstantIntSDNode>(N);
+    if (!CN) return false;
+    APInt apIntN = CN->getAPIntValue();
     if (!apIntN.isIntN(16)) return false;
     unsigned N16bitSignExt = apIntN.trunc(16).sext(32).getZExtValue();
     return ARM_AM::getT2SOImmVal(~N16bitSignExt) != -1;
Index: llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
+++ llvm/lib/Target/ARM/ARMSelectionDAGInfo.cpp
@@ -51,7 +51,7 @@
     break;
   case RTLIB::MEMSET: 
     AEABILibcall = AEABI_MEMSET;
-    if (ConstantSDNode *ConstantSrc = dyn_cast<ConstantSDNode>(Src))
+    if (auto *ConstantSrc = dyn_cast<ConstantIntSDNode>(Src))
       if (ConstantSrc->getZExtValue() == 0)
         AEABILibcall = AEABI_MEMCLR;
     break;
@@ -137,7 +137,7 @@
     return SDValue();
   // This requires the copy size to be a constant, preferably
   // within a subtarget-specific limit.
-  ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
+  auto *ConstantSize = dyn_cast<ConstantIntSDNode>(Size);
   if (!ConstantSize)
     return EmitSpecializedLibcall(DAG, dl, Chain, Dst, Src, Size, Align,
                                   RTLIB::MEMCPY);
Index: llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
+++ llvm/lib/Target/BPF/BPFISelDAGToDAG.cpp
@@ -70,7 +70,7 @@
 
   // Addresses of the form Addr+const or Addr|const
   if (CurDAG->isBaseWithConstantOffset(Addr)) {
-    ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
+    auto *CN = dyn_cast<ConstantIntSDNode>(Addr.getOperand(1));
     if (isInt<32>(CN->getSExtValue())) {
 
       // If the first operand is a FI, get the TargetFI Node
@@ -98,7 +98,7 @@
     return false;
 
   // Addresses of the form Addr+const or Addr|const
-  ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
+  auto *CN = dyn_cast<ConstantIntSDNode>(Addr.getOperand(1));
   if (isInt<32>(CN->getSExtValue())) {
 
     // If the first operand is a FI, get the TargetFI Node
@@ -143,7 +143,8 @@
     break;
   }
   case ISD::INTRINSIC_W_CHAIN: {
-    unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
+    unsigned IntNo =
+        cast<ConstantIntSDNode>(Node->getOperand(1))->getZExtValue();
     switch (IntNo) {
     case Intrinsic::bpf_load_byte:
     case Intrinsic::bpf_load_half:
Index: llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
+++ llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
@@ -260,7 +260,7 @@
   SDValue Chain = LD->getChain();
   SDValue Base = LD->getBasePtr();
   SDValue Offset = LD->getOffset();
-  int32_t Inc = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
+  int32_t Inc = cast<ConstantIntSDNode>(Offset.getNode())->getSExtValue();
   EVT LoadedVT = LD->getMemoryVT();
   unsigned Opcode = 0;
 
@@ -380,7 +380,7 @@
     return nullptr;
 
   SDLoc dl(IntN);
-  unsigned IntNo = cast<ConstantSDNode>(IntN->getOperand(1))->getZExtValue();
+  unsigned IntNo = cast<ConstantIntSDNode>(IntN->getOperand(1))->getZExtValue();
 
   static std::map<unsigned,unsigned> LoadPciMap = {
     { Intrinsic::hexagon_circ_ldb,  Hexagon::L2_loadrb_pci  },
@@ -397,7 +397,7 @@
     EVT ValTy = (IntNo == Intrinsic::hexagon_circ_ldd) ? MVT::i64 : MVT::i32;
     EVT RTys[] = { ValTy, MVT::i32, MVT::Other };
     // Operands: { Base, Increment, Modifier, Chain }
-    auto Inc = cast<ConstantSDNode>(IntN->getOperand(5));
+    auto Inc = cast<ConstantIntSDNode>(IntN->getOperand(5));
     SDValue I = CurDAG->getTargetConstant(Inc->getSExtValue(), dl, MVT::i32);
     MachineSDNode *Res = CurDAG->getMachineNode(FLC->second, dl, RTys,
           { IntN->getOperand(2), I, SDValue(Mod,0), IntN->getOperand(0) });
@@ -493,22 +493,22 @@
   // can provide an address of an unsigned variable to store the result of
   // a sign-extending intrinsic into (or the other way around).
   ISD::LoadExtType IntExt;
-  switch (cast<ConstantSDNode>(C->getOperand(1))->getZExtValue()) {
-    case Intrinsic::hexagon_brev_ldub:
-    case Intrinsic::hexagon_brev_lduh:
-    case Intrinsic::hexagon_circ_ldub:
-    case Intrinsic::hexagon_circ_lduh:
-      IntExt = ISD::ZEXTLOAD;
-      break;
-    case Intrinsic::hexagon_brev_ldw:
-    case Intrinsic::hexagon_brev_ldd:
-    case Intrinsic::hexagon_circ_ldw:
-    case Intrinsic::hexagon_circ_ldd:
-      IntExt = ISD::NON_EXTLOAD;
-      break;
-    default:
-      IntExt = ISD::SEXTLOAD;
-      break;
+  switch (cast<ConstantIntSDNode>(C->getOperand(1))->getZExtValue()) {
+  case Intrinsic::hexagon_brev_ldub:
+  case Intrinsic::hexagon_brev_lduh:
+  case Intrinsic::hexagon_circ_ldub:
+  case Intrinsic::hexagon_circ_lduh:
+    IntExt = ISD::ZEXTLOAD;
+    break;
+  case Intrinsic::hexagon_brev_ldw:
+  case Intrinsic::hexagon_brev_ldd:
+  case Intrinsic::hexagon_circ_ldw:
+  case Intrinsic::hexagon_circ_ldd:
+    IntExt = ISD::NON_EXTLOAD;
+    break;
+  default:
+    IntExt = ISD::SEXTLOAD;
+    break;
   }
   if (N->getExtensionType() != IntExt)
     return false;
@@ -557,7 +557,7 @@
   SDValue Offset = ST->getOffset();
   SDValue Value = ST->getValue();
   // Get the constant value.
-  int32_t Inc = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
+  int32_t Inc = cast<ConstantIntSDNode>(Offset.getNode())->getSExtValue();
   EVT StoredVT = ST->getMemoryVT();
   EVT ValueVT = Value.getValueType();
 
@@ -750,13 +750,13 @@
     return Default();
 
   // RHS is const.
-  int32_t ShlConst = cast<ConstantSDNode>(Shl_1)->getSExtValue();
+  int32_t ShlConst = cast<ConstantIntSDNode>(Shl_1)->getSExtValue();
 
   if (Shl_0.getOpcode() == ISD::MUL) {
     SDValue Mul_0 = Shl_0.getOperand(0); // Val
     SDValue Mul_1 = Shl_0.getOperand(1); // Const
     // RHS of mul is const.
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Mul_1)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Mul_1)) {
       int32_t ValConst = C->getSExtValue() << ShlConst;
       if (isInt<9>(ValConst)) {
         SDValue Val = CurDAG->getTargetConstant(ValConst, dl, MVT::i32);
@@ -772,12 +772,12 @@
   if (Shl_0.getOpcode() == ISD::SUB) {
     SDValue Sub_0 = Shl_0.getOperand(0); // Const 0
     SDValue Sub_1 = Shl_0.getOperand(1); // Val
-    if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(Sub_0)) {
+    if (auto *C1 = dyn_cast<ConstantIntSDNode>(Sub_0)) {
       if (C1->getSExtValue() != 0 || Sub_1.getOpcode() != ISD::SHL)
         return Default();
       SDValue Shl2_0 = Sub_1.getOperand(0); // Val
       SDValue Shl2_1 = Sub_1.getOperand(1); // Const
-      if (ConstantSDNode *C2 = dyn_cast<ConstantSDNode>(Shl2_1)) {
+      if (auto *C2 = dyn_cast<ConstantIntSDNode>(Shl2_1)) {
         int32_t ValConst = 1 << (ShlConst + C2->getSExtValue());
         if (isInt<9>(-ValConst)) {
           SDValue Val = CurDAG->getTargetConstant(-ValConst, dl, MVT::i32);
@@ -842,7 +842,7 @@
 
   SDNode *Int = N->getOperand(0).getNode();
   if ((Int->getOpcode() == ISD::INTRINSIC_WO_CHAIN)) {
-    unsigned ID = cast<ConstantSDNode>(Int->getOperand(0))->getZExtValue();
+    unsigned ID = cast<ConstantIntSDNode>(Int->getOperand(0))->getZExtValue();
     if (doesIntrinsicReturnPredicate(ID)) {
       // Now we need to differentiate target data types.
       if (N->getValueType(0) == MVT::i64) {
@@ -886,7 +886,7 @@
 }
 
 void HexagonDAGToDAGISel::SelectIntrinsicWOChain(SDNode *N) {
-  unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
+  unsigned IID = cast<ConstantIntSDNode>(N->getOperand(0))->getZExtValue();
   unsigned Bits;
   switch (IID) {
   case Intrinsic::hexagon_S2_vsplatrb:
@@ -938,10 +938,10 @@
 //
 void HexagonDAGToDAGISel::SelectConstant(SDNode *N) {
   if (N->getValueType(0) == MVT::i1) {
-    assert(!(cast<ConstantSDNode>(N)->getZExtValue() >> 1));
-    unsigned Opc = (cast<ConstantSDNode>(N)->getSExtValue() != 0)
-                      ? Hexagon::PS_true
-                      : Hexagon::PS_false;
+    assert(!(cast<ConstantIntSDNode>(N)->getZExtValue() >> 1));
+    unsigned Opc = (cast<ConstantIntSDNode>(N)->getSExtValue() != 0)
+                       ? Hexagon::PS_true
+                       : Hexagon::PS_false;
     ReplaceNode(N, CurDAG->getMachineNode(Opc, SDLoc(N), MVT::i1));
     return;
   }
@@ -1003,7 +1003,7 @@
   int64_t Val = 0;
   if (Opc != ISD::FABS && Opc != ISD::FNEG) {
     if (N->getOperand(1).getOpcode() == ISD::Constant)
-      Val = cast<ConstantSDNode>((N)->getOperand(1))->getSExtValue();
+      Val = cast<ConstantIntSDNode>((N)->getOperand(1))->getSExtValue();
     else {
       SelectCode(N);
       return;
@@ -1274,8 +1274,8 @@
     if (I->getOpcode() != ISD::OR)
       continue;
 
-    auto IsZero = [] (const SDValue &V) -> bool {
-      if (ConstantSDNode *SC = dyn_cast<ConstantSDNode>(V.getNode()))
+    auto IsZero = [](const SDValue &V) -> bool {
+      if (auto *SC = dyn_cast<ConstantIntSDNode>(V.getNode()))
         return SC->isNullValue();
       return false;
     };
@@ -1335,14 +1335,14 @@
     if (T1.getOpcode() != ISD::SHL)
       continue;
     SDValue C = T1.getOperand(1);
-    ConstantSDNode *CN = dyn_cast<ConstantSDNode>(C.getNode());
+    auto *CN = dyn_cast<ConstantIntSDNode>(C.getNode());
     if (CN == nullptr)
       continue;
     unsigned CV = CN->getZExtValue();
     if (CV > 2)
       continue;
     // T2 needs to match e, where e = (shl d c) for some d.
-    ConstantSDNode *EN = dyn_cast<ConstantSDNode>(T2.getNode());
+    auto *EN = dyn_cast<ConstantIntSDNode>(T2.getNode());
     if (EN == nullptr)
       continue;
     unsigned EV = EN->getZExtValue();
@@ -1419,7 +1419,7 @@
       return false;
     if (!UseGP && GAOpc != HexagonISD::CONST32)
       return false;
-    if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(N1)) {
+    if (auto *Const = dyn_cast<ConstantIntSDNode>(N1)) {
       SDValue Addr = N0.getOperand(0);
       if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Addr)) {
         if (GA->getOpcode() == ISD::TargetGlobalAddress) {
@@ -1478,13 +1478,13 @@
   case ISD::AND: {
     // Check if this is an AND with "FromBits" of lower bits set to 1.
     uint64_t FromMask = (1 << FromBits) - 1;
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(0))) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Val.getOperand(0))) {
       if (C->getZExtValue() == FromMask) {
         Src = Val.getOperand(1);
         return true;
       }
     }
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(1))) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Val.getOperand(1))) {
       if (C->getZExtValue() == FromMask) {
         Src = Val.getOperand(0);
         return true;
@@ -1496,13 +1496,13 @@
   case ISD::XOR: {
     // OR/XOR with the lower "FromBits" bits set to 0.
     uint64_t FromMask = (1 << FromBits) - 1;
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(0))) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Val.getOperand(0))) {
       if ((C->getZExtValue() & FromMask) == 0) {
         Src = Val.getOperand(1);
         return true;
       }
     }
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(1))) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Val.getOperand(1))) {
       if ((C->getZExtValue() & FromMask) == 0) {
         Src = Val.getOperand(0);
         return true;
@@ -1518,7 +1518,7 @@
 
 bool HexagonDAGToDAGISel::orIsAdd(const SDNode *N) const {
   assert(N->getOpcode() == ISD::OR);
-  auto *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
+  auto *C = dyn_cast<ConstantIntSDNode>(N->getOperand(1));
   assert(C);
 
   // Detect when "or" is used to add an offset to a stack object.
@@ -1549,7 +1549,7 @@
     case ISD::SHL:
       // We only handle constant shifts because these can be easily flattened
       // into multiplications by 2^Op1.
-      return isa<ConstantSDNode>(N->getOperand(1).getNode());
+      return isa<ConstantIntSDNode>(N->getOperand(1).getNode());
     default:
       return false;
   }
@@ -1632,12 +1632,12 @@
   }
 
   void push(WeightedLeaf L, bool SeparateConst=true) {
-    if (!HaveConst && SeparateConst && isa<ConstantSDNode>(L.Value)) {
+    if (!HaveConst && SeparateConst && isa<ConstantIntSDNode>(L.Value)) {
       if (Opcode == ISD::MUL &&
-          cast<ConstantSDNode>(L.Value)->getSExtValue() == 1)
+          cast<ConstantIntSDNode>(L.Value)->getSExtValue() == 1)
         return;
       if (Opcode == ISD::ADD &&
-          cast<ConstantSDNode>(L.Value)->getSExtValue() == 0)
+          cast<ConstantIntSDNode>(L.Value)->getSExtValue() == 0)
         return;
 
       HaveConst = true;
@@ -1674,7 +1674,7 @@
     const WeightedLeaf &L = Q[Pos];
     const SDValue &Val = L.Value;
     if (Val.getOpcode() != ISD::SHL ||
-        !isa<ConstantSDNode>(Val.getOperand(1)) ||
+        !isa<ConstantIntSDNode>(Val.getOperand(1)) ||
         Val.getConstantOperandVal(1) > MaxAmount)
       continue;
     if (!Result.Value.getNode() || Result.Weight > L.Weight ||
@@ -1701,7 +1701,7 @@
     const WeightedLeaf &L = Q[Pos];
     const SDValue &Val = L.Value;
     if (Val.getOpcode() != ISD::MUL ||
-        !isa<ConstantSDNode>(Val.getOperand(1)) ||
+        !isa<ConstantIntSDNode>(Val.getOperand(1)) ||
         Val.getConstantOperandVal(1) > 127)
       continue;
     if (!Result.Value.getNode() || Result.Weight > L.Weight ||
@@ -1731,7 +1731,7 @@
   if (Val.getOpcode() == ISD::MUL) {
     unsigned MaxFactor = 0;
     for (int i = 0; i < 2; ++i) {
-      ConstantSDNode *C = dyn_cast<ConstantSDNode>(Val.getOperand(i));
+      auto *C = dyn_cast<ConstantIntSDNode>(Val.getOperand(i));
       if (!C)
         continue;
       const APInt &CInt = C->getAPIntValue();
@@ -1741,7 +1741,7 @@
     return MaxFactor;
   }
   if (Val.getOpcode() == ISD::SHL) {
-    if (!isa<ConstantSDNode>(Val.getOperand(1).getNode()))
+    if (!isa<ConstantIntSDNode>(Val.getOperand(1).getNode()))
       return 0;
     return (unsigned) Val.getConstantOperandVal(1);
   }
@@ -1754,7 +1754,7 @@
   if (V.getOpcode() == ISD::MUL) {
     SDValue Ops[] = { V.getOperand(0), V.getOperand(1) };
     for (int i = 0; i < 2; ++i)
-      if (isa<ConstantSDNode>(Ops[i].getNode()) &&
+      if (isa<ConstantIntSDNode>(Ops[i].getNode()) &&
           V.getConstantOperandVal(i) % (1ULL << Amount) == 0) {
         uint64_t NewConst = V.getConstantOperandVal(i) >> Amount;
         return (NewConst == 1);
@@ -1770,7 +1770,7 @@
   SDValue Ops[] = { V.getOperand(0), V.getOperand(1) };
   if (V.getOpcode() == ISD::MUL) {
     for (int i=0; i < 2; ++i) {
-      if (isa<ConstantSDNode>(Ops[i].getNode()) &&
+      if (isa<ConstantIntSDNode>(Ops[i].getNode()) &&
           V.getConstantOperandVal(i) % ((uint64_t)1 << Power) == 0) {
         uint64_t NewConst = V.getConstantOperandVal(i) >> Power;
         if (NewConst == 1)
@@ -2019,7 +2019,7 @@
       GA.Value.hasOneUse() && N->use_size() < 3) {
     GlobalAddressSDNode *GANode =
       cast<GlobalAddressSDNode>(GA.Value.getOperand(0));
-    ConstantSDNode *Offset = cast<ConstantSDNode>(Leaves.top().Value);
+    auto *Offset = cast<ConstantIntSDNode>(Leaves.top().Value);
 
     if (getUsesInFunction(GANode->getGlobal()) == 1 && Offset->hasOneUse() &&
         getTargetLowering()->isOffsetFoldingLegal(GANode)) {
@@ -2100,8 +2100,8 @@
       return balanceSubTree(N, TopLevel);
     }
 
-    ConstantSDNode *V0C = dyn_cast<ConstantSDNode>(V0);
-    ConstantSDNode *V1C = dyn_cast<ConstantSDNode>(V1);
+    auto *V0C = dyn_cast<ConstantIntSDNode>(V0);
+    auto *V1C = dyn_cast<ConstantIntSDNode>(V1);
     EVT VT = N->getValueType(0);
     SDValue NewNode;
 
@@ -2143,7 +2143,7 @@
 
   // Restore SHL if we earlier converted it to a MUL
   if (NewRoot.getOpcode() == ISD::MUL) {
-    ConstantSDNode *V1C = dyn_cast<ConstantSDNode>(NewRoot.getOperand(1));
+    auto *V1C = dyn_cast<ConstantIntSDNode>(NewRoot.getOperand(1));
     if (V1C && V1C->getAPIntValue().isPowerOf2()) {
       EVT VT = NewRoot.getValueType();
       SDValue V0 = NewRoot.getOperand(0);
Index: llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
===================================================================
--- llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -929,7 +929,7 @@
     Base = Ptr->getOperand(0);
     Offset = Ptr->getOperand(1);
     // Ensure that Offset is a constant.
-    return isa<ConstantSDNode>(Offset);
+    return isa<ConstantIntSDNode>(Offset);
   }
 
   return false;
@@ -961,7 +961,8 @@
   bool isLegal = getIndexedAddressParts(Op, VT, Base, Offset, IsInc, DAG);
   if (isLegal) {
     auto &HII = *Subtarget.getInstrInfo();
-    int32_t OffsetVal = cast<ConstantSDNode>(Offset.getNode())->getSExtValue();
+    int32_t OffsetVal =
+        cast<ConstantIntSDNode>(Offset.getNode())->getSExtValue();
     if (HII.isValidAutoIncImm(VT, OffsetVal)) {
       AM = IsInc ? ISD::POST_INC : ISD::POST_DEC;
       return true;
@@ -986,7 +987,7 @@
         if (FuncInfo.hasClobberLR())
           break;
         unsigned Flags =
-          cast<ConstantSDNode>(Node->getOperand(i))->getZExtValue();
+            cast<ConstantIntSDNode>(Node->getOperand(i))->getZExtValue();
         unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
         ++i;  // Skip the ID value.
 
@@ -1038,7 +1039,7 @@
 SDValue HexagonTargetLowering::LowerINTRINSIC_VOID(SDValue Op,
       SelectionDAG &DAG) const {
   SDValue Chain = Op.getOperand(0);
-  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
+  unsigned IntNo = cast<ConstantIntSDNode>(Op.getOperand(1))->getZExtValue();
   // Lower the hexagon_prefetch builtin to DCFETCH, as above.
   if (IntNo == Intrinsic::hexagon_prefetch) {
     SDValue Addr = Op.getOperand(2);
@@ -1057,7 +1058,7 @@
   SDValue Align = Op.getOperand(2);
   SDLoc dl(Op);
 
-  ConstantSDNode *AlignConst = dyn_cast<ConstantSDNode>(Align);
+  auto *AlignConst = dyn_cast<ConstantIntSDNode>(Align);
   assert(AlignConst && "Non-constant Align in LowerDYNAMIC_STACKALLOC");
 
   unsigned A = AlignConst->getSExtValue();
@@ -1257,8 +1258,8 @@
 SDValue HexagonTargetLowering::LowerCTPOP(SDValue Op, SelectionDAG &DAG) const {
   SDLoc dl(Op);
   SDValue InpVal = Op.getOperand(0);
-  if (isa<ConstantSDNode>(InpVal)) {
-    uint64_t V = cast<ConstantSDNode>(InpVal)->getZExtValue();
+  if (isa<ConstantIntSDNode>(InpVal)) {
+    uint64_t V = cast<ConstantIntSDNode>(InpVal)->getZExtValue();
     return DAG.getTargetConstant(countPopulation(V), dl, MVT::i64);
   }
   SDValue PopOut = DAG.getNode(HexagonISD::POPCOUNT, dl, MVT::i32, InpVal);
@@ -1297,7 +1298,7 @@
   if ((CC == ISD::SETEQ || CC == ISD::SETNE) &&
       (RHSVT == MVT::i8 || RHSVT == MVT::i16) &&
       (LHSVT == MVT::i8 || LHSVT == MVT::i16)) {
-    ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS);
+    auto *C = dyn_cast<ConstantIntSDNode>(RHS);
     if (C && C->getAPIntValue().isNegative()) {
       LHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, LHS);
       RHS = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i32, RHS);
@@ -1456,7 +1457,7 @@
 
   EVT VT = Op.getValueType();
   SDLoc dl(Op);
-  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned Depth = cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
   if (Depth) {
     SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
     SDValue Offset = DAG.getConstant(4, dl, MVT::i32);
@@ -1478,7 +1479,7 @@
 
   EVT VT = Op.getValueType();
   SDLoc dl(Op);
-  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned Depth = cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
   SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
                                          HRI.getFrameRegister(), VT);
   while (Depth--)
@@ -2372,7 +2373,7 @@
     // (and probably will turn into a SCALAR_TO_VECTOR once legalization
     // reaches it).
     if (Lane == 0 && V1.getOpcode() == ISD::BUILD_VECTOR &&
-        !isa<ConstantSDNode>(V1.getOperand(0))) {
+        !isa<ConstantIntSDNode>(V1.getOperand(0))) {
       bool IsScalarToVector = true;
       for (unsigned i = 1, e = V1.getNumOperands(); i != e; ++i) {
         if (!V1.getOperand(i).isUndef()) {
@@ -2528,8 +2529,8 @@
     if (V1.isUndef())
       V1 = DAG.getConstant(0, dl, MVT::i32);
 
-    ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(V0);
-    ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(V1);
+    auto *C0 = dyn_cast<ConstantIntSDNode>(V0);
+    auto *C1 = dyn_cast<ConstantIntSDNode>(V1);
     // If the element isn't a constant, it is in a register:
     // generate a COMBINE Register Register instruction.
     if (!C0 || !C1)
@@ -2547,7 +2548,7 @@
     for (unsigned i = 0, e = NElts; i != e; ++i) {
       if (BVN->getOperand(i).isUndef())
         continue;
-      ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(BVN->getOperand(i));
+      auto *Cst = dyn_cast<ConstantIntSDNode>(BVN->getOperand(i));
       // If the element isn't a constant, it is in a register:
       // generate a S2_packhl instruction.
       if (!Cst) {
@@ -2577,7 +2578,7 @@
       continue;
 
     int64_t Val = 0;
-    if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Operand))
+    if (auto *Cst = dyn_cast<ConstantIntSDNode>(Operand))
       Val = Cst->getSExtValue();
     else
       HasNonConstantElements = true;
@@ -2607,7 +2608,7 @@
       // is Big Endian.
       unsigned OpIdx = NElts - i - 1;
       SDValue Operand = BVN->getOperand(OpIdx);
-      if (isa<ConstantSDNode>(Operand))
+      if (isa<ConstantIntSDNode>(Operand))
         // This operand is already in ConstVal.
         continue;
 
@@ -2718,7 +2719,7 @@
       !(VT.isByteSized() && OpSize == 2 * VectorSizeInBits))
     return SDValue();
 
-  ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op.getOperand(1));
+  auto *Cst = dyn_cast<ConstantIntSDNode>(Op.getOperand(1));
   if (!Cst)
     return SDValue();
   unsigned Val = Cst->getZExtValue();
@@ -2760,12 +2761,12 @@
                                   EltSize : VTN * EltSize, dl, MVT::i64);
 
   // Constant element number.
-  if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Idx)) {
+  if (auto *CI = dyn_cast<ConstantIntSDNode>(Idx)) {
     uint64_t X = CI->getZExtValue();
     SDValue Offset = DAG.getConstant(X * EltSize, dl, MVT::i32);
     const SDValue Ops[] = {Vec, Width, Offset};
 
-    ConstantSDNode *CW = dyn_cast<ConstantSDNode>(Width);
+    auto *CW = dyn_cast<ConstantIntSDNode>(Width);
     assert(CW && "Non constant width in LowerEXTRACT_VECTOR");
 
     SDValue N;
@@ -2835,7 +2836,7 @@
   SDValue Width = DAG.getConstant(Op.getOpcode() == ISD::INSERT_VECTOR_ELT ?
                                   EltSize : VTN * EltSize, dl, MVT::i64);
 
-  if (ConstantSDNode *C = cast<ConstantSDNode>(Idx)) {
+  if (auto *C = cast<ConstantIntSDNode>(Idx)) {
     SDValue Offset = DAG.getConstant(C->getSExtValue() * EltSize, dl, MVT::i32);
     const SDValue Ops[] = {Vec, Val, Width, Offset};
 
@@ -3199,7 +3200,7 @@
 
 // Return true when the given node fits in a positive half word.
 bool llvm::isPositiveHalfWord(SDNode *N) {
-  ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N);
+  auto *CN = dyn_cast<ConstantIntSDNode>(N);
   if (CN && CN->getSExtValue() > 0 && isInt<16>(CN->getSExtValue()))
     return true;
 
Index: llvm/lib/Target/Hexagon/HexagonInstrInfo.td
===================================================================
--- llvm/lib/Target/Hexagon/HexagonInstrInfo.td
+++ llvm/lib/Target/Hexagon/HexagonInstrInfo.td
@@ -36,28 +36,28 @@
     (or node:$Addr, node:$off), [{ return orIsAdd(N); }]>;
 
 // SDNode for converting immediate C to C-1.
-def DEC_CONST_SIGNED : SDNodeXForm<imm, [{
+def DEC_CONST_SIGNED : ConstIntSDNodeXForm<[{
    // Return the byte immediate const-1 as an SDNode.
    int32_t imm = N->getSExtValue();
    return XformSToSM1Imm(imm, SDLoc(N));
 }]>;
 
 // SDNode for converting immediate C to C-2.
-def DEC2_CONST_SIGNED : SDNodeXForm<imm, [{
+def DEC2_CONST_SIGNED : ConstIntSDNodeXForm<[{
    // Return the byte immediate const-2 as an SDNode.
    int32_t imm = N->getSExtValue();
    return XformSToSM2Imm(imm, SDLoc(N));
 }]>;
 
 // SDNode for converting immediate C to C-3.
-def DEC3_CONST_SIGNED : SDNodeXForm<imm, [{
+def DEC3_CONST_SIGNED : ConstIntSDNodeXForm<[{
    // Return the byte immediate const-3 as an SDNode.
    int32_t imm = N->getSExtValue();
    return XformSToSM3Imm(imm, SDLoc(N));
 }]>;
 
 // SDNode for converting immediate C to C-1.
-def DEC_CONST_UNSIGNED : SDNodeXForm<imm, [{
+def DEC_CONST_UNSIGNED : ConstIntSDNodeXForm<[{
    // Return the byte immediate const-1 as an SDNode.
    uint32_t imm = N->getZExtValue();
    return XformUToUM1Imm(imm, SDLoc(N));
Index: llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td
===================================================================
--- llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td
+++ llvm/lib/Target/Hexagon/HexagonInstrInfoV4.td
@@ -53,7 +53,7 @@
   def A4_ext_g : T_Immext<globaladdress>;
 }
 
-def BITPOS32 : SDNodeXForm<imm, [{
+def BITPOS32 : ConstIntSDNodeXForm<[{
    // Return the bit position we will set [0-31].
    // As an SDNode.
    int32_t imm = N->getSExtValue();
@@ -1052,7 +1052,7 @@
 def s30_2ProperPred  : ImmLeaf<i32, [{
   return isShiftedInt<30,2>(Imm) && !isShiftedInt<29,3>(Imm);
 }]>;
-def RoundTo8 : SDNodeXForm<imm, [{
+def RoundTo8 : ConstIntSDNodeXForm<[{
    int32_t Imm = N->getSExtValue();
    return CurDAG->getTargetConstant(Imm & -8, SDLoc(N), MVT::i32);
 }]>;
@@ -1187,21 +1187,21 @@
   defm S4_storeiri : ST_Imm<"memw", "STriw", u6_2Imm, 0b10>;
 }
 
-def IMM_BYTE : SDNodeXForm<imm, [{
+def IMM_BYTE : ConstIntSDNodeXForm<[{
   // -1 etc is  represented as 255 etc
   // assigning to a byte restores our desired signed value.
   int8_t imm = N->getSExtValue();
   return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32);
 }]>;
 
-def IMM_HALF : SDNodeXForm<imm, [{
+def IMM_HALF : ConstIntSDNodeXForm<[{
   // -1 etc is  represented as 65535 etc
   // assigning to a short restores our desired signed value.
   int16_t imm = N->getSExtValue();
   return CurDAG->getTargetConstant(imm, SDLoc(N), MVT::i32);
 }]>;
 
-def IMM_WORD : SDNodeXForm<imm, [{
+def IMM_WORD : ConstIntSDNodeXForm<[{
   // -1 etc can be represented as 4294967295 etc
   // Currently, it's not doing this. But some optimization
   // might convert -1 to a large +ve number.
@@ -2882,51 +2882,51 @@
   return ImmIsSingleBit(v);
 }]>;
 
-def Set5Imm8 : SDNodeXForm<imm, [{
+def Set5Imm8 : ConstIntSDNodeXForm<[{
    uint32_t imm = (uint8_t)N->getZExtValue();
    return XformMskToBitPosU5Imm(imm, SDLoc(N));
 }]>;
 
-def Set5Imm16 : SDNodeXForm<imm, [{
+def Set5Imm16 : ConstIntSDNodeXForm<[{
    uint32_t imm = (uint16_t)N->getZExtValue();
    return XformMskToBitPosU5Imm(imm, SDLoc(N));
 }]>;
 
-def Set5Imm32 : SDNodeXForm<imm, [{
+def Set5Imm32 : ConstIntSDNodeXForm<[{
    uint32_t imm = (uint32_t)N->getZExtValue();
    return XformMskToBitPosU5Imm(imm, SDLoc(N));
 }]>;
 
-def Clr5Imm8 : SDNodeXForm<imm, [{
+def Clr5Imm8 : ConstIntSDNodeXForm<[{
    uint32_t imm = (uint8_t)~N->getZExtValue();
    return XformMskToBitPosU5Imm(imm, SDLoc(N));
 }]>;
 
-def Clr5Imm16 : SDNodeXForm<imm, [{
+def Clr5Imm16 : ConstIntSDNodeXForm<[{
    uint32_t imm = (uint16_t)~N->getZExtValue();
    return XformMskToBitPosU5Imm(imm, SDLoc(N));
 }]>;
 
-def Clr5Imm32 : SDNodeXForm<imm, [{
+def Clr5Imm32 : ConstIntSDNodeXForm<[{
    int32_t imm = (int32_t)~N->getZExtValue();
    return XformMskToBitPosU5Imm(imm, SDLoc(N));
 }]>;
 
-def NegImm8 : SDNodeXForm<imm, [{
+def NegImm8 : ConstIntSDNodeXForm<[{
   int8_t V = N->getSExtValue();
   return CurDAG->getTargetConstant(-V, SDLoc(N), MVT::i32);
 }]>;
 
-def NegImm16 : SDNodeXForm<imm, [{
+def NegImm16 : ConstIntSDNodeXForm<[{
   int16_t V = N->getSExtValue();
   return CurDAG->getTargetConstant(-V, SDLoc(N), MVT::i32);
 }]>;
 
-def NegImm32 : SDNodeXForm<imm, [{
+def NegImm32 : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(-N->getSExtValue(), SDLoc(N), MVT::i32);
 }]>;
 
-def IdImm : SDNodeXForm<imm, [{ return SDValue(N, 0); }]>;
+def IdImm : ConstIntSDNodeXForm<[{ return SDValue(N, 0); }]>;
 
 //===----------------------------------------------------------------------===//
 // Template class for MemOp instructions with the register value.
@@ -3293,7 +3293,7 @@
          (C4_cmpneqi IntRegs:$src1, s32ImmPred:$src2)>;
 
 // SDNode for converting immediate C to C-1.
-def DEC_CONST_BYTE : SDNodeXForm<imm, [{
+def DEC_CONST_BYTE : ConstIntSDNodeXForm<[{
    // Return the byte immediate const-1 as an SDNode.
    int32_t imm = N->getSExtValue();
    return XformU7ToU7M1Imm(imm, SDLoc(N));
Index: llvm/lib/Target/Hexagon/HexagonIntrinsics.td
===================================================================
--- llvm/lib/Target/Hexagon/HexagonIntrinsics.td
+++ llvm/lib/Target/Hexagon/HexagonIntrinsics.td
@@ -745,7 +745,7 @@
 def : T_R_pat <A2_tfr, int_hexagon_A2_tfr>;
 def : T_I_pat <A2_tfrsi, int_hexagon_A2_tfrsi>;
 
-def ImmExt64: SDNodeXForm<imm, [{
+def ImmExt64: ConstIntSDNodeXForm<[{
   int64_t V = N->getSExtValue();
   return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i64);
 }]>;
Index: llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp
===================================================================
--- llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp
+++ llvm/lib/Target/Hexagon/HexagonSelectionDAGInfo.cpp
@@ -21,7 +21,7 @@
     SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
     SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline,
     MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
-  ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
+  auto *ConstantSize = dyn_cast<ConstantIntSDNode>(Size);
   if (AlwaysInline || (Align & 0x3) != 0 || !ConstantSize)
     return SDValue();
 
Index: llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp
+++ llvm/lib/Target/Lanai/LanaiISelDAGToDAG.cpp
@@ -92,7 +92,7 @@
                         SDValue &AluOp, bool RiMode);
 };
 
-bool canBeRepresentedAsSls(const ConstantSDNode &CN) {
+bool canBeRepresentedAsSls(const ConstantIntSDNode &CN) {
   // Fits in 21-bit signed immediate and two low-order bits are zero.
   return isInt<21>(CN.getSExtValue()) && ((CN.getSExtValue() & 0x3) == 0);
 }
@@ -102,7 +102,7 @@
 // Helper functions for ComplexPattern used on LanaiInstrInfo
 // Used on Lanai Load/Store instructions.
 bool LanaiDAGToDAGISel::selectAddrSls(SDValue Addr, SDValue &Offset) {
-  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr)) {
+  if (auto *CN = dyn_cast<ConstantIntSDNode>(Addr)) {
     SDLoc DL(Addr);
     // Loading from a constant address.
     if (canBeRepresentedAsSls(*CN)) {
@@ -124,7 +124,7 @@
                                          bool RiMode) {
   SDLoc DL(Addr);
 
-  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr)) {
+  if (auto *CN = dyn_cast<ConstantIntSDNode>(Addr)) {
     if (RiMode) {
       // Fits in 16-bit signed immediate.
       if (isInt<16>(CN->getSExtValue())) {
@@ -170,7 +170,7 @@
   if (AluOperator == ISD::ADD) {
     AluOp = CurDAG->getTargetConstant(LPAC::ADD, DL, MVT::i32);
     // Addresses of the form FI+const
-    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
+    if (auto *CN = dyn_cast<ConstantIntSDNode>(Addr.getOperand(1)))
       if ((RiMode && isInt<16>(CN->getSExtValue())) ||
           (!RiMode && isInt<10>(CN->getSExtValue()))) {
         // If the first operand is a FI, get the TargetFI Node
@@ -225,7 +225,7 @@
   LPAC::AluCode AluCode = LPAC::isdToLanaiAluCode(AluOperator);
   if (AluCode != LPAC::UNKNOWN) {
     // Skip addresses of the form FI OP const
-    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
+    if (auto *CN = dyn_cast<ConstantIntSDNode>(Addr.getOperand(1)))
       if (isInt<16>(CN->getSExtValue()))
         return false;
 
Index: llvm/lib/Target/Lanai/LanaiISelLowering.cpp
===================================================================
--- llvm/lib/Target/Lanai/LanaiISelLowering.cpp
+++ llvm/lib/Target/Lanai/LanaiISelLowering.cpp
@@ -278,7 +278,7 @@
   switch (ConstraintLetter) {
   case 'I': // Signed 16 bit constant
     // If this fails, the parent routine will give an error
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op)) {
       if (isInt<16>(C->getSExtValue())) {
         Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
                                        Op.getValueType());
@@ -288,7 +288,7 @@
     return;
   case 'J': // integer zero
   case 'O':
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op)) {
       if (C->getZExtValue() == 0) {
         Result = DAG.getTargetConstant(0, SDLoc(C), Op.getValueType());
         break;
@@ -296,7 +296,7 @@
     }
     return;
   case 'K': // unsigned 16 bit immediate
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op)) {
       if (isUInt<16>(C->getZExtValue())) {
         Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(C),
                                        Op.getValueType());
@@ -305,7 +305,7 @@
     }
     return;
   case 'L': // immediate in the range 0 to 31
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op)) {
       if (C->getZExtValue() <= 31) {
         Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(C),
                                        Op.getValueType());
@@ -314,7 +314,7 @@
     }
     return;
   case 'M': // signed 32 bit immediate where lower 16 bits are 0
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op)) {
       int64_t Val = C->getSExtValue();
       if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)) {
         Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
@@ -323,7 +323,7 @@
     }
     return;
   case 'N': // signed 26 bit immediate
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op)) {
       int64_t Val = C->getSExtValue();
       if ((Val >= -33554432) && (Val <= 33554431)) {
         Result = DAG.getTargetConstant(Val, SDLoc(C), Op.getValueType());
@@ -797,7 +797,7 @@
   case ISD::SETEQ:
     return LPCC::ICC_EQ;
   case ISD::SETGT:
-    if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
+    if (auto *RHSC = dyn_cast<ConstantIntSDNode>(RHS))
       if (RHSC->getZExtValue() == 0xFFFFFFFF) {
         // X > -1 -> X >= 0 -> is_plus(X)
         RHS = DAG.getConstant(0, DL, RHS.getValueType());
@@ -807,7 +807,7 @@
   case ISD::SETUGT:
     return LPCC::ICC_UGT;
   case ISD::SETLT:
-    if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
+    if (auto *RHSC = dyn_cast<ConstantIntSDNode>(RHS))
       if (RHSC->getZExtValue() == 0)
         // X < 0 -> is_minus(X)
         return LPCC::ICC_MI;
@@ -815,7 +815,7 @@
   case ISD::SETULT:
     return LPCC::ICC_ULT;
   case ISD::SETLE:
-    if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
+    if (auto *RHSC = dyn_cast<ConstantIntSDNode>(RHS))
       if (RHSC->getZExtValue() == 0xFFFFFFFF) {
         // X <= -1 -> X < 0 -> is_minus(X)
         RHS = DAG.getConstant(0, DL, RHS.getValueType());
@@ -825,7 +825,7 @@
   case ISD::SETULE:
     return LPCC::ICC_ULE;
   case ISD::SETGE:
-    if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS))
+    if (auto *RHSC = dyn_cast<ConstantIntSDNode>(RHS))
       if (RHSC->getZExtValue() == 0)
         // X >= 0 -> is_plus(X)
         return LPCC::ICC_PL;
@@ -872,7 +872,7 @@
   if (VT != MVT::i32)
     return SDValue();
 
-  ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op->getOperand(1));
+  auto *C = dyn_cast<ConstantIntSDNode>(Op->getOperand(1));
   if (!C)
     return SDValue();
 
@@ -1057,7 +1057,7 @@
 
   EVT VT = Op.getValueType();
   SDLoc DL(Op);
-  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned Depth = cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
   if (Depth) {
     SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
     const unsigned Offset = -4;
@@ -1080,7 +1080,7 @@
   EVT VT = Op.getValueType();
   SDLoc DL(Op);
   SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), DL, Lanai::FP, VT);
-  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned Depth = cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
   while (Depth--) {
     const unsigned Offset = -8;
     SDValue Ptr = DAG.getNode(ISD::ADD, DL, VT, FrameAddr,
Index: llvm/lib/Target/Lanai/LanaiInstrInfo.td
===================================================================
--- llvm/lib/Target/Lanai/LanaiInstrInfo.td
+++ llvm/lib/Target/Lanai/LanaiInstrInfo.td
@@ -61,23 +61,23 @@
 def LanaiAdjDynAlloc : SDNode<"LanaiISD::ADJDYNALLOC", SDT_LanaiAdjDynAlloc>;
 
 // Extract bits 0-15 (low-end) of an immediate value.
-def LO16 : SDNodeXForm<imm, [{
+def LO16 : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant((uint64_t)N->getZExtValue() & 0xffff,
                                    SDLoc(N), MVT::i32);
 }]>;
 
 // Extract bits 16-31 (high-end) of an immediate value.
 // Transformation function: shift the immediate value down into the low bits.
-def HI16 : SDNodeXForm<imm, [{
+def HI16 : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant((uint64_t)N->getZExtValue() >> 16, SDLoc(N),
                                    MVT::i32);
 }]>;
 
-def NEG : SDNodeXForm<imm, [{
+def NEG : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(-N->getSExtValue(), SDLoc(N), MVT::i32);
 }]>;
 
-def LO21 : SDNodeXForm<imm, [{
+def LO21 : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant((uint64_t)N->getZExtValue() & 0x1fffff,
                                    SDLoc(N), MVT::i32);
 }]>;
Index: llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp
===================================================================
--- llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp
+++ llvm/lib/Target/Lanai/LanaiSelectionDAGInfo.cpp
@@ -25,7 +25,7 @@
     bool /*isVolatile*/, bool /*AlwaysInline*/,
     MachinePointerInfo /*DstPtrInfo*/,
     MachinePointerInfo /*SrcPtrInfo*/) const {
-  ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
+  auto *ConstantSize = dyn_cast<ConstantIntSDNode>(Size);
   if (!ConstantSize)
     return SDValue();
 
Index: llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
+++ llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp
@@ -182,7 +182,7 @@
   switch (N.getOpcode()) {
   default: break;
   case ISD::Constant: {
-    uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
+    uint64_t Val = cast<ConstantIntSDNode>(N)->getSExtValue();
     AM.Disp += Val;
     return false;
   }
@@ -217,7 +217,7 @@
 
   case ISD::OR:
     // Handle "X | C" as "X + C" iff X is known to have C bits clear.
-    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
+    if (auto *CN = dyn_cast<ConstantIntSDNode>(N.getOperand(1))) {
       MSP430ISelAddressMode Backup = AM;
       uint64_t Offset = CN->getSExtValue();
       // Start with the LHS as an addr mode.
@@ -306,13 +306,13 @@
   switch (VT.getSimpleVT().SimpleTy) {
   case MVT::i8:
     // Sanity check
-    if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 1)
+    if (cast<ConstantIntSDNode>(LD->getOffset())->getZExtValue() != 1)
       return false;
 
     break;
   case MVT::i16:
     // Sanity check
-    if (cast<ConstantSDNode>(LD->getOffset())->getZExtValue() != 2)
+    if (cast<ConstantIntSDNode>(LD->getOffset())->getZExtValue() != 2)
       return false;
 
     break;
Index: llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
===================================================================
--- llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
+++ llvm/lib/Target/MSP430/MSP430ISelLowering.cpp
@@ -716,7 +716,7 @@
   SDLoc dl(N);
 
   // Expand non-constant shifts to loops:
-  if (!isa<ConstantSDNode>(N->getOperand(1)))
+  if (!isa<ConstantIntSDNode>(N->getOperand(1)))
     switch (Opc) {
     default: llvm_unreachable("Invalid shift opcode!");
     case ISD::SHL:
@@ -730,7 +730,8 @@
                          VT, N->getOperand(0), N->getOperand(1));
     }
 
-  uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
+  uint64_t ShiftAmount =
+      cast<ConstantIntSDNode>(N->getOperand(1))->getZExtValue();
 
   // Expand the stuff into sequence of shifts.
   // FIXME: for some shift amounts this might be done better!
@@ -811,7 +812,7 @@
   case ISD::SETUGE:
     // Turn lhs u>= rhs with lhs constant into rhs u< lhs+1, this allows us to
     // fold constant into instruction.
-    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
+    if (const auto *C = dyn_cast<ConstantIntSDNode>(LHS)) {
       LHS = RHS;
       RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
       TCC = MSP430CC::COND_LO;
@@ -825,7 +826,7 @@
   case ISD::SETULT:
     // Turn lhs u< rhs with lhs constant into rhs u>= lhs+1, this allows us to
     // fold constant into instruction.
-    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
+    if (const auto *C = dyn_cast<ConstantIntSDNode>(LHS)) {
       LHS = RHS;
       RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
       TCC = MSP430CC::COND_HS;
@@ -839,7 +840,7 @@
   case ISD::SETGE:
     // Turn lhs >= rhs with lhs constant into rhs < lhs+1, this allows us to
     // fold constant into instruction.
-    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
+    if (const auto *C = dyn_cast<ConstantIntSDNode>(LHS)) {
       LHS = RHS;
       RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
       TCC = MSP430CC::COND_L;
@@ -853,7 +854,7 @@
   case ISD::SETLT:
     // Turn lhs < rhs with lhs constant into rhs >= lhs+1, this allows us to
     // fold constant into instruction.
-    if (const ConstantSDNode * C = dyn_cast<ConstantSDNode>(LHS)) {
+    if (const auto *C = dyn_cast<ConstantIntSDNode>(LHS)) {
       LHS = RHS;
       RHS = DAG.getConstant(C->getSExtValue() + 1, dl, C->getValueType(0));
       TCC = MSP430CC::COND_GE;
@@ -894,7 +895,7 @@
   // FIXME: since we're doing a post-processing, use a pseudoinstr here, so
   // lowering & isel wouldn't diverge.
   bool andCC = false;
-  if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
+  if (auto *RHSC = dyn_cast<ConstantIntSDNode>(RHS)) {
     if (RHSC->isNullValue() && LHS.hasOneUse() &&
         (LHS.getOpcode() == ISD::AND ||
          (LHS.getOpcode() == ISD::TRUNCATE &&
@@ -913,8 +914,8 @@
   bool Invert = false;
   bool Shift = false;
   bool Convert = true;
-  switch (cast<ConstantSDNode>(TargetCC)->getZExtValue()) {
-   default:
+  switch (cast<ConstantIntSDNode>(TargetCC)->getZExtValue()) {
+  default:
     Convert = false;
     break;
    case MSP430CC::COND_HS:
@@ -1016,7 +1017,7 @@
   if (verifyReturnAddressArgumentIsConstant(Op, DAG))
     return SDValue();
 
-  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned Depth = cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
   SDLoc dl(Op);
   auto PtrVT = getPointerTy(DAG.getDataLayout());
 
@@ -1042,7 +1043,7 @@
 
   EVT VT = Op.getValueType();
   SDLoc dl(Op);  // FIXME probably not meaningful
-  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned Depth = cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
   SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
                                          MSP430::FP, VT);
   while (Depth--)
@@ -1095,7 +1096,7 @@
   if (Op->getOpcode() != ISD::ADD)
     return false;
 
-  if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(Op->getOperand(1))) {
+  if (auto *RHS = dyn_cast<ConstantIntSDNode>(Op->getOperand(1))) {
     uint64_t RHSC = RHS->getZExtValue();
     if ((VT == MVT::i16 && RHSC != 2) ||
         (VT == MVT::i8 && RHSC != 1))
Index: llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
+++ llvm/lib/Target/Mips/Mips16ISelDAGToDAG.cpp
@@ -122,7 +122,7 @@
   }
   // Addresses of the form FI+const or FI|const
   if (CurDAG->isBaseWithConstantOffset(Addr)) {
-    ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
+    auto *CN = dyn_cast<ConstantIntSDNode>(Addr.getOperand(1));
     if (isInt<16>(CN->getSExtValue())) {
       // If the first operand is a FI, get the TargetFI Node
       if (SPAllowed) {
Index: llvm/lib/Target/Mips/Mips64InstrInfo.td
===================================================================
--- llvm/lib/Target/Mips/Mips64InstrInfo.td
+++ llvm/lib/Target/Mips/Mips64InstrInfo.td
@@ -27,12 +27,12 @@
 def immZExt5_64 : ImmLeaf<i64, [{ return Imm == (Imm & 0x1f); }]>;
 
 // Transformation function: get log2 of low 32 bits of immediate
-def Log2LO : SDNodeXForm<imm, [{
+def Log2LO : ConstIntSDNodeXForm<[{
   return getImm(N, Log2_64((unsigned) N->getZExtValue()));
 }]>;
 
 // Transformation function: get log2 of high 32 bits of immediate
-def Log2HI : SDNodeXForm<imm, [{
+def Log2HI : ConstIntSDNodeXForm<[{
   return getImm(N, Log2_64((unsigned) (N->getZExtValue() >> 32)));
 }]>;
 
Index: llvm/lib/Target/Mips/MipsISelLowering.cpp
===================================================================
--- llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -572,7 +572,7 @@
 // Creates and returns a CMovFPT/F node.
 static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True,
                             SDValue False, const SDLoc &DL) {
-  ConstantSDNode *CC = cast<ConstantSDNode>(Cond.getOperand(2));
+  auto *CC = cast<ConstantIntSDNode>(Cond.getOperand(2));
   bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue());
   SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
 
@@ -598,7 +598,7 @@
   if (!FalseTy.isInteger())
     return SDValue();
 
-  ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
+  auto *FalseC = dyn_cast<ConstantIntSDNode>(False);
 
   // If the RHS (False) is 0, we swap the order of the operands
   // of ISD::SELECT (obviously also inverting the condition) so that we can
@@ -625,7 +625,7 @@
   // If both operands are integer constants there's a possibility that we
   // can do some interesting optimizations.
   SDValue True = N->getOperand(1);
-  ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(True);
+  auto *TrueC = dyn_cast<ConstantIntSDNode>(True);
 
   if (!TrueC || !True.getValueType().isInteger())
     return SDValue();
@@ -667,7 +667,7 @@
 
   SDValue ValueIfTrue = N->getOperand(0), ValueIfFalse = N->getOperand(2);
 
-  ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(ValueIfFalse);
+  auto *FalseC = dyn_cast<ConstantIntSDNode>(ValueIfFalse);
   if (!FalseC || FalseC->getZExtValue())
     return SDValue();
 
@@ -703,15 +703,15 @@
     return SDValue();
 
   // The second operand of the shift must be an immediate.
-  ConstantSDNode *CN;
-  if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1))))
+  ConstantIntSDNode *CN;
+  if (!(CN = dyn_cast<ConstantIntSDNode>(ShiftRight.getOperand(1))))
     return SDValue();
 
   uint64_t Pos = CN->getZExtValue();
   uint64_t SMPos, SMSize;
 
   // Op's second operand must be a shifted mask.
-  if (!(CN = dyn_cast<ConstantSDNode>(Mask)) ||
+  if (!(CN = dyn_cast<ConstantIntSDNode>(Mask)) ||
       !isShiftedMask(CN->getZExtValue(), SMPos, SMSize))
     return SDValue();
 
@@ -740,13 +740,13 @@
 
   SDValue And0 = N->getOperand(0), And1 = N->getOperand(1);
   uint64_t SMPos0, SMSize0, SMPos1, SMSize1;
-  ConstantSDNode *CN;
+  ConstantIntSDNode *CN;
 
   // See if Op's first operand matches (and $src1 , mask0).
   if (And0.getOpcode() != ISD::AND)
     return SDValue();
 
-  if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) ||
+  if (!(CN = dyn_cast<ConstantIntSDNode>(And0.getOperand(1))) ||
       !isShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0))
     return SDValue();
 
@@ -754,7 +754,7 @@
   if (And1.getOpcode() != ISD::AND)
     return SDValue();
 
-  if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) ||
+  if (!(CN = dyn_cast<ConstantIntSDNode>(And1.getOperand(1))) ||
       !isShiftedMask(CN->getZExtValue(), SMPos1, SMSize1))
     return SDValue();
 
@@ -766,7 +766,7 @@
   if (Shl.getOpcode() != ISD::SHL)
     return SDValue();
 
-  if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1))))
+  if (!(CN = dyn_cast<ConstantIntSDNode>(Shl.getOperand(1))))
     return SDValue();
 
   unsigned Shamt = CN->getZExtValue();
@@ -1716,7 +1716,7 @@
 
   SDValue CCNode  = CondRes.getOperand(2);
   Mips::CondCode CC =
-    (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
+      (Mips::CondCode)cast<ConstantIntSDNode>(CCNode)->getZExtValue();
   unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T;
   SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32);
   SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32);
@@ -2103,7 +2103,7 @@
 SDValue MipsTargetLowering::
 lowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const {
   // check the depth
-  assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
+  assert((cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
          "Frame address can only be determined for current frame.");
 
   MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
@@ -2121,7 +2121,7 @@
     return SDValue();
 
   // check the depth
-  assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
+  assert((cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue() == 0) &&
          "Return address can be determined only for current frame.");
 
   MachineFunction &MF = DAG.getMachineFunction();
@@ -3572,7 +3572,7 @@
   default: break; // This will fall through to the generic implementation
   case 'I': // Signed 16 bit constant
     // If this fails, the parent routine will give an error
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op)) {
       EVT Type = Op.getValueType();
       int64_t Val = C->getSExtValue();
       if (isInt<16>(Val)) {
@@ -3582,7 +3582,7 @@
     }
     return;
   case 'J': // integer zero
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op)) {
       EVT Type = Op.getValueType();
       int64_t Val = C->getZExtValue();
       if (Val == 0) {
@@ -3592,7 +3592,7 @@
     }
     return;
   case 'K': // unsigned 16 bit immediate
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op)) {
       EVT Type = Op.getValueType();
       uint64_t Val = (uint64_t)C->getZExtValue();
       if (isUInt<16>(Val)) {
@@ -3602,7 +3602,7 @@
     }
     return;
   case 'L': // signed 32 bit immediate where lower 16 bits are 0
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op)) {
       EVT Type = Op.getValueType();
       int64_t Val = C->getSExtValue();
       if ((isInt<32>(Val)) && ((Val & 0xffff) == 0)){
@@ -3612,7 +3612,7 @@
     }
     return;
   case 'N': // immediate in the range of -65535 to -1 (inclusive)
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op)) {
       EVT Type = Op.getValueType();
       int64_t Val = C->getSExtValue();
       if ((Val >= -65535) && (Val <= -1)) {
@@ -3622,7 +3622,7 @@
     }
     return;
   case 'O': // signed 15 bit immediate
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op)) {
       EVT Type = Op.getValueType();
       int64_t Val = C->getSExtValue();
       if ((isInt<15>(Val))) {
@@ -3632,7 +3632,7 @@
     }
     return;
   case 'P': // immediate in the range of 1 to 65535 (inclusive)
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op)) {
       EVT Type = Op.getValueType();
       int64_t Val = C->getSExtValue();
       if ((Val <= 65535) && (Val >= 1)) {
Index: llvm/lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- llvm/lib/Target/Mips/MipsInstrInfo.td
+++ llvm/lib/Target/Mips/MipsInstrInfo.td
@@ -1058,17 +1058,17 @@
 }
 
 // Transformation Function - get the lower 16 bits.
-def LO16 : SDNodeXForm<imm, [{
+def LO16 : ConstIntSDNodeXForm<[{
   return getImm(N, N->getZExtValue() & 0xFFFF);
 }]>;
 
 // Transformation Function - get the higher 16 bits.
-def HI16 : SDNodeXForm<imm, [{
+def HI16 : ConstIntSDNodeXForm<[{
   return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
 }]>;
 
 // Plus 1.
-def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
+def Plus1 : ConstIntSDNodeXForm<[{ return getImm(N, N->getSExtValue() + 1); }]>;
 
 // Node immediate is zero (e.g. insve.d)
 def immz : AnyImmLeaf<[{ return Imm == 0; }]>;
@@ -1089,10 +1089,13 @@
 // immediate are caught.
 // e.g. addiu, sltiu
 def immZExt16  : PatLeaf<(imm), [{
-  if (N->getValueType(0) == MVT::i32)
-    return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
+  auto *C = dyn_cast<ConstantIntSDNode>(N);
+  if (!C)
+    return false;
+  if (C->getValueType(0) == MVT::i32)
+    return (uint32_t)C->getZExtValue() == (unsigned short)C->getZExtValue();
   else
-    return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
+    return (uint64_t)C->getZExtValue() == (unsigned short)C->getZExtValue();
 }], LO16>;
 
 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
Index: llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
+++ llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
@@ -70,7 +70,7 @@
 }
 
 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
-  switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
+  switch (cast<ConstantIntSDNode>(RegIdx)->getZExtValue()) {
   default:
     llvm_unreachable("Could not map int to register");
   case 0: return Mips::MSAIR;
@@ -272,7 +272,7 @@
   // Generate a second addition only if we know that RHS is not a
   // constant-zero node.
   SDNode *AddCarry = Carry;
-  ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS);
+  auto *C = dyn_cast<ConstantIntSDNode>(RHS);
   if (!C || C->getZExtValue())
     AddCarry = CurDAG->getMachineNode(ADDuOp, DL, VT, SDValue(Carry, 0), RHS);
 
@@ -297,7 +297,7 @@
     SDValue Addr, SDValue &Base, SDValue &Offset, unsigned OffsetBits,
     unsigned ShiftAmount = 0) const {
   if (CurDAG->isBaseWithConstantOffset(Addr)) {
-    ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
+    auto *CN = dyn_cast<ConstantIntSDNode>(Addr.getOperand(1));
     if (isIntN(OffsetBits + ShiftAmount, CN->getSExtValue())) {
       EVT ValTy = Addr.getValueType();
 
@@ -456,7 +456,7 @@
     if (isa<FrameIndexSDNode>(Base))
       return false;
 
-    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Offset)) {
+    if (auto *CN = dyn_cast<ConstantIntSDNode>(Offset)) {
       unsigned CnstOff = CN->getZExtValue();
       return (CnstOff == (CnstOff & 0x3c));
     }
@@ -798,7 +798,7 @@
   }
 
   case ISD::Constant: {
-    const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
+    const auto *CN = dyn_cast<ConstantIntSDNode>(Node);
     int64_t Imm = CN->getSExtValue();
     unsigned Size = CN->getValueSizeInBits(0);
 
@@ -840,7 +840,7 @@
   }
 
   case ISD::INTRINSIC_W_CHAIN: {
-    switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
+    switch (cast<ConstantIntSDNode>(Node->getOperand(1))->getZExtValue()) {
     default:
       break;
 
@@ -857,7 +857,7 @@
   }
 
   case ISD::INTRINSIC_WO_CHAIN: {
-    switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
+    switch (cast<ConstantIntSDNode>(Node->getOperand(0))->getZExtValue()) {
     default:
       break;
 
@@ -873,7 +873,7 @@
   }
 
   case ISD::INTRINSIC_VOID: {
-    switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
+    switch (cast<ConstantIntSDNode>(Node->getOperand(1))->getZExtValue()) {
     default:
       break;
 
Index: llvm/lib/Target/Mips/MipsSEISelLowering.cpp
===================================================================
--- llvm/lib/Target/Mips/MipsSEISelLowering.cpp
+++ llvm/lib/Target/Mips/MipsSEISelLowering.cpp
@@ -561,7 +561,7 @@
   // -> (MipsVExtractZExt $a, $b, $c)
   if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
       Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
-    ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
+    auto *Mask = dyn_cast<ConstantIntSDNode>(Op1);
 
     if (!Mask)
       return SDValue();
@@ -836,7 +836,7 @@
                                  const MipsSETargetLowering *TL) {
   EVT VT = N->getValueType(0);
 
-  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
+  if (auto *C = dyn_cast<ConstantIntSDNode>(N->getOperand(1)))
     if (!VT.isVector())
       return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N), VT,
                           TL->getScalarShiftAmountTy(DAG.getDataLayout(), VT),
@@ -908,7 +908,7 @@
     // -> (MipsVExtractSExt $a, $b, $c)
     if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
       SDValue Op0Op0 = Op0->getOperand(0);
-      ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
+      auto *ShAmount = dyn_cast<ConstantIntSDNode>(Op1);
 
       if (!ShAmount)
         return SDValue();
@@ -1457,7 +1457,7 @@
   // The DAG Combiner can't constant fold bitcasted vectors yet so we must do it
   // here for now.
   if (VecTy == MVT::v2i64) {
-    if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) {
+    if (auto *CImm = dyn_cast<ConstantIntSDNode>(Imm)) {
       APInt BitImm = APInt(64, 1) << CImm->getAPIntValue();
 
       SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), DL,
@@ -1505,7 +1505,7 @@
   SDLoc DL(Op);
   EVT ResTy = Op->getValueType(0);
   APInt BitImm = APInt(ResTy.getScalarSizeInBits(), 1)
-                 << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue();
+                 << cast<ConstantIntSDNode>(Op->getOperand(2))->getAPIntValue();
   SDValue BitMask = DAG.getConstant(~BitImm, DL, ResTy);
 
   return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
@@ -1515,7 +1515,7 @@
                                                       SelectionDAG &DAG) const {
   SDLoc DL(Op);
 
-  switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
+  switch (cast<ConstantIntSDNode>(Op->getOperand(0))->getZExtValue()) {
   default:
     return SDValue();
   case Intrinsic::mips_shilo:
@@ -2184,7 +2184,7 @@
 
 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
                                                      SelectionDAG &DAG) const {
-  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
+  unsigned Intr = cast<ConstantIntSDNode>(Op->getOperand(1))->getZExtValue();
   switch (Intr) {
   default:
     return SDValue();
@@ -2252,7 +2252,7 @@
 
 SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
                                                   SelectionDAG &DAG) const {
-  unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
+  unsigned Intr = cast<ConstantIntSDNode>(Op->getOperand(1))->getZExtValue();
   switch (Intr) {
   default:
     return SDValue();
@@ -2312,7 +2312,7 @@
 static bool isConstantOrUndef(const SDValue Op) {
   if (Op->isUndef())
     return true;
-  if (isa<ConstantSDNode>(Op))
+  if (isa<ConstantIntSDNode>(Op))
     return true;
   if (isa<ConstantFPSDNode>(Op))
     return true;
Index: llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
+++ llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
@@ -522,7 +522,7 @@
 }
 
 bool NVPTXDAGToDAGISel::tryIntrinsicChain(SDNode *N) {
-  unsigned IID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
+  unsigned IID = cast<ConstantIntSDNode>(N->getOperand(1))->getZExtValue();
   switch (IID) {
   default:
     return false;
@@ -599,7 +599,7 @@
 }
 
 bool NVPTXDAGToDAGISel::tryIntrinsicNoChain(SDNode *N) {
-  unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
+  unsigned IID = cast<ConstantIntSDNode>(N->getOperand(0))->getZExtValue();
   switch (IID) {
   default:
     return false;
@@ -963,8 +963,9 @@
   unsigned FromTypeWidth = std::max(8U, ScalarVT.getSizeInBits());
   unsigned int FromType;
   // The last operand holds the original LoadSDNode::getExtensionType() value
-  unsigned ExtensionType = cast<ConstantSDNode>(
-      N->getOperand(N->getNumOperands() - 1))->getZExtValue();
+  unsigned ExtensionType =
+      cast<ConstantIntSDNode>(N->getOperand(N->getNumOperands() - 1))
+          ->getZExtValue();
   if (ExtensionType == ISD::SEXTLOAD)
     FromType = NVPTX::PTXLdStInstCode::Signed;
   else if (ScalarVT.isFloatingPoint())
@@ -1318,7 +1319,7 @@
   if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
     Op1 = N->getOperand(2);
     Mem = cast<MemIntrinsicSDNode>(N);
-    unsigned IID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
+    unsigned IID = cast<ConstantIntSDNode>(N->getOperand(1))->getZExtValue();
     switch (IID) {
     default:
       return false;
@@ -2849,7 +2850,7 @@
     VTs = CurDAG->getVTList(EVTs);
   }
 
-  unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
+  unsigned OffsetVal = cast<ConstantIntSDNode>(Offset)->getZExtValue();
 
   SmallVector<SDValue, 2> Ops;
   Ops.push_back(CurDAG->getTargetConstant(OffsetVal, DL, MVT::i32));
@@ -2864,7 +2865,7 @@
   SDLoc DL(N);
   SDValue Chain = N->getOperand(0);
   SDValue Offset = N->getOperand(1);
-  unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
+  unsigned OffsetVal = cast<ConstantIntSDNode>(Offset)->getZExtValue();
   MemSDNode *Mem = cast<MemSDNode>(N);
 
   // How many elements do we have?
@@ -2988,9 +2989,9 @@
   SDLoc DL(N);
   SDValue Chain = N->getOperand(0);
   SDValue Param = N->getOperand(1);
-  unsigned ParamVal = cast<ConstantSDNode>(Param)->getZExtValue();
+  unsigned ParamVal = cast<ConstantIntSDNode>(Param)->getZExtValue();
   SDValue Offset = N->getOperand(2);
-  unsigned OffsetVal = cast<ConstantSDNode>(Offset)->getZExtValue();
+  unsigned OffsetVal = cast<ConstantIntSDNode>(Offset)->getZExtValue();
   MemSDNode *Mem = cast<MemSDNode>(N);
   SDValue Flag = N->getOperand(N->getNumOperands() - 1);
 
@@ -4879,11 +4880,11 @@
   if (N->getOpcode() == ISD::AND) {
     // Canonicalize the operands
     // We want 'and %val, %mask'
-    if (isa<ConstantSDNode>(LHS) && !isa<ConstantSDNode>(RHS)) {
+    if (isa<ConstantIntSDNode>(LHS) && !isa<ConstantIntSDNode>(RHS)) {
       std::swap(LHS, RHS);
     }
 
-    ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(RHS);
+    auto *Mask = dyn_cast<ConstantIntSDNode>(RHS);
     if (!Mask) {
       // We need a constant mask on the RHS of the AND
       return false;
@@ -4906,7 +4907,7 @@
       // We have a 'srl/and' pair, extract the effective start bit and length
       Val = LHS.getNode()->getOperand(0);
       Start = LHS.getNode()->getOperand(1);
-      ConstantSDNode *StartConst = dyn_cast<ConstantSDNode>(Start);
+      auto *StartConst = dyn_cast<ConstantIntSDNode>(Start);
       if (StartConst) {
         uint64_t StartVal = StartConst->getZExtValue();
         // How many "good" bits do we have left?  "good" is defined here as bits
@@ -4934,7 +4935,7 @@
     }
   } else if (N->getOpcode() == ISD::SRL || N->getOpcode() == ISD::SRA) {
     if (LHS->getOpcode() == ISD::AND) {
-      ConstantSDNode *ShiftCnst = dyn_cast<ConstantSDNode>(RHS);
+      auto *ShiftCnst = dyn_cast<ConstantIntSDNode>(RHS);
       if (!ShiftCnst) {
         // Shift amount must be constant
         return false;
@@ -4946,11 +4947,11 @@
       SDValue AndRHS = LHS->getOperand(1);
 
       // Canonicalize the AND to have the mask on the RHS
-      if (isa<ConstantSDNode>(AndLHS)) {
+      if (isa<ConstantIntSDNode>(AndLHS)) {
         std::swap(AndLHS, AndRHS);
       }
 
-      ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(AndRHS);
+      auto *MaskCnst = dyn_cast<ConstantIntSDNode>(AndRHS);
       if (!MaskCnst) {
         // Mask must be constant
         return false;
@@ -4996,7 +4997,7 @@
       Val = LHS->getOperand(0);
 
       SDValue ShlRHS = LHS->getOperand(1);
-      ConstantSDNode *ShlCnst = dyn_cast<ConstantSDNode>(ShlRHS);
+      auto *ShlCnst = dyn_cast<ConstantIntSDNode>(ShlRHS);
       if (!ShlCnst) {
         // Shift amount must be constant
         return false;
@@ -5004,7 +5005,7 @@
       uint64_t InnerShiftAmt = ShlCnst->getZExtValue();
 
       SDValue ShrRHS = RHS;
-      ConstantSDNode *ShrCnst = dyn_cast<ConstantSDNode>(ShrRHS);
+      auto *ShrCnst = dyn_cast<ConstantIntSDNode>(ShrRHS);
       if (!ShrCnst) {
         // Shift amount must be constant
         return false;
@@ -5098,7 +5099,7 @@
 bool NVPTXDAGToDAGISel::SelectADDRsi_imp(
     SDNode *OpNode, SDValue Addr, SDValue &Base, SDValue &Offset, MVT mvt) {
   if (Addr.getOpcode() == ISD::ADD) {
-    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
+    if (auto *CN = dyn_cast<ConstantIntSDNode>(Addr.getOperand(1))) {
       SDValue base = Addr.getOperand(0);
       if (SelectDirectAddr(base, Base)) {
         Offset = CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(OpNode),
@@ -5138,7 +5139,7 @@
     if (SelectDirectAddr(Addr.getOperand(0), Addr)) {
       return false;
     }
-    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
+    if (auto *CN = dyn_cast<ConstantIntSDNode>(Addr.getOperand(1))) {
       if (FrameIndexSDNode *FIN =
               dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
         // Constant offset from frame ref.
Index: llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
===================================================================
--- llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -3943,7 +3943,7 @@
         const SDNode *left = N0.getOperand(0).getNode();
         const SDNode *right = N0.getOperand(1).getNode();
 
-        if (isa<ConstantSDNode>(left) || isa<ConstantSDNode>(right))
+        if (isa<ConstantIntSDNode>(left) || isa<ConstantIntSDNode>(right))
           opIsLive = true;
 
         if (!opIsLive)
@@ -4006,7 +4006,7 @@
   SDValue Val = N->getOperand(0);
   SDValue Mask = N->getOperand(1);
 
-  if (isa<ConstantSDNode>(Val)) {
+  if (isa<ConstantIntSDNode>(Val)) {
     std::swap(Val, Mask);
   }
 
@@ -4023,7 +4023,7 @@
 
   if (Val->getOpcode() == NVPTXISD::LoadV2 ||
       Val->getOpcode() == NVPTXISD::LoadV4) {
-    ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(Mask);
+    auto *MaskCnst = dyn_cast<ConstantIntSDNode>(Mask);
     if (!MaskCnst) {
       // Not an AND with a constant
       return SDValue();
@@ -4048,8 +4048,8 @@
     }
 
     unsigned ExtType =
-      cast<ConstantSDNode>(Val->getOperand(Val->getNumOperands()-1))->
-        getZExtValue();
+        cast<ConstantIntSDNode>(Val->getOperand(Val->getNumOperands() - 1))
+            ->getZExtValue();
     if (ExtType == ISD::SEXTLOAD) {
       // If for some reason the load is a sextload, the and is needed to zero
       // out the high 8 bits
@@ -4185,7 +4185,7 @@
   IsSigned = (LHSSign == Signed);
 
   // The RHS can be a demotable op or a constant
-  if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(RHS)) {
+  if (auto *CI = dyn_cast<ConstantIntSDNode>(RHS)) {
     const APInt &Val = CI->getAPIntValue();
     if (LHSSign == Unsigned) {
       return Val.isIntN(OptSize);
@@ -4219,14 +4219,14 @@
 
   // Canonicalize the multiply so the constant (if any) is on the right
   if (N->getOpcode() == ISD::MUL) {
-    if (isa<ConstantSDNode>(LHS)) {
+    if (isa<ConstantIntSDNode>(LHS)) {
       std::swap(LHS, RHS);
     }
   }
 
   // If we have a SHL, determine the actual multiply amount
   if (N->getOpcode() == ISD::SHL) {
-    ConstantSDNode *ShlRHS = dyn_cast<ConstantSDNode>(RHS);
+    auto *ShlRHS = dyn_cast<ConstantIntSDNode>(RHS);
     if (!ShlRHS) {
       return SDValue();
     }
@@ -4426,7 +4426,7 @@
   SDLoc DL(N);
 
   // Get the intrinsic ID
-  unsigned IntrinNo = cast<ConstantSDNode>(Intrin.getNode())->getZExtValue();
+  unsigned IntrinNo = cast<ConstantIntSDNode>(Intrin.getNode())->getZExtValue();
   switch (IntrinNo) {
   default:
     return;
Index: llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
===================================================================
--- llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
+++ llvm/lib/Target/NVPTX/NVPTXInstrInfo.td
@@ -562,44 +562,62 @@
 
 // Predicates used for converting some patterns to mul.wide.
 def SInt32Const : PatLeaf<(imm), [{
-  const APInt &v = N->getAPIntValue();
+  auto *C = dyn_cast<ConstantIntSDNode>(N);
+  if (!C)
+    return false;
+  const APInt &v = C->getAPIntValue();
   return v.isSignedIntN(32);
 }]>;
 
 def UInt32Const : PatLeaf<(imm), [{
-  const APInt &v = N->getAPIntValue();
+  auto *C = dyn_cast<ConstantIntSDNode>(N);
+  if (!C)
+    return false;
+  const APInt &v = C->getAPIntValue();
   return v.isIntN(32);
 }]>;
 
 def SInt16Const : PatLeaf<(imm), [{
-  const APInt &v = N->getAPIntValue();
+  auto *C = dyn_cast<ConstantIntSDNode>(N);
+  if (!C)
+    return false;
+  const APInt &v = C->getAPIntValue();
   return v.isSignedIntN(16);
 }]>;
 
 def UInt16Const : PatLeaf<(imm), [{
-  const APInt &v = N->getAPIntValue();
+  auto *C = dyn_cast<ConstantIntSDNode>(N);
+  if (!C)
+    return false;
+  const APInt &v = C->getAPIntValue();
   return v.isIntN(16);
 }]>;
 
 def Int5Const : PatLeaf<(imm), [{
   // Check if 0 <= v < 32; only then will the result of (x << v) be an int32.
-  const APInt &v = N->getAPIntValue();
+  auto *C = dyn_cast<ConstantIntSDNode>(N);
+  if (!C)
+    return false;
+  const APInt &v = C->getAPIntValue();
   return v.sge(0) && v.slt(32);
 }]>;
 
 def Int4Const : PatLeaf<(imm), [{
   // Check if 0 <= v < 16; only then will the result of (x << v) be an int16.
-  const APInt &v = N->getAPIntValue();
+  auto *C = dyn_cast<ConstantIntSDNode>(N);
+  if (!C)
+    return false;
+  const APInt &v = C->getAPIntValue();
   return v.sge(0) && v.slt(16);
 }]>;
 
-def SHL2MUL32 : SDNodeXForm<imm, [{
+def SHL2MUL32 : ConstIntSDNodeXForm<[{
   const APInt &v = N->getAPIntValue();
   APInt temp(32, 1);
   return CurDAG->getTargetConstant(temp.shl(v), SDLoc(N), MVT::i32);
 }]>;
 
-def SHL2MUL16 : SDNodeXForm<imm, [{
+def SHL2MUL16 : ConstIntSDNodeXForm<[{
   const APInt &v = N->getAPIntValue();
   APInt temp(16, 1);
   return CurDAG->getTargetConstant(temp.shl(v), SDLoc(N), MVT::i16);
@@ -1134,7 +1152,7 @@
             "}}",
             []>;
 
-def SUB_FRM_32 : SDNodeXForm<imm, [{
+def SUB_FRM_32 : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(32 - N->getZExtValue(), SDLoc(N), MVT::i32);
 }]>;
 
@@ -1188,7 +1206,7 @@
             "}}",
             []>;
 
-def SUB_FRM_64 : SDNodeXForm<imm, [{
+def SUB_FRM_64 : ConstIntSDNodeXForm<[{
     return CurDAG->getTargetConstant(64-N->getZExtValue(), SDLoc(N), MVT::i32);
 }]>;
 
Index: llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -357,11 +357,11 @@
   if (N->getOpcode() != ISD::Constant)
     return false;
 
-  Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
+  Imm = (short)cast<ConstantIntSDNode>(N)->getZExtValue();
   if (N->getValueType(0) == MVT::i32)
-    return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
+    return Imm == (int32_t)cast<ConstantIntSDNode>(N)->getZExtValue();
   else
-    return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
+    return Imm == (int64_t)cast<ConstantIntSDNode>(N)->getZExtValue();
 }
 
 static bool isIntS16Immediate(SDValue Op, short &Imm) {
@@ -373,7 +373,7 @@
 /// operand. If so Imm will receive the 32-bit value.
 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
   if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
-    Imm = cast<ConstantSDNode>(N)->getZExtValue();
+    Imm = cast<ConstantIntSDNode>(N)->getZExtValue();
     return true;
   }
   return false;
@@ -383,7 +383,7 @@
 /// operand.  If so Imm will receive the 64-bit value.
 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
   if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
-    Imm = cast<ConstantSDNode>(N)->getZExtValue();
+    Imm = cast<ConstantIntSDNode>(N)->getZExtValue();
     return true;
   }
   return false;
@@ -813,7 +813,7 @@
   SDLoc dl(N);
 
   // Get 64 bit value.
-  int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
+  int64_t Imm = cast<ConstantIntSDNode>(N)->getZExtValue();
   return getInt64(CurDAG, dl, Imm);
 }
 
@@ -934,7 +934,7 @@
     switch (V.getOpcode()) {
     default: break;
     case ISD::ROTL:
-      if (isa<ConstantSDNode>(V.getOperand(1))) {
+      if (isa<ConstantIntSDNode>(V.getOperand(1))) {
         unsigned RotAmt = V.getConstantOperandVal(1);
 
         const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second;
@@ -946,7 +946,7 @@
       }
       break;
     case ISD::SHL:
-      if (isa<ConstantSDNode>(V.getOperand(1))) {
+      if (isa<ConstantIntSDNode>(V.getOperand(1))) {
         unsigned ShiftAmt = V.getConstantOperandVal(1);
 
         const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second;
@@ -961,7 +961,7 @@
       }
       break;
     case ISD::SRL:
-      if (isa<ConstantSDNode>(V.getOperand(1))) {
+      if (isa<ConstantIntSDNode>(V.getOperand(1))) {
         unsigned ShiftAmt = V.getConstantOperandVal(1);
 
         const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second;
@@ -976,7 +976,7 @@
       }
       break;
     case ISD::AND:
-      if (isa<ConstantSDNode>(V.getOperand(1))) {
+      if (isa<ConstantIntSDNode>(V.getOperand(1))) {
         uint64_t Mask = V.getConstantOperandVal(1);
 
         const SmallVector<ValueBit, 64> *LHSBits;
@@ -2489,10 +2489,9 @@
 
   case PPCISD::SRA_ADDZE: {
     SDValue N0 = N->getOperand(0);
-    SDValue ShiftAmt =
-      CurDAG->getTargetConstant(*cast<ConstantSDNode>(N->getOperand(1))->
-                                  getConstantIntValue(), dl,
-                                  N->getValueType(0));
+    SDValue ShiftAmt = CurDAG->getTargetConstant(
+        *cast<ConstantIntSDNode>(N->getOperand(1))->getConstantIntValue(), dl,
+        N->getValueType(0));
     if (N->getValueType(0) == MVT::i64) {
       SDNode *Op =
         CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, MVT::Glue,
@@ -2786,9 +2785,9 @@
 
     // Handle the setcc cases here.  select_cc lhs, 0, 1, 0, cc
     if (!isPPC64)
-      if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
-        if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
-          if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
+      if (auto *N1C = dyn_cast<ConstantIntSDNode>(N->getOperand(1)))
+        if (auto *N2C = dyn_cast<ConstantIntSDNode>(N->getOperand(2)))
+          if (auto *N3C = dyn_cast<ConstantIntSDNode>(N->getOperand(3)))
             if (N1C->isNullValue() && N3C->isNullValue() &&
                 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
                 // FIXME: Implement this optzn for PPC64.
@@ -2941,7 +2940,7 @@
     // Op #3 is the Dest MBB
     // Op #4 is the Flag.
     // Prevent PPC::PRED_* from being selected into LI.
-    unsigned PCC = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
+    unsigned PCC = cast<ConstantIntSDNode>(N->getOperand(1))->getZExtValue();
     if (EnableBranchHint)
       PCC |= getBranchHint(PCC, FuncInfo, N->getOperand(3));
 
@@ -3062,8 +3061,8 @@
   case PPCISD::VADD_SPLAT: {
     // This expands into one of three sequences, depending on whether
     // the first operand is odd or even, positive or negative.
-    assert(isa<ConstantSDNode>(N->getOperand(0)) &&
-           isa<ConstantSDNode>(N->getOperand(1)) &&
+    assert(isa<ConstantIntSDNode>(N->getOperand(0)) &&
+           isa<ConstantIntSDNode>(N->getOperand(1)) &&
            "Invalid operand on VADD_SPLAT!");
 
     int Elt     = N->getConstantOperandVal(0);
@@ -3171,8 +3170,8 @@
       return false;
     ISD::CondCode CC = cast<CondCodeSDNode>(O.getOperand(4))->get();
 
-    if (!isa<ConstantSDNode>(O.getOperand(2)) ||
-        !isa<ConstantSDNode>(O.getOperand(3)))
+    if (!isa<ConstantIntSDNode>(O.getOperand(2)) ||
+        !isa<ConstantIntSDNode>(O.getOperand(3)))
       return false;
 
     uint64_t PM = O.getConstantOperandVal(2);
@@ -3188,7 +3187,7 @@
     Mask |= PM;
     Alt  |= PAlt;
 
-    if (!isa<ConstantSDNode>(O.getOperand(1)) ||
+    if (!isa<ConstantIntSDNode>(O.getOperand(1)) ||
         O.getConstantOperandVal(1) != 0) {
       SDValue Op0 = O.getOperand(0), Op1 = O.getOperand(1);
       if (Op0.getOpcode() == ISD::TRUNCATE)
@@ -3198,7 +3197,7 @@
 
       if (Op0.getOpcode() == ISD::SRL && Op1.getOpcode() == ISD::SRL &&
           Op0.getOperand(1) == Op1.getOperand(1) && CC == ISD::SETEQ &&
-          isa<ConstantSDNode>(Op0.getOperand(1))) {
+          isa<ConstantIntSDNode>(Op0.getOperand(1))) {
 
         unsigned Bits = Op0.getValueSizeInBits();
         if (b != Bits/8-1)
@@ -3220,7 +3219,7 @@
       // bits from bytes 3 and 4 are known to be zero, the result of the
       // xor can be at most 255)
       if (Op0.getOpcode() == ISD::XOR && CC == ISD::SETULT &&
-          isa<ConstantSDNode>(O.getOperand(1))) {
+          isa<ConstantIntSDNode>(O.getOperand(1))) {
 
         uint64_t ULim = O.getConstantOperandVal(1);
         if (ULim != (UINT64_C(1) << b*8))
@@ -3246,7 +3245,7 @@
 
     SDValue Op = O.getOperand(0);
     if (Op.getOpcode() == ISD::AND) {
-      if (!isa<ConstantSDNode>(Op.getOperand(1)))
+      if (!isa<ConstantIntSDNode>(Op.getOperand(1)))
         return false;
       if (Op.getConstantOperandVal(1) != (UINT64_C(0xFF) << (8*b)))
         return false;
@@ -3261,7 +3260,7 @@
       RHS = XOR.getOperand(1);
       return true;
     } else if (Op.getOpcode() == ISD::SRL) {
-      if (!isa<ConstantSDNode>(Op.getOperand(1)))
+      if (!isa<ConstantIntSDNode>(Op.getOperand(1)))
         return false;
       unsigned Bits = Op.getValueSizeInBits();
       if (b != Bits/8-1)
@@ -3407,8 +3406,8 @@
 
     // For us to materialize these using one instruction, we must be able to
     // represent them as signed 16-bit integers.
-    uint64_t True  = cast<ConstantSDNode>(TrueRes)->getZExtValue(),
-             False = cast<ConstantSDNode>(FalseRes)->getZExtValue();
+    uint64_t True = cast<ConstantIntSDNode>(TrueRes)->getZExtValue(),
+             False = cast<ConstantIntSDNode>(FalseRes)->getZExtValue();
     if (!isInt<16>(True) || !isInt<16>(False))
       break;
 
@@ -3498,7 +3497,7 @@
         Op2->getMachineOpcode() != PPC::LI8)
       return false;
 
-    ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2->getOperand(0));
+    auto *C = dyn_cast<ConstantIntSDNode>(Op2->getOperand(0));
     if (!C)
       return false;
 
@@ -4217,7 +4216,7 @@
       SmallVector<SDValue, 4> Ops;
       for (const SDValue &V : PN->ops()) {
         if (!ToPromote.count(V.getNode()) && V.getValueType() == MVT::i32 &&
-            !isa<ConstantSDNode>(V)) {
+            !isa<ConstantIntSDNode>(V)) {
           SDValue ReplOpOps[] = { ISR.getOperand(0), V, ISR.getOperand(2) };
           SDNode *ReplOp =
             CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, SDLoc(V),
@@ -4319,7 +4318,7 @@
     // we may be able to fold an add-immediate into the memory operation.
     // The check against alignment is below, as it can't occur until we check
     // the arguments to N
-    if (!isa<ConstantSDNode>(N->getOperand(FirstOp)))
+    if (!isa<ConstantIntSDNode>(N->getOperand(FirstOp)))
       continue;
 
     SDValue Base = N->getOperand(FirstOp + 1);
@@ -4351,10 +4350,9 @@
       // For these cases, the immediate may not be divisible by 4, in
       // which case the fold is illegal for DS-form instructions.  (The
       // other cases provide aligned addresses and are always safe.)
-      if ((StorageOpcode == PPC::LWA ||
-           StorageOpcode == PPC::LD  ||
+      if ((StorageOpcode == PPC::LWA || StorageOpcode == PPC::LD ||
            StorageOpcode == PPC::STD) &&
-          (!isa<ConstantSDNode>(Base.getOperand(1)) ||
+          (!isa<ConstantIntSDNode>(Base.getOperand(1)) ||
            Base.getConstantOperandVal(1) % 4 != 0))
         continue;
       break;
@@ -4412,7 +4410,7 @@
       //  2. If the addend is a constant, then it can be combined with a
       //     non-zero offset, but only if the result meets the encoding
       //     requirements.
-      if (auto *C = dyn_cast<ConstantSDNode>(ImmOpnd)) {
+      if (auto *C = dyn_cast<ConstantIntSDNode>(ImmOpnd)) {
         Offset += C->getSExtValue();
 
         if ((StorageOpcode == PPC::LWA || StorageOpcode == PPC::LD ||
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1170,7 +1170,8 @@
   return false;
 }
 
-/// isConstantOrUndef - Op is either an undef node or a ConstantSDNode.  Return
+/// isConstantOrUndef - Op is either an undef node or a ConstantIntSDNode.
+/// Return
 /// true if Op is undef or if it matches the specified value.
 static bool isConstantOrUndef(int Op, int Val) {
   return Op < 0 || Op == Val;
@@ -1656,8 +1657,8 @@
     for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
       if (N->getOperand(i).isUndef()) continue;
       // If the element isn't a constant, bail fully out.
-      if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
-
+      if (!isa<ConstantIntSDNode>(N->getOperand(i)))
+        return SDValue();
 
       if (!UniquedVals[i&(Multiple-1)].getNode())
         UniquedVals[i&(Multiple-1)] = N->getOperand(i);
@@ -1683,14 +1684,16 @@
     if (LeadingZero) {
       if (!UniquedVals[Multiple-1].getNode())
         return DAG.getTargetConstant(0, SDLoc(N), MVT::i32);  // 0,0,0,undef
-      int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
+      int Val =
+          cast<ConstantIntSDNode>(UniquedVals[Multiple - 1])->getZExtValue();
       if (Val < 16)                                   // 0,0,0,4 -> vspltisw(4)
         return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
     }
     if (LeadingOnes) {
       if (!UniquedVals[Multiple-1].getNode())
         return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
-      int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
+      int Val =
+          cast<ConstantIntSDNode>(UniquedVals[Multiple - 1])->getSExtValue();
       if (Val >= -16)                            // -1,-1,-1,-2 -> vspltisw(-2)
         return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
     }
@@ -1711,7 +1714,7 @@
 
   unsigned ValSizeInBytes = EltSize;
   uint64_t Value = 0;
-  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
+  if (auto *CN = dyn_cast<ConstantIntSDNode>(OpVal)) {
     Value = CN->getZExtValue();
   } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
     assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
@@ -1779,14 +1782,14 @@
 /// sign extension from a 16-bit value.  If so, this returns true and the
 /// immediate.
 static bool isIntS16Immediate(SDNode *N, short &Imm) {
-  if (!isa<ConstantSDNode>(N))
+  if (!isa<ConstantIntSDNode>(N))
     return false;
 
-  Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
+  Imm = (short)cast<ConstantIntSDNode>(N)->getZExtValue();
   if (N->getValueType(0) == MVT::i32)
-    return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
+    return Imm == (int32_t)cast<ConstantIntSDNode>(N)->getZExtValue();
   else
-    return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
+    return Imm == (int64_t)cast<ConstantIntSDNode>(N)->getZExtValue();
 }
 static bool isIntS16Immediate(SDValue Op, short &Imm) {
   return isIntS16Immediate(Op.getNode(), Imm);
@@ -1904,8 +1907,9 @@
       return true; // [r+i]
     } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
       // Match LOAD (ADD (X, Lo(G))).
-      assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
-             && "Cannot handle constant offsets yet!");
+      assert(!cast<ConstantIntSDNode>(N.getOperand(1).getOperand(1))
+                  ->getZExtValue() &&
+             "Cannot handle constant offsets yet!");
       Disp = N.getOperand(1).getOperand(0);  // The global address.
       assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
              Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
@@ -1938,7 +1942,7 @@
         return true;
       }
     }
-  } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
+  } else if (auto *CN = dyn_cast<ConstantIntSDNode>(N)) {
     // Loading from a constant address.
 
     // If this address fits entirely in a 16-bit sext immediate field, codegen
@@ -2081,7 +2085,7 @@
     // sext i32 to i64 when addr mode is r+i.
     if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
         LD->getExtensionType() == ISD::SEXTLOAD &&
-        isa<ConstantSDNode>(Offset))
+        isa<ConstantIntSDNode>(Offset))
       return false;
   }
 
@@ -2402,7 +2406,7 @@
   if (SDValue V = lowerCmpEqZeroToCtlzSrl(Op, DAG))
     return V;
 
-  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+  if (auto *C = dyn_cast<ConstantIntSDNode>(Op.getOperand(1))) {
     // Leave comparisons against 0 and -1 alone for now, since they're usually
     // optimized.  FIXME: revisit this when we can custom lower all setcc
     // optimizations.
@@ -4162,7 +4166,7 @@
 /// isCallCompatibleAddress - Return the immediate to use if the specified
 /// 32-bit value is representable in the immediate field of a BxA instruction.
 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
-  ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
+  auto *C = dyn_cast<ConstantIntSDNode>(Op);
   if (!C) return nullptr;
 
   int Addr = C->getZExtValue();
@@ -4651,8 +4655,9 @@
              cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
             Callee.getOpcode() == ISD::TargetExternalSymbol ||
             Callee.getOpcode() == ISD::TargetGlobalAddress ||
-            isa<ConstantSDNode>(Callee)) &&
-    "Expecting an global address, external symbol, absolute value or register");
+            isa<ConstantIntSDNode>(Callee)) &&
+           "Expecting an global address, external symbol, absolute value or "
+           "register");
 
     DAG.getMachineFunction().getFrameInfo().setHasTailCall();
     return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
@@ -7130,7 +7135,7 @@
     bool IsConst = true;
     for (unsigned i = 0; i < 4; ++i) {
       if (BVN->getOperand(i).isUndef()) continue;
-      if (!isa<ConstantSDNode>(BVN->getOperand(i))) {
+      if (!isa<ConstantIntSDNode>(BVN->getOperand(i))) {
         IsConst = false;
         break;
       }
@@ -7703,7 +7708,7 @@
 static bool getVectorCompareInfo(SDValue Intrin, int &CompareOpc,
                                  bool &isDot, const PPCSubtarget &Subtarget) {
   unsigned IntrinsicID =
-    cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
+      cast<ConstantIntSDNode>(Intrin.getOperand(0))->getZExtValue();
   CompareOpc = -1;
   isDot = false;
   switch (IntrinsicID) {
@@ -7857,7 +7862,7 @@
 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
                                                    SelectionDAG &DAG) const {
   unsigned IntrinsicID =
-    cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+      cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
 
   if (IntrinsicID == Intrinsic::thread_pointer) {
     // Reads the thread pointer register, used for __builtin_thread_pointer.
@@ -7900,7 +7905,7 @@
   // Unpack the result based on how the target uses it.
   unsigned BitNo;   // Bit # of CR6.
   bool InvertBit;   // Invert result?
-  switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
+  switch (cast<ConstantIntSDNode>(Op.getOperand(1))->getZExtValue()) {
   default:  // Can't happen, don't crash on invalid number though.
   case 0:   // Return the value of the EQ bit of CR6.
     BitNo = 0; InvertBit = false;
@@ -7974,7 +7979,7 @@
                                                   SelectionDAG &DAG) const {
   assert(Op.getOpcode() == ISD::INSERT_VECTOR_ELT &&
          "Should only be called for ISD::INSERT_VECTOR_ELT");
-  ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(2));
+  auto *C = dyn_cast<ConstantIntSDNode>(Op.getOperand(2));
   // We have legal lowering for constant indices but not for variable ones.
   if (C)
     return Op;
@@ -8027,7 +8032,8 @@
     dl, VTs, Ops, MVT::v4i32, PtrInfo);
 
   // Extract the value requested.
-  unsigned Offset = 4*cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
+  unsigned Offset =
+      4 * cast<ConstantIntSDNode>(N->getOperand(1))->getZExtValue();
   SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
   Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
 
@@ -8415,7 +8421,7 @@
     break;
   }
   case ISD::INTRINSIC_W_CHAIN: {
-    if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
+    if (cast<ConstantIntSDNode>(N->getOperand(1))->getZExtValue() !=
         Intrinsic::ppc_is_decremented_ctr_nonzero)
       break;
 
@@ -9724,7 +9730,7 @@
                                      int64_t& Offset, SelectionDAG &DAG) {
   if (DAG.isBaseWithConstantOffset(Loc)) {
     Base = Loc.getOperand(0);
-    Offset += cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue();
+    Offset += cast<ConstantIntSDNode>(Loc.getOperand(1))->getSExtValue();
 
     // The base might itself be a base plus an offset, and if so, accumulate
     // that as well.
@@ -9783,7 +9789,7 @@
 
   if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
     EVT VT;
-    switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
+    switch (cast<ConstantIntSDNode>(N->getOperand(1))->getZExtValue()) {
     default: return false;
     case Intrinsic::ppc_qpx_qvlfd:
     case Intrinsic::ppc_qpx_qvlfda:
@@ -9827,7 +9833,7 @@
 
   if (N->getOpcode() == ISD::INTRINSIC_VOID) {
     EVT VT;
-    switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
+    switch (cast<ConstantIntSDNode>(N->getOperand(1))->getZExtValue()) {
     default: return false;
     case Intrinsic::ppc_qpx_qvstfd:
     case Intrinsic::ppc_qpx_qvstfda:
@@ -10034,8 +10040,8 @@
     if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
           N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
           N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
-          N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
-        isa<ConstantSDNode>(N->getOperand(i)))
+         N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
+        isa<ConstantIntSDNode>(N->getOperand(i)))
       Inputs.push_back(N->getOperand(i));
     else
       BinOps.push_back(N->getOperand(i));
@@ -10066,7 +10072,7 @@
             BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
             BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
            BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
-          isa<ConstantSDNode>(BinOp.getOperand(i))) {
+          isa<ConstantIntSDNode>(BinOp.getOperand(i))) {
         Inputs.push_back(BinOp.getOperand(i));
       } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
                  BinOp.getOperand(i).getOpcode() == ISD::OR  ||
@@ -10090,7 +10096,7 @@
   // is not quite the same thing as saying that everything has only one
   // use).
   for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
-    if (isa<ConstantSDNode>(Inputs[i]))
+    if (isa<ConstantIntSDNode>(Inputs[i]))
       continue;
 
     for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
@@ -10144,7 +10150,7 @@
   for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
     // Constants may have users outside the cluster of to-be-promoted nodes,
     // and so we need to replace those as we do the promotions.
-    if (isa<ConstantSDNode>(Inputs[i]))
+    if (isa<ConstantIntSDNode>(Inputs[i]))
       continue;
     else
       DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
@@ -10167,7 +10173,7 @@
         PromOp.getOpcode() == ISD::SIGN_EXTEND ||
         PromOp.getOpcode() == ISD::ZERO_EXTEND ||
         PromOp.getOpcode() == ISD::ANY_EXTEND) {
-      if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
+      if (!isa<ConstantIntSDNode>(PromOp.getOperand(0)) &&
           PromOp.getOperand(0).getValueType() != MVT::i1) {
         // The operand is not yet ready (see comment below).
         PromOpHandles.emplace_front(PromOp);
@@ -10175,7 +10181,7 @@
       }
 
       SDValue RepValue = PromOp.getOperand(0);
-      if (isa<ConstantSDNode>(RepValue))
+      if (isa<ConstantIntSDNode>(RepValue))
         RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
 
       DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
@@ -10189,10 +10195,10 @@
     case ISD::SELECT_CC: C = 2; break;
     }
 
-    if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
+    if ((!isa<ConstantIntSDNode>(PromOp.getOperand(C)) &&
          PromOp.getOperand(C).getValueType() != MVT::i1) ||
-        (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
-         PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
+        (!isa<ConstantIntSDNode>(PromOp.getOperand(C + 1)) &&
+         PromOp.getOperand(C + 1).getValueType() != MVT::i1)) {
       // The to-be-promoted operands of this node have not yet been
       // promoted (this should be rare because we're going through the
       // list backward, but if one of the operands has several users in
@@ -10206,7 +10212,7 @@
 
     // If there are any constant inputs, make sure they're replaced now.
     for (unsigned i = 0; i < 2; ++i)
-      if (isa<ConstantSDNode>(Ops[C+i]))
+      if (isa<ConstantIntSDNode>(Ops[C + i]))
         Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
 
     DAG.ReplaceAllUsesOfValueWith(PromOp,
@@ -10279,7 +10285,7 @@
         continue;
 
       if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
-          isa<ConstantSDNode>(BinOp.getOperand(i))) {
+          isa<ConstantIntSDNode>(BinOp.getOperand(i))) {
         Inputs.push_back(BinOp.getOperand(i));
       } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
                  BinOp.getOperand(i).getOpcode() == ISD::OR  ||
@@ -10303,7 +10309,7 @@
   // is not quite the same thing as saying that everything has only one
   // use).
   for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
-    if (isa<ConstantSDNode>(Inputs[i]))
+    if (isa<ConstantIntSDNode>(Inputs[i]))
       continue;
 
     for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
@@ -10361,7 +10367,7 @@
     // If all of the inputs are not already sign/zero extended, then
     // we'll still need to do that at the end.
     for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
-      if (isa<ConstantSDNode>(Inputs[i]))
+      if (isa<ConstantIntSDNode>(Inputs[i]))
         continue;
 
       unsigned OpBits =
@@ -10387,7 +10393,7 @@
     // Constant inputs need to be replaced with the to-be-promoted nodes that
     // use them because they might have users outside of the cluster of
     // promoted nodes.
-    if (isa<ConstantSDNode>(Inputs[i]))
+    if (isa<ConstantIntSDNode>(Inputs[i]))
       continue;
 
     SDValue InSrc = Inputs[i].getOperand(0);
@@ -10423,10 +10429,10 @@
     case ISD::SELECT_CC: C = 2; break;
     }
 
-    if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
+    if ((!isa<ConstantIntSDNode>(PromOp.getOperand(C)) &&
          PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
-        (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
-         PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
+        (!isa<ConstantIntSDNode>(PromOp.getOperand(C + 1)) &&
+         PromOp.getOperand(C + 1).getValueType() != N->getValueType(0))) {
       // The to-be-promoted operands of this node have not yet been
       // promoted (this should be rare because we're going through the
       // list backward, but if one of the operands has several users in
@@ -10453,7 +10459,7 @@
 
     // If this node has constant inputs, then they'll need to be promoted here.
     for (unsigned i = 0; i < 2; ++i) {
-      if (!isa<ConstantSDNode>(Ops[C+i]))
+      if (!isa<ConstantIntSDNode>(Ops[C + i]))
         continue;
       if (Ops[C+i].getValueType() == N->getValueType(0))
         continue;
@@ -10532,8 +10538,8 @@
      Ext2.getOpcode() != ISD::EXTRACT_VECTOR_ELT)
     return SDValue();
 
-  ConstantSDNode *Ext1Op = dyn_cast<ConstantSDNode>(Ext1.getOperand(1));
-  ConstantSDNode *Ext2Op = dyn_cast<ConstantSDNode>(Ext2.getOperand(1));
+  auto *Ext1Op = dyn_cast<ConstantIntSDNode>(Ext1.getOperand(1));
+  auto *Ext2Op = dyn_cast<ConstantIntSDNode>(Ext2.getOperand(1));
   if (!Ext1Op || !Ext2Op)
     return SDValue();
   if (Ext1.getValueType() != MVT::i32 ||
@@ -10793,7 +10799,7 @@
         return N->getOperand(0);
     break;
   case PPCISD::SRA:
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(N->getOperand(0))) {
       if (C->isNullValue() ||   //  0 >>s V -> 0.
           C->isAllOnesValue())    // -1 >>s V -> -1.
         return N->getOperand(0);
@@ -10945,7 +10951,7 @@
           !Trunc->hasOneUse())
         return false;
       if (RightShift->getOpcode() != ISD::SRL ||
-          !isa<ConstantSDNode>(RightShift->getOperand(1)) ||
+          !isa<ConstantIntSDNode>(RightShift->getOperand(1)) ||
           RightShift->getConstantOperandVal(1) != 32 ||
           !RightShift->hasOneUse())
         return false;
@@ -11159,7 +11165,7 @@
     break;
     case ISD::INTRINSIC_WO_CHAIN: {
       bool isLittleEndian = Subtarget.isLittleEndian();
-      unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
+      unsigned IID = cast<ConstantIntSDNode>(N->getOperand(0))->getZExtValue();
       Intrinsic::ID Intr = (isLittleEndian ? Intrinsic::ppc_altivec_lvsr
                                            : Intrinsic::ppc_altivec_lvsl);
       if ((IID == Intr ||
@@ -11179,7 +11185,8 @@
                                     UE = BasePtr->use_end();
                UI != UE; ++UI) {
             if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
-                cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() == IID) {
+                cast<ConstantIntSDNode>(UI->getOperand(0))->getZExtValue() ==
+                    IID) {
               // We've found another LVSL/LVSR, and this address is an aligned
               // multiple of that one. The results will be the same, so use the
               // one we've just found instead.
@@ -11189,20 +11196,22 @@
           }
         }
 
-        if (isa<ConstantSDNode>(Add->getOperand(1))) {
+        if (isa<ConstantIntSDNode>(Add->getOperand(1))) {
           SDNode *BasePtr = Add->getOperand(0).getNode();
           for (SDNode::use_iterator UI = BasePtr->use_begin(),
                UE = BasePtr->use_end(); UI != UE; ++UI) {
             if (UI->getOpcode() == ISD::ADD &&
-                isa<ConstantSDNode>(UI->getOperand(1)) &&
-                (cast<ConstantSDNode>(Add->getOperand(1))->getZExtValue() -
-                 cast<ConstantSDNode>(UI->getOperand(1))->getZExtValue()) %
-                (1ULL << Bits) == 0) {
+                isa<ConstantIntSDNode>(UI->getOperand(1)) &&
+                (cast<ConstantIntSDNode>(Add->getOperand(1))->getZExtValue() -
+                 cast<ConstantIntSDNode>(UI->getOperand(1))->getZExtValue()) %
+                        (1ULL << Bits) ==
+                    0) {
               SDNode *OtherAdd = *UI;
               for (SDNode::use_iterator VI = OtherAdd->use_begin(),
                    VE = OtherAdd->use_end(); VI != VE; ++VI) {
                 if (VI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
-                    cast<ConstantSDNode>(VI->getOperand(0))->getZExtValue() == IID) {
+                    cast<ConstantIntSDNode>(VI->getOperand(0))
+                            ->getZExtValue() == IID) {
                   return SDValue(*VI, 0);
                 }
               }
@@ -11217,7 +11226,7 @@
     // For little endian, VSX loads require generating lxvd2x/xxswapd.
     // Not needed on ISA 3.0 based CPUs since we have a non-permuting load.
     if (Subtarget.needsSwapsForVSXMemOps()) {
-      switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
+      switch (cast<ConstantIntSDNode>(N->getOperand(1))->getZExtValue()) {
       default:
         break;
       case Intrinsic::ppc_vsx_lxvw4x:
@@ -11231,7 +11240,7 @@
     // For little endian, VSX stores require generating xxswapd/stxvd2x.
     // Not needed on ISA 3.0 based CPUs since we have a non-permuting store.
     if (Subtarget.needsSwapsForVSXMemOps()) {
-      switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
+      switch (cast<ConstantIntSDNode>(N->getOperand(1))->getZExtValue()) {
       default:
         break;
       case Intrinsic::ppc_vsx_stxvw4x:
@@ -11336,8 +11345,8 @@
     SDValue Target = N->getOperand(2);
 
     if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
-        cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
-          Intrinsic::ppc_is_decremented_ctr_nonzero) {
+        cast<ConstantIntSDNode>(Cond.getOperand(1))->getZExtValue() ==
+            Intrinsic::ppc_is_decremented_ctr_nonzero) {
 
       // We now need to make the intrinsic dead (it cannot be instruction
       // selected).
@@ -11362,20 +11371,20 @@
     // value. If so, pass-through the AND to get to the intrinsic.
     if (LHS.getOpcode() == ISD::AND &&
         LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
-        cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
-          Intrinsic::ppc_is_decremented_ctr_nonzero &&
-        isa<ConstantSDNode>(LHS.getOperand(1)) &&
+        cast<ConstantIntSDNode>(LHS.getOperand(0).getOperand(1))
+                ->getZExtValue() == Intrinsic::ppc_is_decremented_ctr_nonzero &&
+        isa<ConstantIntSDNode>(LHS.getOperand(1)) &&
         !isNullConstant(LHS.getOperand(1)))
       LHS = LHS.getOperand(0);
 
     if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
-        cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
-          Intrinsic::ppc_is_decremented_ctr_nonzero &&
-        isa<ConstantSDNode>(RHS)) {
+        cast<ConstantIntSDNode>(LHS.getOperand(1))->getZExtValue() ==
+            Intrinsic::ppc_is_decremented_ctr_nonzero &&
+        isa<ConstantIntSDNode>(RHS)) {
       assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
              "Counter decrement comparison is not EQ or NE");
 
-      unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
+      unsigned Val = cast<ConstantIntSDNode>(RHS)->getZExtValue();
       bool isBDNZ = (CC == ISD::SETEQ && Val) ||
                     (CC == ISD::SETNE && !Val);
 
@@ -11393,13 +11402,13 @@
     bool isDot;
 
     if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
-        isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
+        isa<ConstantIntSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
         getVectorCompareInfo(LHS, CompareOpc, isDot, Subtarget)) {
       assert(isDot && "Can't compare against a vector result!");
 
       // If this is a comparison against something other than 0/1, then we know
       // that the condition is never/always true.
-      unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
+      unsigned Val = cast<ConstantIntSDNode>(RHS)->getZExtValue();
       if (Val != 0 && Val != 1) {
         if (CC == ISD::SETEQ)      // Cond never true, remove branch.
           return N->getOperand(0);
@@ -11421,7 +11430,7 @@
 
       // Unpack the result based on how the target uses it.
       PPC::Predicate CompOpc;
-      switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
+      switch (cast<ConstantIntSDNode>(LHS.getOperand(1))->getZExtValue()) {
       default:  // Can't happen, don't crash on invalid number though.
       case 0:   // Branch on the value of the EQ bit of CR6.
         CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
@@ -11502,7 +11511,7 @@
     break;
   }
   case ISD::INTRINSIC_WO_CHAIN: {
-    switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
+    switch (cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue()) {
     default: break;
     case Intrinsic::ppc_altivec_vcmpbfp_p:
     case Intrinsic::ppc_altivec_vcmpeqfp_p:
@@ -11749,7 +11758,7 @@
   case 'N':
   case 'O':
   case 'P': {
-    ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
+    auto *CST = dyn_cast<ConstantIntSDNode>(Op);
     if (!CST) return; // Must be an immediate to match.
     SDLoc dl(Op);
     int64_t Value = CST->getSExtValue();
@@ -11852,7 +11861,7 @@
     return SDValue();
 
   SDLoc dl(Op);
-  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned Depth = cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
 
   // Make sure the function does not optimize away the store of the RA to
   // the stack.
@@ -11880,7 +11889,7 @@
 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
                                           SelectionDAG &DAG) const {
   SDLoc dl(Op);
-  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned Depth = cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
 
   MachineFunction &MF = DAG.getMachineFunction();
   MachineFrameInfo &MFI = MF.getFrameInfo();
Index: llvm/lib/Target/PowerPC/PPCInstr64Bit.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstr64Bit.td
+++ llvm/lib/Target/PowerPC/PPCInstr64Bit.td
@@ -54,12 +54,12 @@
 // 64-bit transformation functions.
 //
 
-def SHL64 : SDNodeXForm<imm, [{
+def SHL64 : ConstIntSDNodeXForm<[{
   // Transformation function: 63 - imm
   return getI32Imm(63 - N->getZExtValue(), SDLoc(N));
 }]>;
 
-def SRL64 : SDNodeXForm<imm, [{
+def SRL64 : ConstIntSDNodeXForm<[{
   // Transformation function: 64 - imm
   return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue(), SDLoc(N))
                            : getI32Imm(0, SDLoc(N));
Index: llvm/lib/Target/PowerPC/PPCInstrHTM.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrHTM.td
+++ llvm/lib/Target/PowerPC/PPCInstrHTM.td
@@ -16,7 +16,7 @@
 
 def HasHTM : Predicate<"PPCSubTarget->hasHTM()">;
 
-def HTM_get_imm : SDNodeXForm<imm, [{
+def HTM_get_imm : ConstIntSDNodeXForm<[{
   return getI32Imm (N->getZExtValue(), SDLoc(N));
 }]>;
 
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -263,40 +263,40 @@
 // PowerPC specific transformation functions and pattern fragments.
 //
 
-def SHL32 : SDNodeXForm<imm, [{
+def SHL32 : ConstIntSDNodeXForm<[{
   // Transformation function: 31 - imm
   return getI32Imm(31 - N->getZExtValue(), SDLoc(N));
 }]>;
 
-def SRL32 : SDNodeXForm<imm, [{
+def SRL32 : ConstIntSDNodeXForm<[{
   // Transformation function: 32 - imm
   return N->getZExtValue() ? getI32Imm(32 - N->getZExtValue(), SDLoc(N))
                            : getI32Imm(0, SDLoc(N));
 }]>;
 
-def LO16 : SDNodeXForm<imm, [{
+def LO16 : ConstIntSDNodeXForm<[{
   // Transformation function: get the low 16 bits.
   return getI32Imm((unsigned short)N->getZExtValue(), SDLoc(N));
 }]>;
 
-def HI16 : SDNodeXForm<imm, [{
+def HI16 : ConstIntSDNodeXForm<[{
   // Transformation function: shift the immediate value down into the low bits.
   return getI32Imm((unsigned)N->getZExtValue() >> 16, SDLoc(N));
 }]>;
 
-def HA16 : SDNodeXForm<imm, [{
+def HA16 : ConstIntSDNodeXForm<[{
   // Transformation function: shift the immediate value down into the low bits.
   int Val = N->getZExtValue();
   return getI32Imm((Val - (signed short)Val) >> 16, SDLoc(N));
 }]>;
-def MB : SDNodeXForm<imm, [{
+def MB : ConstIntSDNodeXForm<[{
   // Transformation function: get the start bit of a mask
   unsigned mb = 0, me;
   (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
   return getI32Imm(mb, SDLoc(N));
 }]>;
 
-def ME : SDNodeXForm<imm, [{
+def ME : ConstIntSDNodeXForm<[{
   // Transformation function: get the end bit of a mask
   unsigned mb, me = 0;
   (void)isRunOfOnes((unsigned)N->getZExtValue(), mb, me);
@@ -337,14 +337,17 @@
 }], HI16>;
 
 def imm16ShiftedSExt : PatLeaf<(imm), [{
+  auto *C = dyn_cast<ConstantIntSDNode>(N);
+  if (!C)
+    return false;
   // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
   // immediate are set.  Used by instructions like 'addis'.  Identical to 
   // imm16ShiftedZExt in 32-bit mode.
-  if (N->getZExtValue() & 0xFFFF) return false;
-  if (N->getValueType(0) == MVT::i32)
+  if (C->getZExtValue() & 0xFFFF) return false;
+  if (C->getValueType(0) == MVT::i32)
     return true;
   // For 64-bit, make sure it is sext right.
-  return N->getZExtValue() == (uint64_t)(int)N->getZExtValue();
+  return C->getZExtValue() == (uint64_t)(int)C->getZExtValue();
 }], HI16>;
 
 def imm64ZExt32  : Operand<i64>, ImmLeaf<i64, [{
Index: llvm/lib/Target/PowerPC/PPCInstrQPX.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrQPX.td
+++ llvm/lib/Target/PowerPC/PPCInstrQPX.td
@@ -89,11 +89,11 @@
 }]>;
 
 def fround_inexact : PatFrag<(ops node:$val), (fpround node:$val), [{
-  return cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() == 0;
+  return cast<ConstantIntSDNode>(N->getOperand(1))->getZExtValue() == 0;
 }]>;
 
 def fround_exact : PatFrag<(ops node:$val), (fpround node:$val), [{
-  return cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() == 1;
+  return cast<ConstantIntSDNode>(N->getOperand(1))->getZExtValue() == 1;
 }]>;
 
 let FastIselShouldIgnore = 1 in // FastIsel should ignore all u12 instrs.
Index: llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ llvm/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -87,7 +87,7 @@
     return false;  // direct calls.
 
   if (Addr.getOpcode() == ISD::ADD) {
-    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
+    if (auto *CN = dyn_cast<ConstantIntSDNode>(Addr.getOperand(1))) {
       if (isInt<13>(CN->getSExtValue())) {
         if (FrameIndexSDNode *FIN =
                 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
@@ -126,7 +126,7 @@
     return false;  // direct calls.
 
   if (Addr.getOpcode() == ISD::ADD) {
-    if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
+    if (auto *CN = dyn_cast<ConstantIntSDNode>(Addr.getOperand(1)))
       if (isInt<13>(CN->getSExtValue()))
         return false;  // Let the reg+imm pattern catch this!
     if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
@@ -181,7 +181,7 @@
     if (i < InlineAsm::Op_FirstOperand)
       continue;
 
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(i))) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(N->getOperand(i))) {
       Flag = C->getZExtValue();
       Kind = InlineAsm::getKind(Flag);
     }
Index: llvm/lib/Target/Sparc/SparcISelLowering.cpp
===================================================================
--- llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -1911,7 +1911,7 @@
       isOneConstant(LHS.getOperand(0)) &&
       isNullConstant(LHS.getOperand(1))) {
     SDValue CMPCC = LHS.getOperand(3);
-    SPCC = cast<ConstantSDNode>(LHS.getOperand(2))->getZExtValue();
+    SPCC = cast<ConstantIntSDNode>(LHS.getOperand(2))->getZExtValue();
     LHS = CMPCC.getOperand(0);
     RHS = CMPCC.getOperand(1);
   }
@@ -2975,7 +2975,7 @@
 
 SDValue SparcTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
                                                      SelectionDAG &DAG) const {
-  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned IntNo = cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
   SDLoc dl(Op);
   switch (IntNo) {
   default: return SDValue();    // Don't custom lower most intrinsics.
@@ -3394,7 +3394,7 @@
   switch (ConstraintLetter) {
   default: break;
   case 'I':
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op)) {
       if (isInt<13>(C->getSExtValue())) {
         Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
                                        Op.getValueType());
Index: llvm/lib/Target/Sparc/SparcInstr64Bit.td
===================================================================
--- llvm/lib/Target/Sparc/SparcInstr64Bit.td
+++ llvm/lib/Target/Sparc/SparcInstr64Bit.td
@@ -62,7 +62,7 @@
 // Single-instruction patterns.
 
 // The ALU instructions want their simm13 operands as i32 immediates.
-def as_i32imm : SDNodeXForm<imm, [{
+def as_i32imm : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
 }]>;
 
@@ -81,12 +81,12 @@
   return Imm < 0 && isInt<33>(Imm);
 }]>;
 // Bits 10-31 inverted. Same as assembler's %hix.
-def HIX22 : SDNodeXForm<imm, [{
+def HIX22 : ConstIntSDNodeXForm<[{
   uint64_t Val = (~N->getZExtValue() >> 10) & ((1u << 22) - 1);
   return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32);
 }]>;
 // Bits 0-9 with ones in bits 10-31. Same as assembler's %lox.
-def LOX10 : SDNodeXForm<imm, [{
+def LOX10 : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(~(~N->getZExtValue() & 0x3ff), SDLoc(N),
                                    MVT::i32);
 }]>;
@@ -120,12 +120,12 @@
 //   (or (sllx (or sethi, simmm13)), (or sethi, simm13))
 
 // Bits 42-63, same as assembler's %hh.
-def HH22 : SDNodeXForm<imm, [{
+def HH22 : ConstIntSDNodeXForm<[{
   uint64_t Val = (N->getZExtValue() >> 42) & ((1u << 22) - 1);
   return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32);
 }]>;
 // Bits 32-41, same as assembler's %hm.
-def HM10 : SDNodeXForm<imm, [{
+def HM10 : ConstIntSDNodeXForm<[{
   uint64_t Val = (N->getZExtValue() >> 32) & ((1u << 10) - 1);
   return CurDAG->getTargetConstant(Val, SDLoc(N), MVT::i32);
 }]>;
Index: llvm/lib/Target/Sparc/SparcInstrInfo.td
===================================================================
--- llvm/lib/Target/Sparc/SparcInstrInfo.td
+++ llvm/lib/Target/Sparc/SparcInstrInfo.td
@@ -75,12 +75,12 @@
 
 def simm13  : AnyImmLeaf<[{ return isInt<13>(Imm); }]>;
 
-def LO10 : SDNodeXForm<imm, [{
+def LO10 : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, SDLoc(N),
                                    MVT::i32);
 }]>;
 
-def HI22 : SDNodeXForm<imm, [{
+def HI22 : ConstIntSDNodeXForm<[{
   // Transformation function: shift the immediate value down into the low bits.
   return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, SDLoc(N),
                                    MVT::i32);
Index: llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
+++ llvm/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
@@ -451,10 +451,10 @@
 
     if (Op0Code == ISD::Constant)
       return expandDisp(AM, IsBase, Op1,
-                        cast<ConstantSDNode>(Op0)->getSExtValue());
+                        cast<ConstantIntSDNode>(Op0)->getSExtValue());
     if (Op1Code == ISD::Constant)
       return expandDisp(AM, IsBase, Op0,
-                        cast<ConstantSDNode>(Op1)->getSExtValue());
+                        cast<ConstantIntSDNode>(Op1)->getSExtValue());
 
     if (IsBase && expandIndex(AM, Op0, Op1))
       return true;
@@ -553,7 +553,7 @@
   // First try treating the address as a constant.
   if (Addr.getOpcode() == ISD::Constant &&
       expandDisp(AM, true, SDValue(),
-                 cast<ConstantSDNode>(Addr)->getSExtValue()))
+                 cast<ConstantIntSDNode>(Addr)->getSExtValue()))
     ;
   // Also see if it's a bare ADJDYNALLOC.
   else if (Addr.getOpcode() == SystemZISD::ADJDYNALLOC &&
@@ -698,7 +698,7 @@
     return false;
 
   // We need a constant mask.
-  auto *MaskNode = dyn_cast<ConstantSDNode>(Op.getOperand(1).getNode());
+  auto *MaskNode = dyn_cast<ConstantIntSDNode>(Op.getOperand(1).getNode());
   if (!MaskNode)
     return false;
 
@@ -760,7 +760,7 @@
     if (RxSBG.Opcode == SystemZ::RNSBG)
       return false;
 
-    auto *MaskNode = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
+    auto *MaskNode = dyn_cast<ConstantIntSDNode>(N.getOperand(1).getNode());
     if (!MaskNode)
       return false;
 
@@ -784,7 +784,7 @@
     if (RxSBG.Opcode != SystemZ::RNSBG)
       return false;
 
-    auto *MaskNode = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
+    auto *MaskNode = dyn_cast<ConstantIntSDNode>(N.getOperand(1).getNode());
     if (!MaskNode)
       return false;
 
@@ -808,7 +808,7 @@
     // Any 64-bit rotate left can be merged into the RxSBG.
     if (RxSBG.BitSize != 64 || N.getValueType() != MVT::i64)
       return false;
-    auto *CountNode = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
+    auto *CountNode = dyn_cast<ConstantIntSDNode>(N.getOperand(1).getNode());
     if (!CountNode)
       return false;
 
@@ -846,7 +846,7 @@
   }
 
   case ISD::SHL: {
-    auto *CountNode = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
+    auto *CountNode = dyn_cast<ConstantIntSDNode>(N.getOperand(1).getNode());
     if (!CountNode)
       return false;
 
@@ -873,7 +873,7 @@
 
   case ISD::SRL:
   case ISD::SRA: {
-    auto *CountNode = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
+    auto *CountNode = dyn_cast<ConstantIntSDNode>(N.getOperand(1).getNode());
     if (!CountNode)
       return false;
 
@@ -950,7 +950,7 @@
         SystemZ::isImmLF(~RISBG.Mask) ||
         SystemZ::isImmHF(~RISBG.Mask)) {
       // Force the new mask into the DAG, since it may include known-one bits.
-      auto *MaskN = cast<ConstantSDNode>(N->getOperand(1).getNode());
+      auto *MaskN = cast<ConstantIntSDNode>(N->getOperand(1).getNode());
       if (MaskN->getZExtValue() != RISBG.Mask) {
         SDValue NewMask = CurDAG->getConstant(RISBG.Mask, DL, VT);
         N = CurDAG->UpdateNodeOperands(N, N->getOperand(0), NewMask);
@@ -1100,7 +1100,7 @@
 
 bool SystemZDAGToDAGISel::tryGather(SDNode *N, unsigned Opcode) {
   SDValue ElemV = N->getOperand(2);
-  auto *ElemN = dyn_cast<ConstantSDNode>(ElemV);
+  auto *ElemN = dyn_cast<ConstantIntSDNode>(ElemV);
   if (!ElemN)
     return false;
 
@@ -1140,7 +1140,7 @@
     return false;
 
   SDValue ElemV = Value.getOperand(1);
-  auto *ElemN = dyn_cast<ConstantSDNode>(ElemV);
+  auto *ElemN = dyn_cast<ConstantIntSDNode>(ElemV);
   if (!ElemN)
     return false;
 
@@ -1250,7 +1250,7 @@
     // If this is a 64-bit operation in which both 32-bit halves are nonzero,
     // split the operation into two.
     if (Node->getValueType(0) == MVT::i64)
-      if (auto *Op1 = dyn_cast<ConstantSDNode>(Node->getOperand(1))) {
+      if (auto *Op1 = dyn_cast<ConstantIntSDNode>(Node->getOperand(1))) {
         uint64_t Val = Op1->getZExtValue();
         if (!SystemZ::isImmLF(Val) && !SystemZ::isImmHF(Val)) {
           splitLargeImmediate(Opcode, Node, Node->getOperand(0),
@@ -1277,7 +1277,7 @@
     // If this is a 64-bit constant that is out of the range of LLILF,
     // LLIHF and LGFI, split it into two 32-bit pieces.
     if (Node->getValueType(0) == MVT::i64) {
-      uint64_t Val = cast<ConstantSDNode>(Node)->getZExtValue();
+      uint64_t Val = cast<ConstantIntSDNode>(Node)->getZExtValue();
       if (!SystemZ::isImmLF(Val) && !SystemZ::isImmHF(Val) && !isInt<32>(Val)) {
         splitLargeImmediate(ISD::OR, Node, SDValue(), Val - uint32_t(Val),
                             uint32_t(Val));
@@ -1295,9 +1295,9 @@
       SDValue CCValid = Node->getOperand(2);
       SDValue CCMask = Node->getOperand(3);
       uint64_t ConstCCValid =
-        cast<ConstantSDNode>(CCValid.getNode())->getZExtValue();
+          cast<ConstantIntSDNode>(CCValid.getNode())->getZExtValue();
       uint64_t ConstCCMask =
-        cast<ConstantSDNode>(CCMask.getNode())->getZExtValue();
+          cast<ConstantIntSDNode>(CCMask.getNode())->getZExtValue();
       // Invert the condition.
       CCMask = CurDAG->getConstant(ConstCCValid ^ ConstCCMask, SDLoc(Node),
                                    CCMask.getValueType());
Index: llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
===================================================================
--- llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -755,35 +755,35 @@
   if (Constraint.length() == 1) {
     switch (Constraint[0]) {
     case 'I': // Unsigned 8-bit constant
-      if (auto *C = dyn_cast<ConstantSDNode>(Op))
+      if (auto *C = dyn_cast<ConstantIntSDNode>(Op))
         if (isUInt<8>(C->getZExtValue()))
           Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
                                               Op.getValueType()));
       return;
 
     case 'J': // Unsigned 12-bit constant
-      if (auto *C = dyn_cast<ConstantSDNode>(Op))
+      if (auto *C = dyn_cast<ConstantIntSDNode>(Op))
         if (isUInt<12>(C->getZExtValue()))
           Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
                                               Op.getValueType()));
       return;
 
     case 'K': // Signed 16-bit constant
-      if (auto *C = dyn_cast<ConstantSDNode>(Op))
+      if (auto *C = dyn_cast<ConstantIntSDNode>(Op))
         if (isInt<16>(C->getSExtValue()))
           Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
                                               Op.getValueType()));
       return;
 
     case 'L': // Signed 20-bit displacement (on all targets we support)
-      if (auto *C = dyn_cast<ConstantSDNode>(Op))
+      if (auto *C = dyn_cast<ConstantIntSDNode>(Op))
         if (isInt<20>(C->getSExtValue()))
           Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
                                               Op.getValueType()));
       return;
 
     case 'M': // 0x7fffffff
-      if (auto *C = dyn_cast<ConstantSDNode>(Op))
+      if (auto *C = dyn_cast<ConstantIntSDNode>(Op))
         if (C->getZExtValue() == 0x7fffffff)
           Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
                                               Op.getValueType()));
@@ -1308,7 +1308,7 @@
 // the mask of valid CC values if so.
 static bool isIntrinsicWithCCAndChain(SDValue Op, unsigned &Opcode,
                                       unsigned &CCValid) {
-  unsigned Id = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
+  unsigned Id = cast<ConstantIntSDNode>(Op.getOperand(1))->getZExtValue();
   switch (Id) {
   case Intrinsic::s390_tbegin:
     Opcode = SystemZISD::TBEGIN;
@@ -1334,7 +1334,7 @@
 // CC value as its final argument.  Provide the associated SystemZISD
 // opcode and the mask of valid CC values if so.
 static bool isIntrinsicWithCC(SDValue Op, unsigned &Opcode, unsigned &CCValid) {
-  unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned Id = cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
   switch (Id) {
   case Intrinsic::s390_vpkshs:
   case Intrinsic::s390_vpksfs:
@@ -1610,7 +1610,7 @@
   if (C.ICmpType == SystemZICMP::UnsignedOnly)
     return;
 
-  auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1.getNode());
+  auto *ConstOp1 = dyn_cast<ConstantIntSDNode>(C.Op1.getNode());
   if (!ConstOp1)
     return;
 
@@ -1643,7 +1643,7 @@
 
   // The load must be an extending one and the constant must be within the
   // range of the unextended value.
-  auto *ConstOp1 = cast<ConstantSDNode>(C.Op1);
+  auto *ConstOp1 = cast<ConstantIntSDNode>(C.Op1);
   uint64_t Value = ConstOp1->getZExtValue();
   uint64_t Mask = (1 << NumBits) - 1;
   if (Load->getExtensionType() == ISD::SEXTLOAD) {
@@ -1731,7 +1731,7 @@
 
   // Never swap comparisons with zero since there are many ways to optimize
   // those later.
-  auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
+  auto *ConstOp1 = dyn_cast<ConstantIntSDNode>(C.Op1);
   if (ConstOp1 && ConstOp1->getZExtValue() == 0)
     return false;
 
@@ -1766,10 +1766,10 @@
     return true;
   if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::ZERO_EXTEND)
     return true;
-  if (C.ICmpType != SystemZICMP::SignedOnly &&
-      Opcode0 == ISD::AND &&
+  if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::AND &&
       C.Op0.getOperand(1).getOpcode() == ISD::Constant &&
-      cast<ConstantSDNode>(C.Op0.getOperand(1))->getZExtValue() == 0xffffffff)
+      cast<ConstantIntSDNode>(C.Op0.getOperand(1))->getZExtValue() ==
+          0xffffffff)
     return true;
 
   return false;
@@ -1830,11 +1830,10 @@
 // with (sext (trunc X)) into a comparison with (shl X, 32).
 static void adjustForLTGFR(Comparison &C) {
   // Check for a comparison between (shl X, 32) and 0.
-  if (C.Op0.getOpcode() == ISD::SHL &&
-      C.Op0.getValueType() == MVT::i64 &&
+  if (C.Op0.getOpcode() == ISD::SHL && C.Op0.getValueType() == MVT::i64 &&
       C.Op1.getOpcode() == ISD::Constant &&
-      cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
-    auto *C1 = dyn_cast<ConstantSDNode>(C.Op0.getOperand(1));
+      cast<ConstantIntSDNode>(C.Op1)->getZExtValue() == 0) {
+    auto *C1 = dyn_cast<ConstantIntSDNode>(C.Op0.getOperand(1));
     if (C1 && C1->getZExtValue() == 32) {
       SDValue ShlOp0 = C.Op0.getOperand(0);
       // See whether X has any SIGN_EXTEND_INREG uses.
@@ -1858,7 +1857,7 @@
   if (C.Op0.getOpcode() == ISD::TRUNCATE &&
       C.Op0.getOperand(0).getOpcode() == ISD::LOAD &&
       C.Op1.getOpcode() == ISD::Constant &&
-      cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
+      cast<ConstantIntSDNode>(C.Op1)->getZExtValue() == 0) {
     auto *L = cast<LoadSDNode>(C.Op0.getOperand(0));
     if (L->getMemoryVT().getStoreSizeInBits() <= C.Op0.getValueSizeInBits()) {
       unsigned Type = L->getExtensionType();
@@ -1874,7 +1873,7 @@
 // Return true if shift operation N has an in-range constant shift value.
 // Store it in ShiftVal if so.
 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) {
-  auto *Shift = dyn_cast<ConstantSDNode>(N.getOperand(1));
+  auto *Shift = dyn_cast<ConstantIntSDNode>(N.getOperand(1));
   if (!Shift)
     return false;
 
@@ -1987,7 +1986,7 @@
 static void adjustForTestUnderMask(SelectionDAG &DAG, const SDLoc &DL,
                                    Comparison &C) {
   // Check that we have a comparison with a constant.
-  auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
+  auto *ConstOp1 = dyn_cast<ConstantIntSDNode>(C.Op1);
   if (!ConstOp1)
     return;
   uint64_t CmpVal = ConstOp1->getZExtValue();
@@ -1995,11 +1994,11 @@
   // Check whether the nonconstant input is an AND with a constant mask.
   Comparison NewC(C);
   uint64_t MaskVal;
-  ConstantSDNode *Mask = nullptr;
+  ConstantIntSDNode *Mask = nullptr;
   if (C.Op0.getOpcode() == ISD::AND) {
     NewC.Op0 = C.Op0.getOperand(0);
     NewC.Op1 = C.Op0.getOperand(1);
-    Mask = dyn_cast<ConstantSDNode>(NewC.Op1);
+    Mask = dyn_cast<ConstantIntSDNode>(NewC.Op1);
     if (!Mask)
       return;
     MaskVal = Mask->getZExtValue();
@@ -2108,7 +2107,7 @@
 static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
                          ISD::CondCode Cond, const SDLoc &DL) {
   if (CmpOp1.getOpcode() == ISD::Constant) {
-    uint64_t Constant = cast<ConstantSDNode>(CmpOp1)->getZExtValue();
+    uint64_t Constant = cast<ConstantIntSDNode>(CmpOp1)->getZExtValue();
     unsigned Opcode, CCValid;
     if (CmpOp0.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
         CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(1, 0) &&
@@ -2403,11 +2402,10 @@
 static bool isAbsolute(SDValue CmpOp, SDValue Pos, SDValue Neg) {
   return (Neg.getOpcode() == ISD::SUB &&
           Neg.getOperand(0).getOpcode() == ISD::Constant &&
-          cast<ConstantSDNode>(Neg.getOperand(0))->getZExtValue() == 0 &&
+          cast<ConstantIntSDNode>(Neg.getOperand(0))->getZExtValue() == 0 &&
           Neg.getOperand(1) == Pos &&
-          (Pos == CmpOp ||
-           (Pos.getOpcode() == ISD::SIGN_EXTEND &&
-            Pos.getOperand(0) == CmpOp)));
+          (Pos == CmpOp || (Pos.getOpcode() == ISD::SIGN_EXTEND &&
+                            Pos.getOperand(0) == CmpOp)));
 }
 
 // Return the absolute or negative absolute of Op; IsNegative decides which.
@@ -2434,11 +2432,10 @@
   // Check for absolute and negative-absolute selections, including those
   // where the comparison value is sign-extended (for LPGFR and LNGFR).
   // This check supplements the one in DAGCombiner.
-  if (C.Opcode == SystemZISD::ICMP &&
-      C.CCMask != SystemZ::CCMASK_CMP_EQ &&
+  if (C.Opcode == SystemZISD::ICMP && C.CCMask != SystemZ::CCMASK_CMP_EQ &&
       C.CCMask != SystemZ::CCMASK_CMP_NE &&
       C.Op1.getOpcode() == ISD::Constant &&
-      cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
+      cast<ConstantIntSDNode>(C.Op1)->getZExtValue() == 0) {
     if (isAbsolute(C.Op0, TrueOp, FalseOp))
       return getAbsolute(DAG, DL, TrueOp, C.CCMask & SystemZ::CCMASK_CMP_LT);
     if (isAbsolute(C.Op0, FalseOp, TrueOp))
@@ -2449,8 +2446,8 @@
 
   // Special case for handling -1/0 results.  The shifts we use here
   // should get optimized with the IPM conversion sequence.
-  auto *TrueC = dyn_cast<ConstantSDNode>(TrueOp);
-  auto *FalseC = dyn_cast<ConstantSDNode>(FalseOp);
+  auto *TrueC = dyn_cast<ConstantIntSDNode>(TrueOp);
+  auto *FalseC = dyn_cast<ConstantIntSDNode>(FalseOp);
   if (TrueC && FalseC) {
     int64_t TrueVal = TrueC->getSExtValue();
     int64_t FalseVal = FalseC->getSExtValue();
@@ -2717,7 +2714,7 @@
   MFI.setFrameAddressIsTaken(true);
 
   SDLoc DL(Op);
-  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned Depth = cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
   EVT PtrVT = getPointerTy(DAG.getDataLayout());
 
   // If the back chain frame index has not been allocated yet, do so.
@@ -2748,7 +2745,7 @@
     return SDValue();
 
   SDLoc DL(Op);
-  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned Depth = cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
   EVT PtrVT = getPointerTy(DAG.getDataLayout());
 
   // FIXME The frontend should detect this case.
@@ -2871,8 +2868,8 @@
 
   // If user has set the no alignment function attribute, ignore
   // alloca alignments.
-  uint64_t AlignVal = (RealignOpt ?
-                       dyn_cast<ConstantSDNode>(Align)->getZExtValue() : 0);
+  uint64_t AlignVal =
+      (RealignOpt ? dyn_cast<ConstantIntSDNode>(Align)->getZExtValue() : 0);
 
   uint64_t StackAlign = TFI->getStackAlignment();
   uint64_t RequiredAlign = std::max(AlignVal, StackAlign);
@@ -3067,7 +3064,7 @@
   // If the low part is a constant that is outside the range of LHI,
   // then we're better off using IILF.
   if (LowOp.getOpcode() == ISD::Constant) {
-    int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
+    int64_t Value = int32_t(cast<ConstantIntSDNode>(LowOp)->getZExtValue());
     if (!isInt<16>(Value))
       return Op;
   }
@@ -3077,7 +3074,8 @@
   if (HighOp.getOpcode() == ISD::AND &&
       HighOp.getOperand(1).getOpcode() == ISD::Constant) {
     SDValue HighOp0 = HighOp.getOperand(0);
-    uint64_t Mask = cast<ConstantSDNode>(HighOp.getOperand(1))->getZExtValue();
+    uint64_t Mask =
+        cast<ConstantIntSDNode>(HighOp.getOperand(1))->getZExtValue();
     if (DAG.MaskedValueIsZero(HighOp0, APInt(64, ~(Mask | 0xffffffff))))
       HighOp = HighOp0;
   }
@@ -3171,9 +3169,9 @@
                                                  SelectionDAG &DAG) const {
   SDLoc DL(Op);
   AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
-    cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
+      cast<ConstantIntSDNode>(Op.getOperand(1))->getZExtValue());
   SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
-    cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
+      cast<ConstantIntSDNode>(Op.getOperand(2))->getZExtValue());
 
   // The only fence that needs an instruction is a sequentially-consistent
   // cross-thread fence.
@@ -3232,7 +3230,7 @@
 
   // Convert atomic subtracts of constants into additions.
   if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
-    if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) {
+    if (auto *Const = dyn_cast<ConstantIntSDNode>(Src2)) {
       Opcode = SystemZISD::ATOMIC_LOADW_ADD;
       Src2 = DAG.getConstant(-Const->getSExtValue(), DL, Src2.getValueType());
     }
@@ -3296,7 +3294,7 @@
     SDValue NegSrc2;
     SDLoc DL(Src2);
 
-    if (auto *Op2 = dyn_cast<ConstantSDNode>(Src2)) {
+    if (auto *Op2 = dyn_cast<ConstantIntSDNode>(Src2)) {
       // Use an addition if the operand is constant and either LAA(G) is
       // available or the negative value is in the range of A(G)FHI.
       int64_t Value = (-Op2->getAPIntValue()).getSExtValue();
@@ -3399,13 +3397,13 @@
 
 SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
                                              SelectionDAG &DAG) const {
-  bool IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
+  bool IsData = cast<ConstantIntSDNode>(Op.getOperand(4))->getZExtValue();
   if (!IsData)
     // Just preserve the chain.
     return Op.getOperand(0);
 
   SDLoc DL(Op);
-  bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
+  bool IsWrite = cast<ConstantIntSDNode>(Op.getOperand(2))->getZExtValue();
   unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
   auto *Node = cast<MemIntrinsicSDNode>(Op.getNode());
   SDValue Ops[] = {
@@ -3457,7 +3455,7 @@
                        CC);
   }
 
-  unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned Id = cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
   switch (Id) {
   case Intrinsic::thread_pointer:
     return lowerThreadPointer(SDLoc(Op), DAG);
@@ -4014,7 +4012,7 @@
     if (!Op.isUndef()) {
       uint64_t Value;
       if (Op.getOpcode() == ISD::Constant)
-        Value = dyn_cast<ConstantSDNode>(Op)->getZExtValue();
+        Value = dyn_cast<ConstantIntSDNode>(Op)->getZExtValue();
       else if (Op.getOpcode() == ISD::ConstantFP)
         Value = (dyn_cast<ConstantFPSDNode>(Op)->getValueAPF().bitcastToAPInt()
                  .getZExtValue());
@@ -4093,7 +4091,7 @@
       Op = Op.getOperand(0);
     if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
         Op.getOperand(1).getOpcode() == ISD::Constant) {
-      unsigned Elem = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
+      unsigned Elem = cast<ConstantIntSDNode>(Op.getOperand(1))->getZExtValue();
       GS.add(Op.getOperand(0), Elem);
       FoundOne = true;
     } else if (Op.isUndef()) {
@@ -4370,7 +4368,7 @@
       Op1.getOpcode() != ISD::BITCAST &&
       Op1.getOpcode() != ISD::ConstantFP &&
       Op2.getOpcode() == ISD::Constant) {
-    uint64_t Index = dyn_cast<ConstantSDNode>(Op2)->getZExtValue();
+    uint64_t Index = dyn_cast<ConstantIntSDNode>(Op2)->getZExtValue();
     unsigned Mask = VT.getVectorNumElements() - 1;
     if (Index <= Mask)
       return Op;
@@ -4396,7 +4394,7 @@
   EVT VecVT = Op0.getValueType();
 
   // Extractions of constant indices can be done directly.
-  if (auto *CIndexN = dyn_cast<ConstantSDNode>(Op1)) {
+  if (auto *CIndexN = dyn_cast<ConstantIntSDNode>(Op1)) {
     uint64_t Index = CIndexN->getZExtValue();
     unsigned Mask = VecVT.getVectorNumElements() - 1;
     if (Index <= Mask)
@@ -4832,7 +4830,7 @@
     SDValue Vec = Op.getOperand(0);
     EVT VecVT = Vec.getValueType();
     if (canTreatAsByteVector(VecVT)) {
-      if (auto *IndexN = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+      if (auto *IndexN = dyn_cast<ConstantIntSDNode>(Op.getOperand(1))) {
         unsigned BytesPerElement = VecVT.getVectorElementType().getStoreSize();
         unsigned TruncBytes = TruncVT.getStoreSize();
         if (BytesPerElement % TruncBytes == 0) {
@@ -4866,10 +4864,10 @@
   SDValue N0 = N->getOperand(0);
   EVT VT = N->getValueType(0);
   if (N0.hasOneUse() && N0.getOpcode() == ISD::SRA) {
-    auto *SraAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1));
+    auto *SraAmt = dyn_cast<ConstantIntSDNode>(N0.getOperand(1));
     SDValue Inner = N0.getOperand(0);
     if (SraAmt && Inner.hasOneUse() && Inner.getOpcode() == ISD::SHL) {
-      if (auto *ShlAmt = dyn_cast<ConstantSDNode>(Inner.getOperand(1))) {
+      if (auto *ShlAmt = dyn_cast<ConstantIntSDNode>(Inner.getOperand(1))) {
         unsigned Extra = (VT.getSizeInBits() - N0.getValueSizeInBits());
         unsigned NewShlAmt = ShlAmt->getZExtValue() + Extra;
         unsigned NewSraAmt = SraAmt->getZExtValue() + Extra;
@@ -4896,7 +4894,7 @@
   if (Op0.getOpcode() == ISD::BITCAST)
     Op0 = Op0.getOperand(0);
   if (Op0.getOpcode() == SystemZISD::BYTE_MASK &&
-      cast<ConstantSDNode>(Op0.getOperand(0))->getZExtValue() == 0) {
+      cast<ConstantIntSDNode>(Op0.getOperand(0))->getZExtValue() == 0) {
     // (z_merge_* 0, 0) -> 0.  This is mostly useful for using VLLEZF
     // for v4f32.
     if (Op1 == N->getOperand(0))
@@ -4972,7 +4970,7 @@
 SDValue SystemZTargetLowering::combineEXTRACT_VECTOR_ELT(
     SDNode *N, DAGCombinerInfo &DCI) const {
   // Try to simplify a vector extraction.
-  if (auto *IndexN = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
+  if (auto *IndexN = dyn_cast<ConstantIntSDNode>(N->getOperand(1))) {
     SDValue Op0 = N->getOperand(0);
     EVT VecVT = Op0.getValueType();
     return combineExtract(SDLoc(N), N->getValueType(0), VecVT, Op0,
@@ -5001,20 +4999,18 @@
   // This is a special case since the target doesn't really support v2f32s.
   SelectionDAG &DAG = DCI.DAG;
   SDValue Op0 = N->getOperand(0);
-  if (N->getValueType(0) == MVT::f32 &&
-      Op0.hasOneUse() &&
+  if (N->getValueType(0) == MVT::f32 && Op0.hasOneUse() &&
       Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
       Op0.getOperand(0).getValueType() == MVT::v2f64 &&
       Op0.getOperand(1).getOpcode() == ISD::Constant &&
-      cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue() == 0) {
+      cast<ConstantIntSDNode>(Op0.getOperand(1))->getZExtValue() == 0) {
     SDValue Vec = Op0.getOperand(0);
     for (auto *U : Vec->uses()) {
-      if (U != Op0.getNode() &&
-          U->hasOneUse() &&
+      if (U != Op0.getNode() && U->hasOneUse() &&
           U->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
           U->getOperand(0) == Vec &&
           U->getOperand(1).getOpcode() == ISD::Constant &&
-          cast<ConstantSDNode>(U->getOperand(1))->getZExtValue() == 1) {
+          cast<ConstantIntSDNode>(U->getOperand(1))->getZExtValue() == 1) {
         SDValue OtherRound = SDValue(*U->use_begin(), 0);
         if (OtherRound.getOpcode() == ISD::FP_ROUND &&
             OtherRound.getOperand(0) == SDValue(U, 0) &&
@@ -5099,7 +5095,7 @@
   SDValue N1 = N->getOperand(1);
   if (N1.getOpcode() == ISD::AND) {
     SDValue AndMaskOp = N1->getOperand(1);
-    auto *AndMask = dyn_cast<ConstantSDNode>(AndMaskOp);
+    auto *AndMask = dyn_cast<ConstantIntSDNode>(AndMaskOp);
 
     // The AND mask is constant
     if (AndMask) {
Index: llvm/lib/Target/SystemZ/SystemZOperands.td
===================================================================
--- llvm/lib/Target/SystemZ/SystemZOperands.td
+++ llvm/lib/Target/SystemZ/SystemZOperands.td
@@ -148,97 +148,97 @@
 //===----------------------------------------------------------------------===//
 
 // Bits 0-15 (counting from the lsb).
-def LL16 : SDNodeXForm<imm, [{
+def LL16 : ConstIntSDNodeXForm<[{
   uint64_t Value = N->getZExtValue() & 0x000000000000FFFFULL;
   return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
 }]>;
 
 // Bits 16-31 (counting from the lsb).
-def LH16 : SDNodeXForm<imm, [{
+def LH16 : ConstIntSDNodeXForm<[{
   uint64_t Value = (N->getZExtValue() & 0x00000000FFFF0000ULL) >> 16;
   return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
 }]>;
 
 // Bits 32-47 (counting from the lsb).
-def HL16 : SDNodeXForm<imm, [{
+def HL16 : ConstIntSDNodeXForm<[{
   uint64_t Value = (N->getZExtValue() & 0x0000FFFF00000000ULL) >> 32;
   return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
 }]>;
 
 // Bits 48-63 (counting from the lsb).
-def HH16 : SDNodeXForm<imm, [{
+def HH16 : ConstIntSDNodeXForm<[{
   uint64_t Value = (N->getZExtValue() & 0xFFFF000000000000ULL) >> 48;
   return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
 }]>;
 
 // Low 32 bits.
-def LF32 : SDNodeXForm<imm, [{
+def LF32 : ConstIntSDNodeXForm<[{
   uint64_t Value = N->getZExtValue() & 0x00000000FFFFFFFFULL;
   return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
 }]>;
 
 // High 32 bits.
-def HF32 : SDNodeXForm<imm, [{
+def HF32 : ConstIntSDNodeXForm<[{
   uint64_t Value = N->getZExtValue() >> 32;
   return CurDAG->getTargetConstant(Value, SDLoc(N), MVT::i64);
 }]>;
 
 // Truncate an immediate to a 8-bit signed quantity.
-def SIMM8 : SDNodeXForm<imm, [{
+def SIMM8 : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(int8_t(N->getZExtValue()), SDLoc(N),
                                    MVT::i64);
 }]>;
 
 // Truncate an immediate to a 8-bit unsigned quantity.
-def UIMM8 : SDNodeXForm<imm, [{
+def UIMM8 : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(uint8_t(N->getZExtValue()), SDLoc(N),
                                    MVT::i64);
 }]>;
 
 // Truncate an immediate to a 8-bit unsigned quantity and mask off low bit.
-def UIMM8EVEN : SDNodeXForm<imm, [{
+def UIMM8EVEN : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(N->getZExtValue() & 0xfe, SDLoc(N),
                                    MVT::i64);
 }]>;
 
 // Truncate an immediate to a 12-bit unsigned quantity.
-def UIMM12 : SDNodeXForm<imm, [{
+def UIMM12 : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(N->getZExtValue() & 0xfff, SDLoc(N),
                                    MVT::i64);
 }]>;
 
 // Truncate an immediate to a 16-bit signed quantity.
-def SIMM16 : SDNodeXForm<imm, [{
+def SIMM16 : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(int16_t(N->getZExtValue()), SDLoc(N),
                                    MVT::i64);
 }]>;
 
 // Truncate an immediate to a 16-bit unsigned quantity.
-def UIMM16 : SDNodeXForm<imm, [{
+def UIMM16 : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(uint16_t(N->getZExtValue()), SDLoc(N),
                                    MVT::i64);
 }]>;
 
 // Truncate an immediate to a 32-bit signed quantity.
-def SIMM32 : SDNodeXForm<imm, [{
+def SIMM32 : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(int32_t(N->getZExtValue()), SDLoc(N),
                                    MVT::i64);
 }]>;
 
 // Truncate an immediate to a 32-bit unsigned quantity.
-def UIMM32 : SDNodeXForm<imm, [{
+def UIMM32 : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(uint32_t(N->getZExtValue()), SDLoc(N),
                                    MVT::i64);
 }]>;
 
 // Truncate an immediate to a 48-bit unsigned quantity.
-def UIMM48 : SDNodeXForm<imm, [{
+def UIMM48 : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(uint64_t(N->getZExtValue()) & 0xffffffffffff,
                                    SDLoc(N), MVT::i64);
 }]>;
 
 // Negate and then truncate an immediate to a 32-bit unsigned quantity.
-def NEGIMM32 : SDNodeXForm<imm, [{
+def NEGIMM32 : ConstIntSDNodeXForm<[{
   return CurDAG->getTargetConstant(uint32_t(-N->getZExtValue()), SDLoc(N),
                                    MVT::i64);
 }]>;
Index: llvm/lib/Target/SystemZ/SystemZOperators.td
===================================================================
--- llvm/lib/Target/SystemZ/SystemZOperators.td
+++ llvm/lib/Target/SystemZ/SystemZOperators.td
@@ -360,11 +360,11 @@
 
 // Signed and unsigned comparisons.
 def z_scmp : PatFrag<(ops node:$a, node:$b), (z_icmp node:$a, node:$b, imm), [{
-  unsigned Type = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
+  unsigned Type = cast<ConstantIntSDNode>(N->getOperand(2))->getZExtValue();
   return Type != SystemZICMP::UnsignedOnly;
 }]>;
 def z_ucmp : PatFrag<(ops node:$a, node:$b), (z_icmp node:$a, node:$b, imm), [{
-  unsigned Type = cast<ConstantSDNode>(N->getOperand(2))->getZExtValue();
+  unsigned Type = cast<ConstantIntSDNode>(N->getOperand(2))->getZExtValue();
   return Type != SystemZICMP::SignedOnly;
 }]>;
 
Index: llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
===================================================================
--- llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
+++ llvm/lib/Target/SystemZ/SystemZSelectionDAGInfo.cpp
@@ -53,7 +53,7 @@
   if (IsVolatile)
     return SDValue();
 
-  if (auto *CSize = dyn_cast<ConstantSDNode>(Size))
+  if (auto *CSize = dyn_cast<ConstantIntSDNode>(Size))
     return emitMemMem(DAG, DL, SystemZISD::MVC, SystemZISD::MVC_LOOP,
                       Chain, Dst, Src, CSize->getZExtValue());
   return SDValue();
@@ -82,11 +82,11 @@
   if (IsVolatile)
     return SDValue();
 
-  if (auto *CSize = dyn_cast<ConstantSDNode>(Size)) {
+  if (auto *CSize = dyn_cast<ConstantIntSDNode>(Size)) {
     uint64_t Bytes = CSize->getZExtValue();
     if (Bytes == 0)
       return SDValue();
-    if (auto *CByte = dyn_cast<ConstantSDNode>(Byte)) {
+    if (auto *CByte = dyn_cast<ConstantIntSDNode>(Byte)) {
       // Handle cases that can be done using at most two of
       // MVI, MVHI, MVHHI and MVGHI.  The latter two can only be
       // used if ByteVal is all zeros or all ones; in other casees,
@@ -125,7 +125,7 @@
     assert(Bytes >= 2 && "Should have dealt with 0- and 1-byte cases already");
 
     // Handle the special case of a memset of 0, which can use XC.
-    auto *CByte = dyn_cast<ConstantSDNode>(Byte);
+    auto *CByte = dyn_cast<ConstantIntSDNode>(Byte);
     if (CByte && CByte->getZExtValue() == 0)
       return emitMemMem(DAG, DL, SystemZISD::XC, SystemZISD::XC_LOOP,
                         Chain, Dst, Dst, Bytes);
@@ -181,7 +181,7 @@
     SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src1,
     SDValue Src2, SDValue Size, MachinePointerInfo Op1PtrInfo,
     MachinePointerInfo Op2PtrInfo) const {
-  if (auto *CSize = dyn_cast<ConstantSDNode>(Size)) {
+  if (auto *CSize = dyn_cast<ConstantIntSDNode>(Size)) {
     uint64_t Bytes = CSize->getZExtValue();
     assert(Bytes > 0 && "Caller should have handled 0-size case");
     Chain = emitCLC(DAG, DL, Chain, Src1, Src2, Bytes);
Index: llvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td
===================================================================
--- llvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td
+++ llvm/lib/Target/WebAssembly/WebAssemblyInstrMemory.td
@@ -30,7 +30,7 @@
 
 // Treat an 'or' node as an 'add' if the or'ed bits are known to be zero.
 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
-  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
+  if (auto *CN = dyn_cast<ConstantIntSDNode>(N->getOperand(1)))
     return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
 
   APInt KnownZero0, KnownOne0;
Index: llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -183,12 +183,12 @@
     void PreprocessISelDAG() override;
 
     inline bool immSext8(SDNode *N) const {
-      return isInt<8>(cast<ConstantSDNode>(N)->getSExtValue());
+      return isInt<8>(cast<ConstantIntSDNode>(N)->getSExtValue());
     }
 
     // True if the 64-bit immediate fits in a 32-bit sign-extended field.
     inline bool i64immSExt32(SDNode *N) const {
-      uint64_t v = cast<ConstantSDNode>(N)->getZExtValue();
+      uint64_t v = cast<ConstantIntSDNode>(N)->getZExtValue();
       return (int64_t)v == (int32_t)v;
     }
 
@@ -433,7 +433,7 @@
       // addl 4(%esp), %eax
       // The former is 2 bytes shorter. In case where the increment is 1, then
       // the saving can be 4 bytes (by using incl %eax).
-      if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
+      if (auto *Imm = dyn_cast<ConstantIntSDNode>(Op1))
         if (Imm->getAPIntValue().isSignedIntN(8))
           return false;
 
@@ -715,7 +715,7 @@
   // This optimization is valid because the GNU TLS model defines that
   // gs:0 (or fs:0 on X86-64) contains its own address.
   // For more information see http://people.redhat.com/drepper/tls.pdf
-  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Address))
+  if (auto *C = dyn_cast<ConstantIntSDNode>(Address))
     if (C->getSExtValue() == 0 && AM.Segment.getNode() == nullptr &&
         Subtarget->isTargetGlibc())
       switch (N->getPointerInfo().getAddrSpace()) {
@@ -918,8 +918,7 @@
                                       SDValue Shift, SDValue X,
                                       X86ISelAddressMode &AM) {
   if (Shift.getOpcode() != ISD::SRL ||
-      !isa<ConstantSDNode>(Shift.getOperand(1)) ||
-      !Shift.hasOneUse())
+      !isa<ConstantIntSDNode>(Shift.getOperand(1)) || !Shift.hasOneUse())
     return true;
 
   int ScaleLog = 8 - Shift.getConstantOperandVal(1);
@@ -961,7 +960,7 @@
                                         SDValue Shift, SDValue X,
                                         X86ISelAddressMode &AM) {
   if (Shift.getOpcode() != ISD::SHL ||
-      !isa<ConstantSDNode>(Shift.getOperand(1)))
+      !isa<ConstantIntSDNode>(Shift.getOperand(1)))
     return true;
 
   // Not likely to be profitable if either the AND or SHIFT node has more
@@ -1028,7 +1027,7 @@
                                     SDValue Shift, SDValue X,
                                     X86ISelAddressMode &AM) {
   if (Shift.getOpcode() != ISD::SRL || !Shift.hasOneUse() ||
-      !isa<ConstantSDNode>(Shift.getOperand(1)))
+      !isa<ConstantIntSDNode>(Shift.getOperand(1)))
     return true;
 
   unsigned ShiftAmt = Shift.getConstantOperandVal(1);
@@ -1125,7 +1124,7 @@
     if (!(AM.ES || AM.MCSym) && AM.JT != -1)
       return true;
 
-    if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N))
+    if (auto *Cst = dyn_cast<ConstantIntSDNode>(N))
       if (!foldOffsetIntoAddress(Cst->getSExtValue(), AM))
         return false;
     return true;
@@ -1143,7 +1142,7 @@
     break;
   }
   case ISD::Constant: {
-    uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
+    uint64_t Val = cast<ConstantIntSDNode>(N)->getSExtValue();
     if (!foldOffsetIntoAddress(Val, AM))
       return false;
     break;
@@ -1174,8 +1173,7 @@
     if (AM.IndexReg.getNode() != nullptr || AM.Scale != 1)
       break;
 
-    if (ConstantSDNode
-          *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1))) {
+    if (auto *CN = dyn_cast<ConstantIntSDNode>(N.getNode()->getOperand(1))) {
       unsigned Val = CN->getZExtValue();
       // Note that we handle x<<1 as (,x,2) rather than (x,x) here so
       // that the base operand remains free for further matching. If
@@ -1190,8 +1188,8 @@
         // constant into the disp field here.
         if (CurDAG->isBaseWithConstantOffset(ShVal)) {
           AM.IndexReg = ShVal.getNode()->getOperand(0);
-          ConstantSDNode *AddVal =
-            cast<ConstantSDNode>(ShVal.getNode()->getOperand(1));
+          auto *AddVal =
+              cast<ConstantIntSDNode>(ShVal.getNode()->getOperand(1));
           uint64_t Disp = (uint64_t)AddVal->getSExtValue() << Val;
           if (!foldOffsetIntoAddress(Disp, AM))
             return false;
@@ -1218,8 +1216,8 @@
     // The mask used for the transform is expected to be post-shift, but we
     // found the shift first so just apply the shift to the mask before passing
     // it down.
-    if (!isa<ConstantSDNode>(N.getOperand(1)) ||
-        !isa<ConstantSDNode>(And.getOperand(1)))
+    if (!isa<ConstantIntSDNode>(N.getOperand(1)) ||
+        !isa<ConstantIntSDNode>(And.getOperand(1)))
       break;
     uint64_t Mask = And.getConstantOperandVal(1) >> N.getConstantOperandVal(1);
 
@@ -1241,8 +1239,7 @@
     if (AM.BaseType == X86ISelAddressMode::RegBase &&
         AM.Base_Reg.getNode() == nullptr &&
         AM.IndexReg.getNode() == nullptr) {
-      if (ConstantSDNode
-            *CN = dyn_cast<ConstantSDNode>(N.getNode()->getOperand(1)))
+      if (auto *CN = dyn_cast<ConstantIntSDNode>(N.getNode()->getOperand(1)))
         if (CN->getZExtValue() == 3 || CN->getZExtValue() == 5 ||
             CN->getZExtValue() == 9) {
           AM.Scale = unsigned(CN->getZExtValue())-1;
@@ -1254,10 +1251,10 @@
           // value is an add of something and a constant, we can fold the
           // constant into the disp field here.
           if (MulVal.getNode()->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
-              isa<ConstantSDNode>(MulVal.getNode()->getOperand(1))) {
+              isa<ConstantIntSDNode>(MulVal.getNode()->getOperand(1))) {
             Reg = MulVal.getNode()->getOperand(0);
-            ConstantSDNode *AddVal =
-              cast<ConstantSDNode>(MulVal.getNode()->getOperand(1));
+            auto *AddVal =
+                cast<ConstantIntSDNode>(MulVal.getNode()->getOperand(1));
             uint64_t Disp = AddVal->getSExtValue() * CN->getZExtValue();
             if (foldOffsetIntoAddress(Disp, AM))
               Reg = N.getNode()->getOperand(0);
@@ -1370,7 +1367,7 @@
     // addressing mode optimizations.
     if (X.getSimpleValueType().getSizeInBits() > 64) break;
 
-    if (!isa<ConstantSDNode>(N.getOperand(1)))
+    if (!isa<ConstantIntSDNode>(N.getOperand(1)))
       break;
     uint64_t Mask = N.getConstantOperandVal(1);
 
@@ -1439,8 +1436,8 @@
   Scale = getI8Imm(ScalarSize/8, DL);
 
   // If Base is 0, the whole address is in index and the Scale is 1
-  if (isa<ConstantSDNode>(Base)) {
-    assert(cast<ConstantSDNode>(Base)->isNullValue() &&
+  if (isa<ConstantIntSDNode>(Base)) {
+    assert(cast<ConstantIntSDNode>(Base)->isNullValue() &&
            "Unexpected base in gather/scatter");
     Scale = getI8Imm(1, DL);
     Base = CurDAG->getRegister(0, MVT::i32);
@@ -1547,7 +1544,7 @@
 
 
 bool X86DAGToDAGISel::selectMOV64Imm32(SDValue N, SDValue &Imm) {
-  if (const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
+  if (const auto *CN = dyn_cast<ConstantIntSDNode>(N)) {
     uint64_t ImmVal = CN->getZExtValue();
     if ((uint32_t)ImmVal != (uint64_t)ImmVal)
       return false;
@@ -1900,7 +1897,7 @@
   SDValue Base = Node->getOperand(3);
   SDValue VIdx = Node->getOperand(4);
   SDValue VMask = Node->getOperand(5);
-  ConstantSDNode *Scale = dyn_cast<ConstantSDNode>(Node->getOperand(6));
+  auto *Scale = dyn_cast<ConstantIntSDNode>(Node->getOperand(6));
   if (!Scale)
     return false;
 
@@ -1963,7 +1960,8 @@
     break;
   }
   case ISD::INTRINSIC_W_CHAIN: {
-    unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
+    unsigned IntNo =
+        cast<ConstantIntSDNode>(Node->getOperand(1))->getZExtValue();
     switch (IntNo) {
     default: break;
     case Intrinsic::x86_avx2_gather_d_pd:
@@ -2041,8 +2039,8 @@
     if (NVT != MVT::i32 && NVT != MVT::i64)
       break;
 
-    ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N1);
-    ConstantSDNode *ShlCst = dyn_cast<ConstantSDNode>(N0->getOperand(1));
+    auto *Cst = dyn_cast<ConstantIntSDNode>(N1);
+    auto *ShlCst = dyn_cast<ConstantIntSDNode>(N0->getOperand(1));
     if (!Cst || !ShlCst)
       break;
 
@@ -2514,7 +2512,7 @@
         N0.getNode()->hasOneUse() &&
         N0.getValueType() != MVT::i8 &&
         X86::isZeroNode(N1)) {
-      ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getNode()->getOperand(1));
+      auto *C = dyn_cast<ConstantIntSDNode>(N0.getNode()->getOperand(1));
       if (!C) break;
 
       // For example, convert "testl %eax, $8" to "testb %al, $8"
Index: llvm/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -3979,7 +3979,7 @@
                                bool isFP, SDValue &LHS, SDValue &RHS,
                                SelectionDAG &DAG) {
   if (!isFP) {
-    if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) {
+    if (auto *RHSC = dyn_cast<ConstantIntSDNode>(RHS)) {
       if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) {
         // X > -1   -> X == 0, jump !sign.
         RHS = DAG.getConstant(0, DL, RHS.getValueType());
@@ -4274,12 +4274,12 @@
 /// extract that is suitable for instruction that extract 128 or 256 bit vectors
 static bool isVEXTRACTIndex(SDNode *N, unsigned vecWidth) {
   assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
-  if (!isa<ConstantSDNode>(N->getOperand(1).getNode()))
+  if (!isa<ConstantIntSDNode>(N->getOperand(1).getNode()))
     return false;
 
   // The index should be aligned on a vecWidth-bit boundary.
   uint64_t Index =
-    cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
+      cast<ConstantIntSDNode>(N->getOperand(1).getNode())->getZExtValue();
 
   MVT VT = N->getSimpleValueType(0);
   unsigned ElSize = VT.getScalarSizeInBits();
@@ -4293,11 +4293,11 @@
 /// insertion of 128 or 256-bit subvectors
 static bool isVINSERTIndex(SDNode *N, unsigned vecWidth) {
   assert((vecWidth == 128 || vecWidth == 256) && "Unexpected vector width");
-  if (!isa<ConstantSDNode>(N->getOperand(2).getNode()))
+  if (!isa<ConstantIntSDNode>(N->getOperand(2).getNode()))
     return false;
   // The index should be aligned on a vecWidth-bit boundary.
   uint64_t Index =
-    cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
+      cast<ConstantIntSDNode>(N->getOperand(2).getNode())->getZExtValue();
 
   MVT VT = N->getSimpleValueType(0);
   unsigned ElSize = VT.getScalarSizeInBits();
@@ -4324,11 +4324,11 @@
 
 static unsigned getExtractVEXTRACTImmediate(SDNode *N, unsigned vecWidth) {
   assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
-  assert(isa<ConstantSDNode>(N->getOperand(1).getNode()) &&
+  assert(isa<ConstantIntSDNode>(N->getOperand(1).getNode()) &&
          "Illegal extract subvector for VEXTRACT");
 
   uint64_t Index =
-    cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
+      cast<ConstantIntSDNode>(N->getOperand(1).getNode())->getZExtValue();
 
   MVT VecVT = N->getOperand(0).getSimpleValueType();
   MVT ElVT = VecVT.getVectorElementType();
@@ -4339,11 +4339,11 @@
 
 static unsigned getInsertVINSERTImmediate(SDNode *N, unsigned vecWidth) {
   assert((vecWidth == 128 || vecWidth == 256) && "Unsupported vector width");
-  assert(isa<ConstantSDNode>(N->getOperand(2).getNode()) &&
+  assert(isa<ConstantIntSDNode>(N->getOperand(2).getNode()) &&
          "Illegal insert subvector for VINSERT");
 
   uint64_t Index =
-    cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
+      cast<ConstantIntSDNode>(N->getOperand(2).getNode())->getZExtValue();
 
   MVT VecVT = N->getSimpleValueType(0);
   MVT ElVT = VecVT.getVectorElementType();
@@ -4584,10 +4584,10 @@
   SDValue SubVec = Op.getOperand(1);
   SDValue Idx = Op.getOperand(2);
 
-  if (!isa<ConstantSDNode>(Idx))
+  if (!isa<ConstantIntSDNode>(Idx))
     return SDValue();
 
-  unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
+  unsigned IdxVal = cast<ConstantIntSDNode>(Idx)->getZExtValue();
   if (IdxVal == 0  && Vec.isUndef()) // the operation is legal
     return Op;
 
@@ -4803,7 +4803,7 @@
     // TODO: Handle (VT.getScalarSizeInBits() % MaskEltSizeInBits) == 0
     if (VT.getScalarSizeInBits() != MaskEltSizeInBits)
       return false;
-    if (auto *CN = dyn_cast<ConstantSDNode>(MaskNode.getOperand(0))) {
+    if (auto *CN = dyn_cast<ConstantIntSDNode>(MaskNode.getOperand(0))) {
       const APInt &MaskElement = CN->getAPIntValue();
       for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
         APInt RawElt = MaskElement.getLoBits(MaskEltSizeInBits);
@@ -4816,7 +4816,7 @@
   if (MaskNode.getOpcode() == X86ISD::VZEXT_MOVL &&
       MaskNode.getOperand(0).getOpcode() == ISD::SCALAR_TO_VECTOR) {
     SDValue MaskOp = MaskNode.getOperand(0).getOperand(0);
-    if (auto *CN = dyn_cast<ConstantSDNode>(MaskOp)) {
+    if (auto *CN = dyn_cast<ConstantIntSDNode>(MaskOp)) {
       if ((MaskEltSizeInBits % VT.getScalarSizeInBits()) == 0) {
         RawMask.push_back(CN->getZExtValue());
         RawMask.append(NumMaskElts - 1, 0);
@@ -4848,7 +4848,7 @@
     return false;
 
   for (SDValue Op : MaskNode->ops()) {
-    if (auto *CN = dyn_cast<ConstantSDNode>(Op.getNode()))
+    if (auto *CN = dyn_cast<ConstantIntSDNode>(Op.getNode()))
       SplitElementToMask(CN->getAPIntValue());
     else if (auto *CFN = dyn_cast<ConstantFPSDNode>(Op.getNode()))
       SplitElementToMask(CFN->getValueAPF().bitcastToAPInt());
@@ -4899,16 +4899,16 @@
   switch(N->getOpcode()) {
   case X86ISD::BLENDI:
     ImmN = N->getOperand(N->getNumOperands()-1);
-    DecodeBLENDMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
+    DecodeBLENDMask(VT, cast<ConstantIntSDNode>(ImmN)->getZExtValue(), Mask);
     break;
   case X86ISD::SHUFP:
     ImmN = N->getOperand(N->getNumOperands()-1);
-    DecodeSHUFPMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
+    DecodeSHUFPMask(VT, cast<ConstantIntSDNode>(ImmN)->getZExtValue(), Mask);
     IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
     break;
   case X86ISD::INSERTPS:
     ImmN = N->getOperand(N->getNumOperands()-1);
-    DecodeINSERTPSMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
+    DecodeINSERTPSMask(cast<ConstantIntSDNode>(ImmN)->getZExtValue(), Mask);
     IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
     break;
   case X86ISD::UNPCKH:
@@ -4930,7 +4930,7 @@
   case X86ISD::PALIGNR:
     assert(VT.getScalarType() == MVT::i8 && "Byte vector expected");
     ImmN = N->getOperand(N->getNumOperands()-1);
-    DecodePALIGNRMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
+    DecodePALIGNRMask(VT, cast<ConstantIntSDNode>(ImmN)->getZExtValue(), Mask);
     IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
     Ops.push_back(N->getOperand(1));
     Ops.push_back(N->getOperand(0));
@@ -4938,29 +4938,29 @@
   case X86ISD::VSHLDQ:
     assert(VT.getScalarType() == MVT::i8 && "Byte vector expected");
     ImmN = N->getOperand(N->getNumOperands() - 1);
-    DecodePSLLDQMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
+    DecodePSLLDQMask(VT, cast<ConstantIntSDNode>(ImmN)->getZExtValue(), Mask);
     IsUnary = true;
     break;
   case X86ISD::VSRLDQ:
     assert(VT.getScalarType() == MVT::i8 && "Byte vector expected");
     ImmN = N->getOperand(N->getNumOperands() - 1);
-    DecodePSRLDQMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
+    DecodePSRLDQMask(VT, cast<ConstantIntSDNode>(ImmN)->getZExtValue(), Mask);
     IsUnary = true;
     break;
   case X86ISD::PSHUFD:
   case X86ISD::VPERMILPI:
     ImmN = N->getOperand(N->getNumOperands()-1);
-    DecodePSHUFMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
+    DecodePSHUFMask(VT, cast<ConstantIntSDNode>(ImmN)->getZExtValue(), Mask);
     IsUnary = true;
     break;
   case X86ISD::PSHUFHW:
     ImmN = N->getOperand(N->getNumOperands()-1);
-    DecodePSHUFHWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
+    DecodePSHUFHWMask(VT, cast<ConstantIntSDNode>(ImmN)->getZExtValue(), Mask);
     IsUnary = true;
     break;
   case X86ISD::PSHUFLW:
     ImmN = N->getOperand(N->getNumOperands()-1);
-    DecodePSHUFLWMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
+    DecodePSHUFLWMask(VT, cast<ConstantIntSDNode>(ImmN)->getZExtValue(), Mask);
     IsUnary = true;
     break;
   case X86ISD::VZEXT_MOVL:
@@ -5007,7 +5007,7 @@
   }
   case X86ISD::VPERMI:
     ImmN = N->getOperand(N->getNumOperands()-1);
-    DecodeVPERMMask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
+    DecodeVPERMMask(VT, cast<ConstantIntSDNode>(ImmN)->getZExtValue(), Mask);
     IsUnary = true;
     break;
   case X86ISD::MOVSS:
@@ -5016,7 +5016,8 @@
     break;
   case X86ISD::VPERM2X128:
     ImmN = N->getOperand(N->getNumOperands()-1);
-    DecodeVPERM2X128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), Mask);
+    DecodeVPERM2X128Mask(VT, cast<ConstantIntSDNode>(ImmN)->getZExtValue(),
+                         Mask);
     IsUnary = IsFakeUnary = N->getOperand(0) == N->getOperand(1);
     break;
   case X86ISD::MOVSLDUP:
@@ -5041,7 +5042,7 @@
     unsigned MaskEltSize = VT.getScalarSizeInBits();
     SDValue MaskNode = N->getOperand(2);
     SDValue CtrlNode = N->getOperand(3);
-    if (ConstantSDNode *CtrlOp = dyn_cast<ConstantSDNode>(CtrlNode)) {
+    if (auto *CtrlOp = dyn_cast<ConstantIntSDNode>(CtrlNode)) {
       unsigned CtrlImm = CtrlOp->getZExtValue();
       SmallVector<uint64_t, 32> RawMask;
       if (getTargetShuffleMaskIndices(MaskNode, MaskEltSize, RawMask)) {
@@ -5429,7 +5430,7 @@
       continue;
     SDValue Elt = Op->getOperand(i);
     if (Elt.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
-        !isa<ConstantSDNode>(Elt.getOperand(1)))
+        !isa<ConstantIntSDNode>(Elt.getOperand(1)))
       return SDValue();
     // Make sure that this node is extracting from a 128-bit vector.
     MVT VT = Elt.getOperand(0).getSimpleValueType();
@@ -5458,7 +5459,7 @@
 
     Elt = Op->getOperand(EltIdx);
     // By construction, Elt is a EXTRACT_VECTOR_ELT with constant index.
-    EltMaskIdx = cast<ConstantSDNode>(Elt.getOperand(1))->getZExtValue();
+    EltMaskIdx = cast<ConstantIntSDNode>(Elt.getOperand(1))->getZExtValue();
     if (Elt.getOperand(0) != V1 || EltMaskIdx != EltIdx)
       break;
     Mask[EltIdx] = EltIdx;
@@ -5489,8 +5490,9 @@
     SDValue SrcVector = Current->getOperand(0);
     if (!V1.getNode())
       V1 = SrcVector;
-    CanFold = SrcVector == V1 &&
-      cast<ConstantSDNode>(Current.getOperand(1))->getZExtValue() == i;
+    CanFold =
+        SrcVector == V1 &&
+        cast<ConstantIntSDNode>(Current.getOperand(1))->getZExtValue() == i;
   }
 
   if (!CanFold)
@@ -5886,7 +5888,7 @@
     if (ScalarSize == 32 || (IsGE256 && ScalarSize == 64) ||
         (OptForSize && (ScalarSize == 64 || Subtarget.hasAVX2()))) {
       const Constant *C = nullptr;
-      if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(Ld))
+      if (auto *CI = dyn_cast<ConstantIntSDNode>(Ld))
         C = CI->getConstantIntValue();
       else if (ConstantFPSDNode *CF = dyn_cast<ConstantFPSDNode>(Ld))
         C = CF->getConstantFPValue();
@@ -5939,7 +5941,7 @@
 /// index.
 static int getUnderlyingExtractedFromVec(SDValue &ExtractedFromVec,
                                          SDValue ExtIdx) {
-  int Idx = cast<ConstantSDNode>(ExtIdx)->getZExtValue();
+  int Idx = cast<ConstantIntSDNode>(ExtIdx)->getZExtValue();
   if (!isa<ShuffleVectorSDNode>(ExtractedFromVec))
     return Idx;
 
@@ -6001,7 +6003,7 @@
     SDValue ExtractedFromVec = Op.getOperand(i).getOperand(0);
     SDValue ExtIdx = Op.getOperand(i).getOperand(1);
     // Quit if non-constant index.
-    if (!isa<ConstantSDNode>(ExtIdx))
+    if (!isa<ConstantIntSDNode>(ExtIdx))
       return SDValue();
     int Idx = getUnderlyingExtractedFromVec(ExtractedFromVec, ExtIdx);
 
@@ -6040,14 +6042,14 @@
 }
 
 static SDValue ConvertI1VectorToInteger(SDValue Op, SelectionDAG &DAG) {
-  assert(ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) &&
+  assert(ISD::isBuildVectorOfConstantIntSDNodes(Op.getNode()) &&
          Op.getScalarValueSizeInBits() == 1 &&
          "Can not convert non-constant vector");
   uint64_t Immediate = 0;
   for (unsigned idx = 0, e = Op.getNumOperands(); idx < e; ++idx) {
     SDValue In = Op.getOperand(idx);
     if (!In.isUndef())
-      Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
+      Immediate |= cast<ConstantIntSDNode>(In)->getZExtValue() << idx;
   }
   SDLoc dl(Op);
   MVT VT = MVT::getIntegerVT(std::max((int)Op.getValueSizeInBits(), 8));
@@ -6068,7 +6070,7 @@
   if (ISD::isBuildVectorAllOnes(Op.getNode()))
     return DAG.getTargetConstant(1, dl, VT);
 
-  if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
+  if (ISD::isBuildVectorOfConstantIntSDNodes(Op.getNode())) {
     SDValue Imm = ConvertI1VectorToInteger(Op, DAG);
     if (Imm.getValueSizeInBits() == VT.getSizeInBits())
       return DAG.getBitcast(VT, Imm);
@@ -6087,10 +6089,10 @@
     SDValue In = Op.getOperand(idx);
     if (In.isUndef())
       continue;
-    if (!isa<ConstantSDNode>(In))
+    if (!isa<ConstantIntSDNode>(In))
       NonConstIdx.push_back(idx);
     else {
-      Immediate |= cast<ConstantSDNode>(In)->getZExtValue() << idx;
+      Immediate |= cast<ConstantIntSDNode>(In)->getZExtValue() << idx;
       HasConstElts = true;
     }
     if (SplatIdx < 0)
@@ -6188,15 +6190,15 @@
     // Try to match the following pattern:
     // (BINOP (extract_vector_elt A, I), (extract_vector_elt A, I+1))
     CanFold = (Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
-        Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
-        Op0.getOperand(0) == Op1.getOperand(0) &&
-        isa<ConstantSDNode>(Op0.getOperand(1)) &&
-        isa<ConstantSDNode>(Op1.getOperand(1)));
+               Op1.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
+               Op0.getOperand(0) == Op1.getOperand(0) &&
+               isa<ConstantIntSDNode>(Op0.getOperand(1)) &&
+               isa<ConstantIntSDNode>(Op1.getOperand(1)));
     if (!CanFold)
       break;
 
-    unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
-    unsigned I1 = cast<ConstantSDNode>(Op1.getOperand(1))->getZExtValue();
+    unsigned I0 = cast<ConstantIntSDNode>(Op0.getOperand(1))->getZExtValue();
+    unsigned I1 = cast<ConstantIntSDNode>(Op1.getOperand(1))->getZExtValue();
 
     if (i * 2 < NumElts) {
       if (V0.isUndef()) {
@@ -6345,12 +6347,12 @@
     // Early exit if we cannot match that sequence.
     if (Op0.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
         Op1.getOpcode() != ISD::EXTRACT_VECTOR_ELT ||
-        !isa<ConstantSDNode>(Op0.getOperand(1)) ||
-        !isa<ConstantSDNode>(Op1.getOperand(1)) ||
+        !isa<ConstantIntSDNode>(Op0.getOperand(1)) ||
+        !isa<ConstantIntSDNode>(Op1.getOperand(1)) ||
         Op0.getOperand(1) != Op1.getOperand(1))
       return SDValue();
 
-    unsigned I0 = cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue();
+    unsigned I0 = cast<ConstantIntSDNode>(Op0.getOperand(1))->getZExtValue();
     if (I0 != i)
       return SDValue();
 
@@ -6565,7 +6567,7 @@
     SDValue RHS = Elt.getOperand(1);
 
     // We expect the canonicalized RHS operand to be the constant.
-    if (!isa<ConstantSDNode>(RHS))
+    if (!isa<ConstantIntSDNode>(RHS))
       return SDValue();
     LHSElts.push_back(LHS);
     RHSElts.push_back(RHS);
@@ -7298,7 +7300,7 @@
       SDValue Op = V.getOperand(M / Scale);
       if (Op.isUndef() || X86::isZeroNode(Op))
         Zeroable[i] = true;
-      else if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(Op)) {
+      else if (auto *Cst = dyn_cast<ConstantIntSDNode>(Op)) {
         APInt Val = Cst->getAPIntValue();
         Val = Val.lshr((M % Scale) * ScalarSizeInBits);
         Val = Val.getLoBits(ScalarSizeInBits);
@@ -8637,7 +8639,7 @@
     }
     case ISD::INSERT_SUBVECTOR: {
       SDValue VOuter = V.getOperand(0), VInner = V.getOperand(1);
-      auto ConstantIdx = dyn_cast<ConstantSDNode>(V.getOperand(2));
+      auto ConstantIdx = dyn_cast<ConstantIntSDNode>(V.getOperand(2));
       if (!ConstantIdx)
         break;
 
@@ -12419,7 +12421,7 @@
   SDLoc dl(Op);
   MVT VT = Op.getSimpleValueType();
 
-  if (!ISD::isBuildVectorOfConstantSDNodes(Cond.getNode()))
+  if (!ISD::isBuildVectorOfConstantIntSDNodes(Cond.getNode()))
     return SDValue();
   auto *CondBV = cast<BuildVectorSDNode>(Cond);
 
@@ -12428,9 +12430,9 @@
   SmallVector<int, 32> Mask;
   for (int i = 0, Size = VT.getVectorNumElements(); i < Size; ++i) {
     SDValue CondElt = CondBV->getOperand(i);
-    Mask.push_back(
-        isa<ConstantSDNode>(CondElt) ? i + (isNullConstant(CondElt) ? Size : 0)
-                                     : -1);
+    Mask.push_back(isa<ConstantIntSDNode>(CondElt)
+                       ? i + (isNullConstant(CondElt) ? Size : 0)
+                       : -1);
   }
   return DAG.getVectorShuffle(VT, dl, LHS, RHS, Mask);
 }
@@ -12438,9 +12440,9 @@
 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
   // A vselect where all conditions and data are constants can be optimized into
   // a single vector load by SelectionDAGLegalize::ExpandBUILD_VECTOR().
-  if (ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(0).getNode()) &&
-      ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(1).getNode()) &&
-      ISD::isBuildVectorOfConstantSDNodes(Op.getOperand(2).getNode()))
+  if (ISD::isBuildVectorOfConstantIntSDNodes(Op.getOperand(0).getNode()) &&
+      ISD::isBuildVectorOfConstantIntSDNodes(Op.getOperand(1).getNode()) &&
+      ISD::isBuildVectorOfConstantIntSDNodes(Op.getOperand(2).getNode()))
     return SDValue();
 
   // Try to lower this to a blend-style vector shuffle. This can handle all
@@ -12516,7 +12518,7 @@
 
   if (VT == MVT::i32 || VT == MVT::i64) {
     // ExtractPS/pextrq works with constant index.
-    if (isa<ConstantSDNode>(Op.getOperand(1)))
+    if (isa<ConstantIntSDNode>(Op.getOperand(1)))
       return Op;
   }
 
@@ -12539,7 +12541,7 @@
 
   // variable index can't be handled in mask registers,
   // extend vector to VR512
-  if (!isa<ConstantSDNode>(Idx)) {
+  if (!isa<ConstantIntSDNode>(Idx)) {
     MVT ExtVT = (VecVT == MVT::v8i1 ?  MVT::v8i64 : MVT::v16i32);
     SDValue Ext = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtVT, Vec);
     SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
@@ -12547,7 +12549,7 @@
     return DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
   }
 
-  unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
+  unsigned IdxVal = cast<ConstantIntSDNode>(Idx)->getZExtValue();
   if ((!Subtarget.hasDQI() && (VecVT.getVectorNumElements() == 8)) ||
       (VecVT.getVectorNumElements() < 8)) {
     // Use kshiftlw/rw instruction.
@@ -12578,7 +12580,7 @@
   if (Op.getSimpleValueType() == MVT::i1)
     return ExtractBitFromMaskVector(Op, DAG);
 
-  if (!isa<ConstantSDNode>(Idx)) {
+  if (!isa<ConstantIntSDNode>(Idx)) {
     if (VecVT.is512BitVector() ||
         (VecVT.is256BitVector() && Subtarget.hasInt256() &&
          VecVT.getScalarSizeInBits() == 32)) {
@@ -12600,7 +12602,7 @@
     return SDValue();
   }
 
-  unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
+  unsigned IdxVal = cast<ConstantIntSDNode>(Idx)->getZExtValue();
 
   // If this is a 256-bit vector result, first extract the 128-bit vector and
   // then extract the element from the 128-bit vector.
@@ -12686,7 +12688,7 @@
   SDValue Idx = Op.getOperand(2);
   MVT VecVT = Vec.getSimpleValueType();
 
-  if (!isa<ConstantSDNode>(Idx)) {
+  if (!isa<ConstantIntSDNode>(Idx)) {
     // Non constant index. Extend source and destination,
     // insert element and then truncate the result.
     MVT ExtVecVT = (VecVT == MVT::v8i1 ?  MVT::v8i64 : MVT::v16i32);
@@ -12697,7 +12699,7 @@
     return DAG.getNode(ISD::TRUNCATE, dl, VecVT, ExtOp);
   }
 
-  unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
+  unsigned IdxVal = cast<ConstantIntSDNode>(Idx)->getZExtValue();
   SDValue EltInVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Elt);
   unsigned NumElems = VecVT.getVectorNumElements();
 
@@ -12754,9 +12756,9 @@
   SDValue N0 = Op.getOperand(0);
   SDValue N1 = Op.getOperand(1);
   SDValue N2 = Op.getOperand(2);
-  if (!isa<ConstantSDNode>(N2))
+  if (!isa<ConstantIntSDNode>(N2))
     return SDValue();
-  auto *N2C = cast<ConstantSDNode>(N2);
+  auto *N2C = cast<ConstantIntSDNode>(N2);
   unsigned IdxVal = N2C->getZExtValue();
 
   // If we are clearing out a element, we do this more efficiently with a
@@ -12907,18 +12909,18 @@
   SDLoc dl(Op);
   SDValue In =  Op.getOperand(0);
   SDValue Idx = Op.getOperand(1);
-  unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
+  unsigned IdxVal = cast<ConstantIntSDNode>(Idx)->getZExtValue();
   MVT ResVT   = Op.getSimpleValueType();
   MVT InVT    = In.getSimpleValueType();
 
   if (Subtarget.hasFp256()) {
     if (ResVT.is128BitVector() &&
         (InVT.is256BitVector() || InVT.is512BitVector()) &&
-        isa<ConstantSDNode>(Idx)) {
+        isa<ConstantIntSDNode>(Idx)) {
       return extract128BitVector(In, IdxVal, DAG, dl);
     }
     if (ResVT.is256BitVector() && InVT.is512BitVector() &&
-        isa<ConstantSDNode>(Idx)) {
+        isa<ConstantIntSDNode>(Idx)) {
       return extract256BitVector(In, IdxVal, DAG, dl);
     }
   }
@@ -12946,10 +12948,10 @@
   SDValue SubVec = Op.getOperand(1);
   SDValue Idx = Op.getOperand(2);
 
-  if (!isa<ConstantSDNode>(Idx))
+  if (!isa<ConstantIntSDNode>(Idx))
     return SDValue();
 
-  unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
+  unsigned IdxVal = cast<ConstantIntSDNode>(Idx)->getZExtValue();
   MVT OpVT = Op.getSimpleValueType();
   MVT SubVecVT = SubVec.getSimpleValueType();
 
@@ -12964,7 +12966,7 @@
   if ((IdxVal == OpVT.getVectorNumElements() / 2) &&
       Vec.getOpcode() == ISD::INSERT_SUBVECTOR &&
       OpVT.is256BitVector() && SubVecVT.is128BitVector()) {
-    auto *Idx2 = dyn_cast<ConstantSDNode>(Vec.getOperand(2));
+    auto *Idx2 = dyn_cast<ConstantIntSDNode>(Vec.getOperand(2));
     if (Idx2 && Idx2->getZExtValue() == 0) {
       SDValue SubVec2 = Vec.getOperand(1);
       // If needed, look through bitcasts to get to the load.
@@ -14787,7 +14789,7 @@
 
     // Quit if without a constant index.
     SDValue Idx = I->getOperand(1);
-    if (!isa<ConstantSDNode>(Idx))
+    if (!isa<ConstantIntSDNode>(Idx))
       return SDValue();
 
     SDValue ExtractedFromVec = I->getOperand(0);
@@ -14804,7 +14806,7 @@
       M = VecInMap.insert(std::make_pair(ExtractedFromVec, 0)).first;
       VecIns.push_back(ExtractedFromVec);
     }
-    M->second |= 1U << cast<ConstantSDNode>(Idx)->getZExtValue();
+    M->second |= 1U << cast<ConstantIntSDNode>(Idx)->getZExtValue();
   }
 
   assert((VT.is128BitVector() || VT.is256BitVector()) &&
@@ -14974,8 +14976,8 @@
           UI->getOpcode() != ISD::STORE)
         goto default_case;
 
-    if (ConstantSDNode *C =
-        dyn_cast<ConstantSDNode>(ArithOp.getNode()->getOperand(1))) {
+    if (auto *C =
+            dyn_cast<ConstantIntSDNode>(ArithOp.getNode()->getOperand(1))) {
       // An add of one will be selected as an INC.
       if (C->isOne() && !Subtarget.slowIncDec()) {
         Opcode = X86ISD::INC;
@@ -15001,7 +15003,7 @@
     // against zero turn it into an equivalent AND. This allows turning it into
     // a TEST instruction later.
     if ((X86CC == X86::COND_E || X86CC == X86::COND_NE) && Op->hasOneUse() &&
-        isa<ConstantSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
+        isa<ConstantIntSDNode>(Op->getOperand(1)) && !hasNonFlagsUse(Op)) {
       EVT VT = Op.getValueType();
       unsigned BitWidth = VT.getSizeInBits();
       unsigned ShAmt = Op->getConstantOperandVal(1);
@@ -15127,7 +15129,7 @@
   if (isNullConstant(Op1))
     return EmitTest(Op0, X86CC, dl, DAG);
 
-  assert(!(isa<ConstantSDNode>(Op1) && Op0.getValueType() == MVT::i1) &&
+  assert(!(isa<ConstantIntSDNode>(Op1) && Op0.getValueType() == MVT::i1) &&
          "Unexpected comparison operation for MVT::i1 operands");
 
   if ((Op0.getValueType() == MVT::i8 || Op0.getValueType() == MVT::i16 ||
@@ -15135,7 +15137,7 @@
     // Only promote the compare up to I32 if it is a 16 bit operation
     // with an immediate.  16 bit immediates are to be avoided.
     if ((Op0.getValueType() == MVT::i16 &&
-         (isa<ConstantSDNode>(Op0) || isa<ConstantSDNode>(Op1))) &&
+         (isa<ConstantIntSDNode>(Op0) || isa<ConstantIntSDNode>(Op1))) &&
         !DAG.getMachineFunction().getFunction()->optForMinSize() &&
         !Subtarget.isAtom()) {
       unsigned ExtendOp =
@@ -15318,7 +15320,7 @@
       RHS = Op0.getOperand(1);
     }
   } else if (Op1.getOpcode() == ISD::Constant) {
-    ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1);
+    auto *AndRHS = cast<ConstantIntSDNode>(Op1);
     uint64_t AndRHSVal = AndRHS->getZExtValue();
     SDValue AndLHS = Op0;
 
@@ -15538,7 +15540,7 @@
   SmallVector<SDValue, 8> ULTOp1;
 
   for (unsigned i = 0; i < n; ++i) {
-    ConstantSDNode *Elt = dyn_cast<ConstantSDNode>(BV->getOperand(i));
+    auto *Elt = dyn_cast<ConstantIntSDNode>(BV->getOperand(i));
     if (!Elt || Elt->isOpaque() || Elt->getSimpleValueType(0) != EVT)
       return SDValue();
 
@@ -16070,12 +16072,12 @@
 
   if (VT.isVector() && VT.getVectorElementType() == MVT::i1) {
     SDValue Op1Scalar;
-    if (ISD::isBuildVectorOfConstantSDNodes(Op1.getNode()))
+    if (ISD::isBuildVectorOfConstantIntSDNodes(Op1.getNode()))
       Op1Scalar = ConvertI1VectorToInteger(Op1, DAG);
     else if (Op1.getOpcode() == ISD::BITCAST && Op1.getOperand(0))
       Op1Scalar = Op1.getOperand(0);
     SDValue Op2Scalar;
-    if (ISD::isBuildVectorOfConstantSDNodes(Op2.getNode()))
+    if (ISD::isBuildVectorOfConstantIntSDNodes(Op2.getNode()))
       Op2Scalar = ConvertI1VectorToInteger(Op2, DAG);
     else if (Op2.getOpcode() == ISD::BITCAST && Op2.getOperand(0))
       Op2Scalar = Op2.getOperand(0);
@@ -16116,7 +16118,8 @@
       isNullConstant(Cond.getOperand(1).getOperand(1))) {
     SDValue Cmp = Cond.getOperand(1);
 
-    unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue();
+    unsigned CondCode =
+        cast<ConstantIntSDNode>(Cond.getOperand(0))->getZExtValue();
 
     if ((isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
         (CondCode == X86::COND_E || CondCode == X86::COND_NE)) {
@@ -16176,7 +16179,7 @@
     bool IllegalFPCMov = false;
     if (VT.isFloatingPoint() && !VT.isVector() &&
         !isScalarFPTypeInSSEReg(VT))  // FPStack?
-      IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue());
+      IllegalFPCMov = !hasFPCMov(cast<ConstantIntSDNode>(CC)->getSExtValue());
 
     if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) ||
         Opc == X86ISD::BT) { // FIXME
@@ -16245,7 +16248,7 @@
   // a >= b ?  0 : -1 -> RES = ~setcc_carry
   if (Cond.getOpcode() == X86ISD::SUB) {
     Cond = ConvertCmpIfNecessary(Cond, DAG);
-    unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue();
+    unsigned CondCode = cast<ConstantIntSDNode>(CC)->getZExtValue();
 
     if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) &&
         (isAllOnesConstant(Op1) || isAllOnesConstant(Op2)) &&
@@ -16865,7 +16868,7 @@
       Cond = Cmp;
       addTest = false;
     } else {
-      switch (cast<ConstantSDNode>(CC)->getZExtValue()) {
+      switch (cast<ConstantIntSDNode>(CC)->getZExtValue()) {
       default: break;
       case X86::COND_O:
       case X86::COND_B:
@@ -17097,7 +17100,7 @@
   SDNode *Node = Op.getNode();
   SDValue Chain = Op.getOperand(0);
   SDValue Size  = Op.getOperand(1);
-  unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
+  unsigned Align = cast<ConstantIntSDNode>(Op.getOperand(2))->getZExtValue();
   EVT VT = Node->getValueType(0);
 
   // Chain the dynamic stack allocation so that it doesn't modify the stack
@@ -17333,10 +17336,10 @@
   // Fold this packed vector shift into a build vector if SrcOp is a
   // vector of Constants or UNDEFs, and SrcOp valuetype is the same as VT.
   if (VT == SrcOp.getSimpleValueType() &&
-      ISD::isBuildVectorOfConstantSDNodes(SrcOp.getNode())) {
+      ISD::isBuildVectorOfConstantIntSDNodes(SrcOp.getNode())) {
     SmallVector<SDValue, 8> Elts;
     unsigned NumElts = SrcOp->getNumOperands();
-    ConstantSDNode *ND;
+    ConstantIntSDNode *ND;
 
     switch(Opc) {
     default: llvm_unreachable("Unknown opcode!");
@@ -17347,7 +17350,7 @@
           Elts.push_back(CurrentOp);
           continue;
         }
-        ND = cast<ConstantSDNode>(CurrentOp);
+        ND = cast<ConstantIntSDNode>(CurrentOp);
         const APInt &C = ND->getAPIntValue();
         Elts.push_back(DAG.getConstant(C.shl(ShiftAmt), dl, ElementType));
       }
@@ -17359,7 +17362,7 @@
           Elts.push_back(CurrentOp);
           continue;
         }
-        ND = cast<ConstantSDNode>(CurrentOp);
+        ND = cast<ConstantIntSDNode>(CurrentOp);
         const APInt &C = ND->getAPIntValue();
         Elts.push_back(DAG.getConstant(C.lshr(ShiftAmt), dl, ElementType));
       }
@@ -17371,7 +17374,7 @@
           Elts.push_back(CurrentOp);
           continue;
         }
-        ND = cast<ConstantSDNode>(CurrentOp);
+        ND = cast<ConstantIntSDNode>(CurrentOp);
         const APInt &C = ND->getAPIntValue();
         Elts.push_back(DAG.getConstant(C.ashr(ShiftAmt), dl, ElementType));
       }
@@ -17394,7 +17397,7 @@
   assert((SVT == MVT::i32 || SVT == MVT::i64) && "Unexpected value type!");
 
   // Catch shift-by-constant.
-  if (ConstantSDNode *CShAmt = dyn_cast<ConstantSDNode>(ShAmt))
+  if (auto *CShAmt = dyn_cast<ConstantIntSDNode>(ShAmt))
     return getTargetVShiftByConstNode(Opc, dl, VT, SrcOp,
                                       CShAmt->getZExtValue(), DAG);
 
@@ -17625,7 +17628,7 @@
 static SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, const X86Subtarget &Subtarget,
                                        SelectionDAG &DAG) {
   SDLoc dl(Op);
-  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned IntNo = cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
   MVT VT = Op.getSimpleValueType();
   const IntrinsicData* IntrData = getIntrinsicWithoutChain(IntNo);
   if (IntrData) {
@@ -17669,7 +17672,7 @@
       unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
       if (IntrWithRoundingModeOpcode != 0) {
         SDValue Rnd = Op.getOperand(4);
-        unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
+        unsigned Round = cast<ConstantIntSDNode>(Rnd)->getZExtValue();
         if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
           return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
                                       dl, Op.getValueType(),
@@ -17725,7 +17728,7 @@
       unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
       if (IntrWithRoundingModeOpcode != 0) {
         SDValue Rnd = Op.getOperand(5);
-        unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
+        unsigned Round = cast<ConstantIntSDNode>(Rnd)->getZExtValue();
         if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
           return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
                                       dl, Op.getValueType(),
@@ -17799,8 +17802,9 @@
         Src3 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Src3);
       else if (IntrData->Type == INSERT_SUBVEC) {
         // imm should be adapted to ISD::INSERT_SUBVECTOR behavior
-        assert(isa<ConstantSDNode>(Src3) && "Expected a ConstantSDNode here!");
-        unsigned Imm = cast<ConstantSDNode>(Src3)->getZExtValue();
+        assert(isa<ConstantIntSDNode>(Src3) &&
+               "Expected a ConstantIntSDNode here!");
+        unsigned Imm = cast<ConstantIntSDNode>(Src3)->getZExtValue();
         Imm *= Src2.getSimpleValueType().getVectorNumElements();
         Src3 = DAG.getTargetConstant(Imm, dl, MVT::i32);
       }
@@ -17811,7 +17815,7 @@
       unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
       if (IntrWithRoundingModeOpcode != 0) {
         SDValue Rnd = Op.getOperand(6);
-        unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
+        unsigned Round = cast<ConstantIntSDNode>(Rnd)->getZExtValue();
         if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
           return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
                                       dl, Op.getValueType(),
@@ -17881,7 +17885,7 @@
       unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
       if (IntrWithRoundingModeOpcode != 0) {
         SDValue Rnd = Op.getOperand(5);
-        if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
+        if (cast<ConstantIntSDNode>(Rnd)->getZExtValue() !=
             X86::STATIC_ROUNDING::CUR_DIRECTION)
           return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
                                                   dl, Op.getValueType(),
@@ -17944,7 +17948,7 @@
       unsigned IntrWithRoundingModeOpcode = IntrData->Opc1;
       if (IntrWithRoundingModeOpcode != 0) {
         SDValue Rnd = Op.getOperand(4);
-        unsigned Round = cast<ConstantSDNode>(Rnd)->getZExtValue();
+        unsigned Round = cast<ConstantIntSDNode>(Rnd)->getZExtValue();
         if (Round != X86::STATIC_ROUNDING::CUR_DIRECTION) {
           return getVectorMaskingNode(DAG.getNode(IntrWithRoundingModeOpcode,
                                       dl, Op.getValueType(),
@@ -18011,7 +18015,7 @@
         // (IntrData->Opc1 != 0), then we check the rounding mode operand.
         if (IntrData->Opc1 != 0) {
           SDValue Rnd = Op.getOperand(5);
-          if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
+          if (cast<ConstantIntSDNode>(Rnd)->getZExtValue() !=
               X86::STATIC_ROUNDING::CUR_DIRECTION)
             Cmp = DAG.getNode(IntrData->Opc1, dl, MaskVT, Op.getOperand(1),
                               Op.getOperand(2), CC, Rnd);
@@ -18044,7 +18048,7 @@
       SDValue Cmp;
       if (IntrData->Opc1 != 0) {
         SDValue Rnd = Op.getOperand(5);
-        if (cast<ConstantSDNode>(Rnd)->getZExtValue() !=
+        if (cast<ConstantIntSDNode>(Rnd)->getZExtValue() !=
             X86::STATIC_ROUNDING::CUR_DIRECTION)
           Cmp = DAG.getNode(IntrData->Opc1, dl, MVT::i1, Src1, Src2, CC, Rnd);
       }
@@ -18110,11 +18114,12 @@
     case COMI_RM: { // Comparison intrinsics with Sae
       SDValue LHS = Op.getOperand(1);
       SDValue RHS = Op.getOperand(2);
-      unsigned CondVal = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
+      unsigned CondVal =
+          cast<ConstantIntSDNode>(Op.getOperand(3))->getZExtValue();
       SDValue Sae = Op.getOperand(4);
 
       SDValue FCmp;
-      if (cast<ConstantSDNode>(Sae)->getZExtValue() ==
+      if (cast<ConstantIntSDNode>(Sae)->getZExtValue() ==
           X86::STATIC_ROUNDING::CUR_DIRECTION)
         FCmp = DAG.getNode(X86ISD::FSETCCM, dl, MVT::i1, LHS, RHS,
                                   DAG.getConstant(CondVal, dl, MVT::i8));
@@ -18462,7 +18467,7 @@
                               SDValue Index, SDValue ScaleOp, SDValue Chain,
                               const X86Subtarget &Subtarget) {
   SDLoc dl(Op);
-  auto *C = cast<ConstantSDNode>(ScaleOp);
+  auto *C = cast<ConstantIntSDNode>(ScaleOp);
   SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
   MVT MaskVT = MVT::getVectorVT(MVT::i1,
                              Index.getSimpleValueType().getVectorNumElements());
@@ -18484,7 +18489,7 @@
                                SDValue Index, SDValue ScaleOp, SDValue Chain,
                                const X86Subtarget &Subtarget) {
   SDLoc dl(Op);
-  auto *C = cast<ConstantSDNode>(ScaleOp);
+  auto *C = cast<ConstantIntSDNode>(ScaleOp);
   SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
   SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
   SDValue Segment = DAG.getRegister(0, MVT::i32);
@@ -18503,7 +18508,7 @@
                                SDValue ScaleOp, SDValue Chain,
                                const X86Subtarget &Subtarget) {
   SDLoc dl(Op);
-  auto *C = cast<ConstantSDNode>(ScaleOp);
+  auto *C = cast<ConstantIntSDNode>(ScaleOp);
   SDValue Scale = DAG.getTargetConstant(C->getZExtValue(), dl, MVT::i8);
   SDValue Disp = DAG.getTargetConstant(0, dl, MVT::i32);
   SDValue Segment = DAG.getRegister(0, MVT::i32);
@@ -18709,7 +18714,7 @@
 
 static SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, const X86Subtarget &Subtarget,
                                       SelectionDAG &DAG) {
-  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
+  unsigned IntNo = cast<ConstantIntSDNode>(Op.getOperand(1))->getZExtValue();
 
   const IntrinsicData* IntrData = getIntrinsicWithChain(IntNo);
   if (!IntrData) {
@@ -18779,7 +18784,7 @@
   }
   case PREFETCH: {
     SDValue Hint = Op.getOperand(6);
-    unsigned HintVal = cast<ConstantSDNode>(Hint)->getZExtValue();
+    unsigned HintVal = cast<ConstantIntSDNode>(Hint)->getZExtValue();
     assert(HintVal < 2 && "Wrong prefetch hint in intrinsic: should be 0 or 1");
     unsigned Opcode = (HintVal ? IntrData->Opc1 : IntrData->Opc0);
     SDValue Chain = Op.getOperand(0);
@@ -18912,7 +18917,7 @@
   if (verifyReturnAddressArgumentIsConstant(Op, DAG))
     return SDValue();
 
-  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned Depth = cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
   SDLoc dl(Op);
   EVT PtrVT = getPointerTy(DAG.getDataLayout());
 
@@ -18958,7 +18963,7 @@
   unsigned FrameReg =
       RegInfo->getPtrSizedFrameRegister(DAG.getMachineFunction());
   SDLoc dl(Op);  // FIXME probably not meaningful
-  unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned Depth = cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
   assert(((FrameReg == X86::RBP && VT == MVT::i64) ||
           (FrameReg == X86::EBP && VT == MVT::i32)) &&
          "Invalid Frame Register!");
@@ -20230,7 +20235,7 @@
     uint64_t ShiftAmt = 0;
     unsigned BaseOp = (SplatIndex < 0 ? 0 : SplatIndex * Ratio);
     for (unsigned i = 0; i != Ratio; ++i) {
-      ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + BaseOp));
+      auto *C = dyn_cast<ConstantIntSDNode>(Amt.getOperand(i + BaseOp));
       if (!C)
         return SDValue();
       // 6 == Log2(64)
@@ -20242,7 +20247,7 @@
       for (unsigned i = Ratio; i != Amt.getNumOperands(); i += Ratio) {
         uint64_t ShAmt = 0;
         for (unsigned j = 0; j != Ratio; ++j) {
-          ConstantSDNode *C = dyn_cast<ConstantSDNode>(Amt.getOperand(i + j));
+          auto *C = dyn_cast<ConstantIntSDNode>(Amt.getOperand(i + j));
           if (!C)
             return SDValue();
           // 6 == Log2(64)
@@ -20299,10 +20304,9 @@
                  "Unexpected shuffle index found!");
           BaseShAmt = InVec.getOperand(SplatIdx);
         } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
-           if (ConstantSDNode *C =
-               dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
-             if (C->getZExtValue() == SplatIdx)
-               BaseShAmt = InVec.getOperand(1);
+          if (auto *C = dyn_cast<ConstantIntSDNode>(InVec.getOperand(2))) {
+            if (C->getZExtValue() == SplatIdx)
+              BaseShAmt = InVec.getOperand(1);
            }
         }
 
@@ -20352,7 +20356,7 @@
   SDLoc dl(Op);
   SDValue R = Op.getOperand(0);
   SDValue Amt = Op.getOperand(1);
-  bool ConstantAmt = ISD::isBuildVectorOfConstantSDNodes(Amt.getNode());
+  bool ConstantAmt = ISD::isBuildVectorOfConstantIntSDNodes(Amt.getNode());
 
   assert(VT.isVector() && "Custom lowering only for vector shifts!");
   assert(Subtarget.hasSSE2() && "Only custom lower when we have SSE2!");
@@ -20424,7 +20428,7 @@
         continue;
       }
 
-      ConstantSDNode *ND = cast<ConstantSDNode>(Op);
+      auto *ND = cast<ConstantIntSDNode>(Op);
       APInt C(SVTBits, ND->getAPIntValue().getZExtValue());
       uint64_t ShAmt = C.getZExtValue();
       if (ShAmt >= SVTBits) {
@@ -20499,15 +20503,15 @@
       }
     }
 
-    if (CanBeSimplified && isa<ConstantSDNode>(Amt1) &&
-        isa<ConstantSDNode>(Amt2)) {
+    if (CanBeSimplified && isa<ConstantIntSDNode>(Amt1) &&
+        isa<ConstantIntSDNode>(Amt2)) {
       // Replace this node with two shifts followed by a MOVSS/MOVSD/PBLEND.
       MVT CastVT = MVT::v4i32;
-      SDValue Splat1 =
-          DAG.getConstant(cast<ConstantSDNode>(Amt1)->getAPIntValue(), dl, VT);
+      SDValue Splat1 = DAG.getConstant(
+          cast<ConstantIntSDNode>(Amt1)->getAPIntValue(), dl, VT);
       SDValue Shift1 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat1);
-      SDValue Splat2 =
-          DAG.getConstant(cast<ConstantSDNode>(Amt2)->getAPIntValue(), dl, VT);
+      SDValue Splat2 = DAG.getConstant(
+          cast<ConstantIntSDNode>(Amt2)->getAPIntValue(), dl, VT);
       SDValue Shift2 = DAG.getNode(Op->getOpcode(), dl, VT, R, Splat2);
       SDValue BitCast1 = DAG.getBitcast(CastVT, Shift1);
       SDValue BitCast2 = DAG.getBitcast(CastVT, Shift2);
@@ -20711,7 +20715,7 @@
     // If we have a constant shift amount, the non-SSE41 path is best as
     // avoiding bitcasts make it easier to constant fold and reduce to PBLENDW.
     bool UseSSE41 = Subtarget.hasSSE41() &&
-                    !ISD::isBuildVectorOfConstantSDNodes(Amt.getNode());
+                    !ISD::isBuildVectorOfConstantIntSDNodes(Amt.getNode());
 
     auto SignBitSelect = [&](SDValue Sel, SDValue V0, SDValue V1) {
       // On SSE41 targets we make use of the fact that VSELECT lowers
@@ -21026,9 +21030,9 @@
                                  SelectionDAG &DAG) {
   SDLoc dl(Op);
   AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>(
-    cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue());
+      cast<ConstantIntSDNode>(Op.getOperand(1))->getZExtValue());
   SynchronizationScope FenceScope = static_cast<SynchronizationScope>(
-    cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
+      cast<ConstantIntSDNode>(Op.getOperand(2))->getZExtValue());
 
   // The only fence that needs an instruction is a sequentially-consistent
   // cross-thread fence.
@@ -21713,7 +21717,7 @@
       InNumElts = InVT.getVectorNumElements();
     }
   }
-  if (ISD::isBuildVectorOfConstantSDNodes(InOp.getNode()) ||
+  if (ISD::isBuildVectorOfConstantIntSDNodes(InOp.getNode()) ||
       ISD::isBuildVectorOfConstantFPSDNodes(InOp.getNode())) {
     SmallVector<SDValue, 16> Ops;
     for (unsigned i = 0; i < InNumElts; ++i)
@@ -22248,7 +22252,7 @@
     return;
   }
   case ISD::INTRINSIC_W_CHAIN: {
-    unsigned IntNo = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
+    unsigned IntNo = cast<ConstantIntSDNode>(N->getOperand(1))->getZExtValue();
     switch (IntNo) {
     default : llvm_unreachable("Do not know how to custom type "
                                "legalize this intrinsic operation!");
@@ -26159,7 +26163,7 @@
     // instruction because a MOVSD is 1-2 bytes smaller than a BLENDPD.
 
     if (VT == MVT::v2f64)
-      if (auto *Mask = dyn_cast<ConstantSDNode>(N->getOperand(2)))
+      if (auto *Mask = dyn_cast<ConstantIntSDNode>(N->getOperand(2)))
         if (Mask->getZExtValue() == 2 && !isShuffleFoldableLoad(V0)) {
           SDValue NewMask = DAG.getConstant(1, DL, MVT::i8);
           return DAG.getNode(X86ISD::BLENDI, DL, VT, V1, V0, NewMask);
@@ -26172,7 +26176,7 @@
     SDValue Op0 = N.getOperand(0);
     SDValue Op1 = N.getOperand(1);
     SDValue Op2 = N.getOperand(2);
-    unsigned InsertPSMask = cast<ConstantSDNode>(Op2)->getZExtValue();
+    unsigned InsertPSMask = cast<ConstantIntSDNode>(Op2)->getZExtValue();
     unsigned SrcIdx = (InsertPSMask >> 6) & 0x3;
     unsigned DstIdx = (InsertPSMask >> 4) & 0x3;
     unsigned ZeroMask = InsertPSMask & 0xF;
@@ -26570,7 +26574,7 @@
   SDValue EltNo = N->getOperand(1);
   EVT EltVT = N->getValueType(0);
 
-  if (!isa<ConstantSDNode>(EltNo))
+  if (!isa<ConstantIntSDNode>(EltNo))
     return SDValue();
 
   EVT OriginalVT = InVec.getValueType();
@@ -26604,7 +26608,7 @@
 
   // Select the input vector, guarding against out of range extract vector.
   unsigned NumElems = CurrentVT.getVectorNumElements();
-  int Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
+  int Elt = cast<ConstantIntSDNode>(EltNo)->getZExtValue();
   int Idx = (Elt > (int)NumElems) ? SM_SentinelUndef : ShuffleMask[Elt];
 
   if (Idx == SM_SentinelZero)
@@ -26693,7 +26697,7 @@
   }
   if (((Subtarget.hasSSE1() && VT == MVT::f32) ||
        (Subtarget.hasSSE2() && VT == MVT::f64)) &&
-      isa<ConstantSDNode>(N0.getOperand(1)) &&
+      isa<ConstantIntSDNode>(N0.getOperand(1)) &&
       N0.getOperand(0).getOpcode() == ISD::BITCAST &&
       N0.getOperand(0).getOperand(0).getValueType() == VT) {
     SDValue N000 = N0.getOperand(0).getOperand(0);
@@ -26919,7 +26923,7 @@
   if (InputVector.getOpcode() == ISD::BITCAST && InputVector.hasOneUse() &&
       N->getValueType(0) == MVT::i32 &&
       InputVector.getValueType() == MVT::v2i32 &&
-      isa<ConstantSDNode>(N->getOperand(1)) &&
+      isa<ConstantIntSDNode>(N->getOperand(1)) &&
       N->getConstantOperandVal(1) == 0) {
     SDValue MMXSrc = InputVector.getNode()->getOperand(0);
 
@@ -26930,13 +26934,13 @@
 
   EVT VT = N->getValueType(0);
 
-  if (VT == MVT::i1 && isa<ConstantSDNode>(N->getOperand(1)) &&
+  if (VT == MVT::i1 && isa<ConstantIntSDNode>(N->getOperand(1)) &&
       InputVector.getOpcode() == ISD::BITCAST &&
-      isa<ConstantSDNode>(InputVector.getOperand(0))) {
+      isa<ConstantIntSDNode>(InputVector.getOperand(0))) {
     uint64_t ExtractedElt =
-        cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
+        cast<ConstantIntSDNode>(N->getOperand(1))->getZExtValue();
     uint64_t InputValue =
-        cast<ConstantSDNode>(InputVector.getOperand(0))->getZExtValue();
+        cast<ConstantIntSDNode>(InputVector.getOperand(0))->getZExtValue();
     uint64_t Res = (InputValue >> ExtractedElt) & 1;
     return DAG.getConstant(Res, dl, MVT::i1);
   }
@@ -26973,12 +26977,12 @@
     if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND &&
         Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND)
       return SDValue();
-    if (!isa<ConstantSDNode>(Extract->getOperand(1)))
+    if (!isa<ConstantIntSDNode>(Extract->getOperand(1)))
       return SDValue();
 
     // Record which element was extracted.
     ExtractedElements |=
-      1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue();
+        1 << cast<ConstantIntSDNode>(Extract->getOperand(1))->getZExtValue();
 
     Uses.push_back(Extract);
   }
@@ -27040,7 +27044,7 @@
     SDNode *Extract = *UI;
 
     SDValue Idx = Extract->getOperand(1);
-    uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
+    uint64_t IdxVal = cast<ConstantIntSDNode>(Idx)->getZExtValue();
     DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), Vals[IdxVal]);
   }
 
@@ -27119,8 +27123,8 @@
   SDValue RHS = N->getOperand(2);
   SDLoc DL(N);
 
-  auto *TrueC = dyn_cast<ConstantSDNode>(LHS);
-  auto *FalseC = dyn_cast<ConstantSDNode>(RHS);
+  auto *TrueC = dyn_cast<ConstantIntSDNode>(LHS);
+  auto *FalseC = dyn_cast<ConstantIntSDNode>(RHS);
   if (!TrueC || !FalseC)
     return SDValue();
 
@@ -27135,7 +27139,7 @@
       // Efficiently invertible.
       (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible.
        (Cond.getOpcode() == ISD::XOR &&  // xor(X, C) -> invertible.
-        isa<ConstantSDNode>(Cond.getOperand(1))))) {
+        isa<ConstantIntSDNode>(Cond.getOperand(1))))) {
     NeedsCondInvert = true;
     std::swap(TrueC, FalseC);
   }
@@ -27498,7 +27502,7 @@
   // SimplifyDemandedBits to simplify the condition operand.
   if (N->getOpcode() == ISD::VSELECT && DCI.isBeforeLegalizeOps() &&
       !DCI.isBeforeLegalize() &&
-      !ISD::isBuildVectorOfConstantSDNodes(Cond.getNode())) {
+      !ISD::isBuildVectorOfConstantIntSDNodes(Cond.getNode())) {
     unsigned BitWidth = Cond.getScalarValueSizeInBits();
 
     // Don't optimize vector selects that map to mask-registers.
@@ -27611,7 +27615,7 @@
   if (!CmpLHS.hasOneUse())
     return SDValue();
 
-  auto *CmpRHSC = dyn_cast<ConstantSDNode>(CmpRHS);
+  auto *CmpRHSC = dyn_cast<ConstantIntSDNode>(CmpRHS);
   if (!CmpRHSC || CmpRHSC->getZExtValue() != 0)
     return SDValue();
 
@@ -27621,7 +27625,7 @@
     return SDValue();
 
   SDValue OpRHS = CmpLHS.getOperand(2);
-  auto *OpRHSC = dyn_cast<ConstantSDNode>(OpRHS);
+  auto *OpRHSC = dyn_cast<ConstantIntSDNode>(OpRHS);
   if (!OpRHSC)
     return SDValue();
 
@@ -27678,13 +27682,13 @@
   SDValue Op2 = Cmp.getOperand(1);
 
   SDValue SetCC;
-  const ConstantSDNode* C = nullptr;
+  const ConstantIntSDNode *C = nullptr;
   bool needOppositeCond = (CC == X86::COND_E);
   bool checkAgainstTrue = false; // Is it a comparison against 1?
 
-  if ((C = dyn_cast<ConstantSDNode>(Op1)))
+  if ((C = dyn_cast<ConstantIntSDNode>(Op1)))
     SetCC = Op2;
-  else if ((C = dyn_cast<ConstantSDNode>(Op2)))
+  else if ((C = dyn_cast<ConstantIntSDNode>(Op2)))
     SetCC = Op1;
   else // Quit if all operands are not constants.
     return SDValue();
@@ -27734,8 +27738,8 @@
     return SetCC.getOperand(1);
   case X86ISD::CMOV: {
     // Check whether false/true value has canonical one, i.e. 0 or 1.
-    ConstantSDNode *FVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(0));
-    ConstantSDNode *TVal = dyn_cast<ConstantSDNode>(SetCC.getOperand(1));
+    auto *FVal = dyn_cast<ConstantIntSDNode>(SetCC.getOperand(0));
+    auto *TVal = dyn_cast<ConstantIntSDNode>(SetCC.getOperand(1));
     // Quit if true value is not a constant.
     if (!TVal)
       return SDValue();
@@ -27867,8 +27871,8 @@
   // If this is a select between two integer constants, try to do some
   // optimizations.  Note that the operands are ordered the opposite of SELECT
   // operands.
-  if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) {
-    if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) {
+  if (auto *TrueC = dyn_cast<ConstantIntSDNode>(TrueOp)) {
+    if (auto *FalseC = dyn_cast<ConstantIntSDNode>(FalseOp)) {
       // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is
       // larger than FalseC (the false value).
       if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) {
@@ -27976,19 +27980,19 @@
     // the DCI.xxxx conditions are provided to postpone the optimization as
     // late as possible.
 
-    ConstantSDNode *CmpAgainst = nullptr;
+    ConstantIntSDNode *CmpAgainst = nullptr;
     if ((Cond.getOpcode() == X86ISD::CMP || Cond.getOpcode() == X86ISD::SUB) &&
-        (CmpAgainst = dyn_cast<ConstantSDNode>(Cond.getOperand(1))) &&
-        !isa<ConstantSDNode>(Cond.getOperand(0))) {
+        (CmpAgainst = dyn_cast<ConstantIntSDNode>(Cond.getOperand(1))) &&
+        !isa<ConstantIntSDNode>(Cond.getOperand(0))) {
 
       if (CC == X86::COND_NE &&
-          CmpAgainst == dyn_cast<ConstantSDNode>(FalseOp)) {
+          CmpAgainst == dyn_cast<ConstantIntSDNode>(FalseOp)) {
         CC = X86::GetOppositeBranchCondition(CC);
         std::swap(TrueOp, FalseOp);
       }
 
       if (CC == X86::COND_E &&
-          CmpAgainst == dyn_cast<ConstantSDNode>(TrueOp)) {
+          CmpAgainst == dyn_cast<ConstantIntSDNode>(TrueOp)) {
         SDValue Ops[] = { FalseOp, Cond.getOperand(0),
                           DAG.getConstant(CC, DL, MVT::i8), Cond };
         return DAG.getNode(X86ISD::CMOV, DL, N->getVTList (), Ops);
@@ -28072,7 +28076,7 @@
       for (const SDValue &SubOp : Opd.getNode()->op_values()) {
         if (SubOp.isUndef())
           continue;
-        auto *CN = dyn_cast<ConstantSDNode>(SubOp);
+        auto *CN = dyn_cast<ConstantIntSDNode>(SubOp);
         if (!CN)
           return false;
         APInt IntVal = CN->getAPIntValue();
@@ -28258,7 +28262,7 @@
   if (VT != MVT::i64 && VT != MVT::i32)
     return SDValue();
 
-  ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1));
+  auto *C = dyn_cast<ConstantIntSDNode>(N->getOperand(1));
   if (!C)
     return SDValue();
   uint64_t MulAmt = C->getZExtValue();
@@ -28334,7 +28338,7 @@
 static SDValue combineShiftLeft(SDNode *N, SelectionDAG &DAG) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
-  ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
+  auto *N1C = dyn_cast<ConstantIntSDNode>(N1);
   EVT VT = N0.getValueType();
 
   // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2))
@@ -28343,7 +28347,7 @@
       N1C && N0.getOpcode() == ISD::AND &&
       N0.getOperand(1).getOpcode() == ISD::Constant) {
     SDValue N00 = N0.getOperand(0);
-    APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
+    APInt Mask = cast<ConstantIntSDNode>(N0.getOperand(1))->getAPIntValue();
     const APInt &ShAmt = N1C->getAPIntValue();
     Mask = Mask.shl(ShAmt);
     bool MaskOK = false;
@@ -28415,8 +28419,8 @@
 
   SDValue N00 = N0.getOperand(0);
   SDValue N01 = N0.getOperand(1);
-  APInt ShlConst = (cast<ConstantSDNode>(N01))->getAPIntValue();
-  APInt SarConst = (cast<ConstantSDNode>(N1))->getAPIntValue();
+  APInt ShlConst = (cast<ConstantIntSDNode>(N01))->getAPIntValue();
+  APInt SarConst = (cast<ConstantIntSDNode>(N1))->getAPIntValue();
   EVT CVT = N1.getValueType();
 
   if (SarConst.isNegative())
@@ -28678,7 +28682,7 @@
 
   // The right side has to be a 'trunc' or a constant vector.
   bool RHSTrunc = N1.getOpcode() == ISD::TRUNCATE;
-  ConstantSDNode *RHSConstSplat = nullptr;
+  ConstantIntSDNode *RHSConstSplat = nullptr;
   if (auto *RHSBV = dyn_cast<BuildVectorSDNode>(N1))
     RHSConstSplat = RHSBV->getConstantSplatNode();
   if (!RHSTrunc && !RHSConstSplat)
@@ -28916,8 +28920,8 @@
   if (N0.getOpcode() != ISD::SRA && N0.getOpcode() != ISD::SRL)
     return SDValue();
 
-  ConstantSDNode *MaskNode = dyn_cast<ConstantSDNode>(N1);
-  ConstantSDNode *ShiftNode = dyn_cast<ConstantSDNode>(N0.getOperand(1));
+  auto *MaskNode = dyn_cast<ConstantIntSDNode>(N1);
+  auto *ShiftNode = dyn_cast<ConstantIntSDNode>(N0.getOperand(1));
   if (MaskNode && ShiftNode) {
     uint64_t Mask = MaskNode->getZExtValue();
     uint64_t Shift = ShiftNode->getZExtValue();
@@ -28989,7 +28993,7 @@
         SraAmt = AmtConst->getZExtValue();
   } else if (Mask.getOpcode() == X86ISD::VSRAI) {
     SDValue SraC = Mask.getOperand(1);
-    SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue();
+    SraAmt = cast<ConstantIntSDNode>(SraC)->getZExtValue();
   }
   if ((SraAmt + 1) != EltBits)
     return SDValue();
@@ -29128,7 +29132,7 @@
   unsigned Bits = VT.getSizeInBits();
   if (ShAmt1.getOpcode() == ISD::SUB) {
     SDValue Sum = ShAmt1.getOperand(0);
-    if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) {
+    if (auto *SumC = dyn_cast<ConstantIntSDNode>(Sum)) {
       SDValue ShAmt1Op1 = ShAmt1.getOperand(1);
       if (ShAmt1Op1.getOpcode() == ISD::TRUNCATE)
         ShAmt1Op1 = ShAmt1Op1.getOperand(0);
@@ -29138,8 +29142,8 @@
                            DAG.getNode(ISD::TRUNCATE, DL,
                                        MVT::i8, ShAmt0));
     }
-  } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) {
-    ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0);
+  } else if (auto *ShAmt1C = dyn_cast<ConstantIntSDNode>(ShAmt1)) {
+    auto *ShAmt0C = dyn_cast<ConstantIntSDNode>(ShAmt0);
     if (ShAmt0C && (ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue()) == Bits)
       return DAG.getNode(Opc, DL, VT,
                          N0.getOperand(0), N1.getOperand(0),
@@ -29147,14 +29151,14 @@
                                        MVT::i8, ShAmt0));
   } else if (ShAmt1.getOpcode() == ISD::XOR) {
     SDValue Mask = ShAmt1.getOperand(1);
-    if (ConstantSDNode *MaskC = dyn_cast<ConstantSDNode>(Mask)) {
+    if (auto *MaskC = dyn_cast<ConstantIntSDNode>(Mask)) {
       unsigned InnerShift = (X86ISD::SHLD == Opc ? ISD::SRL : ISD::SHL);
       SDValue ShAmt1Op0 = ShAmt1.getOperand(0);
       if (ShAmt1Op0.getOpcode() == ISD::TRUNCATE)
         ShAmt1Op0 = ShAmt1Op0.getOperand(0);
       if (MaskC->getSExtValue() == (Bits - 1) && ShAmt1Op0 == ShAmt0) {
         if (Op1.getOpcode() == InnerShift &&
-            isa<ConstantSDNode>(Op1.getOperand(1)) &&
+            isa<ConstantIntSDNode>(Op1.getOperand(1)) &&
             Op1.getConstantOperandVal(1) == 1) {
           return DAG.getNode(Opc, DL, VT, Op0, Op1.getOperand(0),
                              DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ShAmt0));
@@ -29192,7 +29196,7 @@
       N0.getOperand(1) == N1 &&
       N1.getOpcode() == ISD::SRA &&
       N1.getOperand(0) == N0.getOperand(0))
-    if (ConstantSDNode *Y1C = dyn_cast<ConstantSDNode>(N1.getOperand(1)))
+    if (auto *Y1C = dyn_cast<ConstantIntSDNode>(N1.getOperand(1)))
       if (Y1C->getAPIntValue() == VT.getSizeInBits()-1) {
         // Generate SUB & CMOV.
         SDValue Neg = DAG.getNode(X86ISD::SUB, DL, DAG.getVTList(VT, MVT::i32),
@@ -29238,7 +29242,7 @@
     return SDValue();
 
   // Make sure the shift amount extracts the sign bit.
-  if (!isa<ConstantSDNode>(Shift.getOperand(1)) ||
+  if (!isa<ConstantIntSDNode>(Shift.getOperand(1)) ||
       Shift.getConstantOperandVal(1) != ShiftTy.getSizeInBits() - 1)
     return SDValue();
 
@@ -29362,7 +29366,7 @@
     if (!BV || !BV->isConstant())
       return false;
     for (unsigned i = 0, e = V.getNumOperands(); i < e; i++) {
-      ConstantSDNode *C = dyn_cast<ConstantSDNode>(V.getOperand(i));
+      auto *C = dyn_cast<ConstantIntSDNode>(V.getOperand(i));
       if (!C)
         return false;
       uint64_t Val = C->getZExtValue();
@@ -29496,7 +29500,7 @@
     const SDValue &Op = BV->getOperand(i);
     if (Op.isUndef())
       continue;
-    auto *ConstNode = dyn_cast<ConstantSDNode>(Op);
+    auto *ConstNode = dyn_cast<ConstantIntSDNode>(Op);
     if (!ConstNode)
       return -1;
     if (ConstNode->getAPIntValue().isAllOnesValue()) {
@@ -29568,7 +29572,7 @@
 static SDValue
 combineMaskedLoadConstantMask(MaskedLoadSDNode *ML, SelectionDAG &DAG,
                               TargetLowering::DAGCombinerInfo &DCI) {
-  if (!ISD::isBuildVectorOfConstantSDNodes(ML->getMask().getNode()))
+  if (!ISD::isBuildVectorOfConstantIntSDNodes(ML->getMask().getNode()))
     return SDValue();
 
   SDLoc DL(ML);
@@ -30795,7 +30799,7 @@
   // Having a constant operand to the 'add' ensures that we are not increasing
   // the instruction count because the constant is extended for free below.
   // A constant operand can also become the displacement field of an LEA.
-  auto *AddOp1 = dyn_cast<ConstantSDNode>(Add.getOperand(1));
+  auto *AddOp1 = dyn_cast<ConstantIntSDNode>(Add.getOperand(1));
   if (!AddOp1)
     return SDValue();
 
@@ -31209,7 +31213,7 @@
     //
     if (EFLAGS.getOpcode() == X86ISD::SUB && EFLAGS.hasOneUse() &&
         EFLAGS.getValueType().isInteger() &&
-        !isa<ConstantSDNode>(EFLAGS.getOperand(1))) {
+        !isa<ConstantIntSDNode>(EFLAGS.getOperand(1))) {
       SDValue NewSub = DAG.getNode(X86ISD::SUB, SDLoc(EFLAGS),
                                    EFLAGS.getNode()->getVTList(),
                                    EFLAGS.getOperand(1), EFLAGS.getOperand(0));
@@ -31557,13 +31561,13 @@
 
   // X86 can't encode an immediate LHS of a sub. See if we can push the
   // negation into a preceding instruction.
-  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) {
+  if (auto *C = dyn_cast<ConstantIntSDNode>(Op0)) {
     // If the RHS of the sub is a XOR with one use and a constant, invert the
     // immediate. Then add one to the LHS of the sub so we can turn
     // X-Y -> X+~Y+1, saving one register.
     if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR &&
-        isa<ConstantSDNode>(Op1.getOperand(1))) {
-      APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue();
+        isa<ConstantIntSDNode>(Op1.getOperand(1))) {
+      APInt XorC = cast<ConstantIntSDNode>(Op1.getOperand(1))->getAPIntValue();
       EVT VT = Op0.getValueType();
       SDValue NewXor = DAG.getNode(ISD::XOR, SDLoc(Op1), VT,
                                    Op1.getOperand(0),
@@ -31595,7 +31599,7 @@
   unsigned InputBits = OpEltVT.getSizeInBits() * VT.getVectorNumElements();
 
   // Perform any constant folding.
-  if (ISD::isBuildVectorOfConstantSDNodes(Op.getNode())) {
+  if (ISD::isBuildVectorOfConstantIntSDNodes(Op.getNode())) {
     SmallVector<SDValue, 4> Vals;
     for (int i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
       SDValue OpElt = Op.getOperand(i);
@@ -31603,7 +31607,7 @@
         Vals.push_back(DAG.getUNDEF(SVT));
         continue;
       }
-      APInt Cst = cast<ConstantSDNode>(OpElt.getNode())->getAPIntValue();
+      APInt Cst = cast<ConstantIntSDNode>(OpElt.getNode())->getAPIntValue();
       assert(Cst.getBitWidth() == OpEltVT.getSizeInBits());
       Cst = Cst.zextOrTrunc(SVT.getSizeInBits());
       Vals.push_back(DAG.getConstant(Cst, DL, SVT));
@@ -31670,7 +31674,7 @@
   MVT VT = RHS.getSimpleValueType();
   SDLoc DL(N);
 
-  auto *C = dyn_cast<ConstantSDNode>(RHS);
+  auto *C = dyn_cast<ConstantIntSDNode>(RHS);
   if (!C || C->getZExtValue() != 1)
     return SDValue();
 
@@ -31884,9 +31888,11 @@
     if (!Commute && MayFoldLoad(N1))
       return false;
     // Avoid disabling potential load folding opportunities.
-    if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op)))
+    if (MayFoldLoad(N0) &&
+        (!isa<ConstantIntSDNode>(N1) || MayFoldIntoStore(Op)))
       return false;
-    if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op)))
+    if (MayFoldLoad(N1) &&
+        (!isa<ConstantIntSDNode>(N0) || MayFoldIntoStore(Op)))
       return false;
     Promote = true;
   }
@@ -32195,7 +32201,7 @@
   switch (ConstraintLetter) {
   default: break;
   case 'I':
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op)) {
       if (C->getZExtValue() <= 31) {
         Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
                                        Op.getValueType());
@@ -32204,7 +32210,7 @@
     }
     return;
   case 'J':
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op)) {
       if (C->getZExtValue() <= 63) {
         Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
                                        Op.getValueType());
@@ -32213,7 +32219,7 @@
     }
     return;
   case 'K':
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op)) {
       if (isInt<8>(C->getSExtValue())) {
         Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
                                        Op.getValueType());
@@ -32222,7 +32228,7 @@
     }
     return;
   case 'L':
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op)) {
       if (C->getZExtValue() == 0xff || C->getZExtValue() == 0xffff ||
           (Subtarget.is64Bit() && C->getZExtValue() == 0xffffffff)) {
         Result = DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
@@ -32232,7 +32238,7 @@
     }
     return;
   case 'M':
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op)) {
       if (C->getZExtValue() <= 3) {
         Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
                                        Op.getValueType());
@@ -32241,7 +32247,7 @@
     }
     return;
   case 'N':
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op)) {
       if (C->getZExtValue() <= 255) {
         Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
                                        Op.getValueType());
@@ -32250,7 +32256,7 @@
     }
     return;
   case 'O':
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op)) {
       if (C->getZExtValue() <= 127) {
         Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
                                        Op.getValueType());
@@ -32260,7 +32266,7 @@
     return;
   case 'e': {
     // 32-bit signed value
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op)) {
       if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
                                            C->getSExtValue())) {
         // Widen to 64 bits here to get it sign extended.
@@ -32274,7 +32280,7 @@
   }
   case 'Z': {
     // 32-bit unsigned value
-    if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) {
+    if (auto *C = dyn_cast<ConstantIntSDNode>(Op)) {
       if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()),
                                            C->getZExtValue())) {
         Result = DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
@@ -32288,7 +32294,7 @@
   }
   case 'i': {
     // Literal immediates are always ok.
-    if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) {
+    if (auto *CST = dyn_cast<ConstantIntSDNode>(Op)) {
       // Widen to 64 bits here to get it sign extended.
       Result = DAG.getTargetConstant(CST->getSExtValue(), SDLoc(Op), MVT::i64);
       break;
@@ -32311,13 +32317,13 @@
         Offset += GA->getOffset();
         break;
       } else if (Op.getOpcode() == ISD::ADD) {
-        if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+        if (auto *C = dyn_cast<ConstantIntSDNode>(Op.getOperand(1))) {
           Offset += C->getZExtValue();
           Op = Op.getOperand(0);
           continue;
         }
       } else if (Op.getOpcode() == ISD::SUB) {
-        if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
+        if (auto *C = dyn_cast<ConstantIntSDNode>(Op.getOperand(1))) {
           Offset += -C->getZExtValue();
           Op = Op.getOperand(0);
           continue;
Index: llvm/lib/Target/X86/X86InstrCompiler.td
===================================================================
--- llvm/lib/Target/X86/X86InstrCompiler.td
+++ llvm/lib/Target/X86/X86InstrCompiler.td
@@ -15,12 +15,12 @@
 //===----------------------------------------------------------------------===//
 // Pattern Matching Support
 
-def GetLo32XForm : SDNodeXForm<imm, [{
+def GetLo32XForm : ConstIntSDNodeXForm<[{
   // Transformation function: get the low 32 bits.
   return getI32Imm((unsigned)N->getZExtValue(), SDLoc(N));
 }]>;
 
-def GetLo8XForm : SDNodeXForm<imm, [{
+def GetLo8XForm : ConstIntSDNodeXForm<[{
   // Transformation function: get the low 8 bits.
   return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
 }]>;
@@ -1315,7 +1315,7 @@
 
 // Treat an 'or' node is as an 'add' if the or'ed bits are known to be zero.
 def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
-  if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N->getOperand(1)))
+  if (auto *CN = dyn_cast<ConstantIntSDNode>(N->getOperand(1)))
     return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
 
   APInt KnownZero0, KnownOne0;
Index: llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
===================================================================
--- llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
+++ llvm/lib/Target/X86/X86InstrFragmentsSIMD.td
@@ -852,7 +852,7 @@
   return N->isExactlyValue(+0.0);
 }]>;
 
-def I8Imm : SDNodeXForm<imm, [{
+def I8Imm : ConstIntSDNodeXForm<[{
   // Transformation function: get the low 8 bits.
   return getI8Imm((uint8_t)N->getZExtValue(), SDLoc(N));
 }]>;
@@ -863,7 +863,7 @@
 }]>;
 
 // BYTE_imm - Transform bit immediates into byte immediates.
-def BYTE_imm  : SDNodeXForm<imm, [{
+def BYTE_imm  : ConstIntSDNodeXForm<[{
   // Transformation function: imm >> 3
   return getI32Imm(N->getZExtValue() >> 3, SDLoc(N));
 }]>;
Index: llvm/lib/Target/X86/X86InstrInfo.cpp
===================================================================
--- llvm/lib/Target/X86/X86InstrInfo.cpp
+++ llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -7412,14 +7412,14 @@
   // Scale should be 1, Index should be Reg0.
   if (Load1->getOperand(1) == Load2->getOperand(1) &&
       Load1->getOperand(2) == Load2->getOperand(2)) {
-    if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
+    if (cast<ConstantIntSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
       return false;
 
     // Now let's examine the displacements.
-    if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
-        isa<ConstantSDNode>(Load2->getOperand(3))) {
-      Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
-      Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
+    if (isa<ConstantIntSDNode>(Load1->getOperand(3)) &&
+        isa<ConstantIntSDNode>(Load2->getOperand(3))) {
+      Offset1 = cast<ConstantIntSDNode>(Load1->getOperand(3))->getSExtValue();
+      Offset2 = cast<ConstantIntSDNode>(Load2->getOperand(3))->getSExtValue();
       return true;
     }
   }
Index: llvm/lib/Target/X86/X86InstrInfo.td
===================================================================
--- llvm/lib/Target/X86/X86InstrInfo.td
+++ llvm/lib/Target/X86/X86InstrInfo.td
@@ -2280,7 +2280,7 @@
 }
 
 
-def CountTrailingOnes : SDNodeXForm<imm, [{
+def CountTrailingOnes : ConstIntSDNodeXForm<[{
   // Count the trailing ones in the immediate.
   return getI8Imm(countTrailingOnes(N->getZExtValue()), SDLoc(N));
 }]>;
Index: llvm/lib/Target/X86/X86InstrShiftRotate.td
===================================================================
--- llvm/lib/Target/X86/X86InstrShiftRotate.td
+++ llvm/lib/Target/X86/X86InstrShiftRotate.td
@@ -848,12 +848,12 @@
 
 } // Defs = [EFLAGS]
 
-def ROT32L2R_imm8  : SDNodeXForm<imm, [{
+def ROT32L2R_imm8  : ConstIntSDNodeXForm<[{
   // Convert a ROTL shamt to a ROTR shamt on 32-bit integer.
   return getI8Imm(32 - N->getZExtValue(), SDLoc(N));
 }]>;
 
-def ROT64L2R_imm8  : SDNodeXForm<imm, [{
+def ROT64L2R_imm8  : ConstIntSDNodeXForm<[{
   // Convert a ROTL shamt to a ROTR shamt on 64-bit integer.
   return getI8Imm(64 - N->getZExtValue(), SDLoc(N));
 }]>;
Index: llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
===================================================================
--- llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
+++ llvm/lib/Target/X86/X86SelectionDAGInfo.cpp
@@ -48,7 +48,7 @@
     SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src,
     SDValue Size, unsigned Align, bool isVolatile,
     MachinePointerInfo DstPtrInfo) const {
-  ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
+  auto *ConstantSize = dyn_cast<ConstantIntSDNode>(Size);
   const X86Subtarget &Subtarget =
       DAG.getMachineFunction().getSubtarget<X86Subtarget>();
 
@@ -69,7 +69,7 @@
   if ((Align & 3) != 0 || !ConstantSize ||
       ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold()) {
     // Check to see if there is a specialized entry-point for memory zeroing.
-    ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
+    auto *V = dyn_cast<ConstantIntSDNode>(Src);
 
     if (const char *bzeroEntry = V &&
         V->isNullValue() ? Subtarget.getBZeroEntry() : nullptr) {
@@ -102,7 +102,7 @@
   SDValue InFlag;
   EVT AVT;
   SDValue Count;
-  ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
+  auto *ValC = dyn_cast<ConstantIntSDNode>(Src);
   unsigned BytesLeft = 0;
   bool TwoRepStos = false;
   if (ValC) {
@@ -199,7 +199,7 @@
     MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
   // This requires the copy size to be a constant, preferably
   // within a subtarget-specific limit.
-  ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
+  auto *ConstantSize = dyn_cast<ConstantIntSDNode>(Size);
   const X86Subtarget &Subtarget =
       DAG.getMachineFunction().getSubtarget<X86Subtarget>();
   if (!ConstantSize)
Index: llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
===================================================================
--- llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
+++ llvm/lib/Target/XCore/XCoreISelDAGToDAG.cpp
@@ -91,10 +91,10 @@
     return true;
   }
   if (Addr.getOpcode() == ISD::ADD) {
-    ConstantSDNode *CN = nullptr;
-    if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0)))
-      && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))
-      && (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {
+    ConstantIntSDNode *CN = nullptr;
+    if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) &&
+        (CN = dyn_cast<ConstantIntSDNode>(Addr.getOperand(1))) &&
+        (CN->getSExtValue() % 4 == 0 && CN->getSExtValue() >= 0)) {
       // Constant positive word offset from frame index
       Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
       Offset = CurDAG->getTargetConstant(CN->getSExtValue(), SDLoc(Addr),
@@ -132,7 +132,7 @@
   switch (N->getOpcode()) {
   default: break;
   case ISD::Constant: {
-    uint64_t Val = cast<ConstantSDNode>(N)->getZExtValue();
+    uint64_t Val = cast<ConstantIntSDNode>(N)->getZExtValue();
     if (immMskBitp(Val)) {
       // Transformation function: get the size of a mask
       // Look for the first non-zero bit
@@ -241,7 +241,7 @@
   SDValue Addr = N->getOperand(1);
   if (Addr->getOpcode() != ISD::INTRINSIC_W_CHAIN)
     return false;
-  unsigned IntNo = cast<ConstantSDNode>(Addr->getOperand(1))->getZExtValue();
+  unsigned IntNo = cast<ConstantIntSDNode>(Addr->getOperand(1))->getZExtValue();
   if (IntNo != Intrinsic::xcore_checkevent)
     return false;
   SDValue nextAddr = Addr->getOperand(2);
Index: llvm/lib/Target/XCore/XCoreISelLowering.cpp
===================================================================
--- llvm/lib/Target/XCore/XCoreISelLowering.cpp
+++ llvm/lib/Target/XCore/XCoreISelLowering.cpp
@@ -440,7 +440,7 @@
     if (DAG.isBaseWithConstantOffset(BasePtr) &&
         isWordAligned(BasePtr->getOperand(0), DAG)) {
       SDValue NewBasePtr = BasePtr->getOperand(0);
-      Offset = cast<ConstantSDNode>(BasePtr->getOperand(1))->getSExtValue();
+      Offset = cast<ConstantIntSDNode>(BasePtr->getOperand(1))->getSExtValue();
       return lowerLoadWordFromAlignedBasePlusOffset(DL, Chain, NewBasePtr,
                                                     Offset, DAG);
     }
@@ -794,7 +794,7 @@
   // An index of zero corresponds to the current function's frame address.
   // An index of one to the parent's frame address, and so on.
   // Depths > 0 not supported yet!
-  if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
+  if (cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue() > 0)
     return SDValue();
 
   MachineFunction &MF = DAG.getMachineFunction();
@@ -810,7 +810,7 @@
   // An index of zero corresponds to the current function's return address.
   // An index of one to the parent's return address, and so on.
   // Depths > 0 not supported yet!
-  if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
+  if (cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue() > 0)
     return SDValue();
 
   MachineFunction &MF = DAG.getMachineFunction();
@@ -932,7 +932,7 @@
 SDValue XCoreTargetLowering::
 LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
   SDLoc DL(Op);
-  unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
+  unsigned IntNo = cast<ConstantIntSDNode>(Op.getOperand(0))->getZExtValue();
   switch (IntNo) {
     case Intrinsic::xcore_crc8:
       EVT VT = Op.getValueType();
@@ -1592,7 +1592,7 @@
   switch (N->getOpcode()) {
   default: break;
   case ISD::INTRINSIC_VOID:
-    switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
+    switch (cast<ConstantIntSDNode>(N->getOperand(1))->getZExtValue()) {
     case Intrinsic::xcore_outt:
     case Intrinsic::xcore_outct:
     case Intrinsic::xcore_chkct: {
@@ -1635,8 +1635,8 @@
     SDValue N0 = N->getOperand(0);
     SDValue N1 = N->getOperand(1);
     SDValue N2 = N->getOperand(2);
-    ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
-    ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
+    auto *N0C = dyn_cast<ConstantIntSDNode>(N0);
+    auto *N1C = dyn_cast<ConstantIntSDNode>(N1);
     EVT VT = N0.getValueType();
 
     // canonicalize constant to RHS
@@ -1672,8 +1672,8 @@
     SDValue N0 = N->getOperand(0);
     SDValue N1 = N->getOperand(1);
     SDValue N2 = N->getOperand(2);
-    ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
-    ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
+    auto *N0C = dyn_cast<ConstantIntSDNode>(N0);
+    auto *N1C = dyn_cast<ConstantIntSDNode>(N1);
     EVT VT = N0.getValueType();
 
     // fold (lsub 0, 0, x) -> x, -x iff x has only the low bit set
@@ -1712,8 +1712,8 @@
     SDValue N1 = N->getOperand(1);
     SDValue N2 = N->getOperand(2);
     SDValue N3 = N->getOperand(3);
-    ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
-    ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
+    auto *N0C = dyn_cast<ConstantIntSDNode>(N0);
+    auto *N1C = dyn_cast<ConstantIntSDNode>(N1);
     EVT VT = N0.getValueType();
     // Canonicalize multiplicative constant to RHS. If both multiplicative
     // operands are constant canonicalize smallest to RHS.
@@ -1839,29 +1839,29 @@
     break;
   case ISD::INTRINSIC_W_CHAIN:
     {
-      unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
-      switch (IntNo) {
-      case Intrinsic::xcore_getts:
-        // High bits are known to be zero.
-        KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(),
-                                          KnownZero.getBitWidth() - 16);
-        break;
-      case Intrinsic::xcore_int:
-      case Intrinsic::xcore_inct:
-        // High bits are known to be zero.
-        KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(),
-                                          KnownZero.getBitWidth() - 8);
-        break;
-      case Intrinsic::xcore_testct:
-        // Result is either 0 or 1.
-        KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(),
-                                          KnownZero.getBitWidth() - 1);
-        break;
-      case Intrinsic::xcore_testwct:
-        // Result is in the range 0 - 4.
-        KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(),
-                                          KnownZero.getBitWidth() - 3);
-        break;
+    unsigned IntNo = cast<ConstantIntSDNode>(Op.getOperand(1))->getZExtValue();
+    switch (IntNo) {
+    case Intrinsic::xcore_getts:
+      // High bits are known to be zero.
+      KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(),
+                                        KnownZero.getBitWidth() - 16);
+      break;
+    case Intrinsic::xcore_int:
+    case Intrinsic::xcore_inct:
+      // High bits are known to be zero.
+      KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(),
+                                        KnownZero.getBitWidth() - 8);
+      break;
+    case Intrinsic::xcore_testct:
+      // Result is either 0 or 1.
+      KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(),
+                                        KnownZero.getBitWidth() - 1);
+      break;
+    case Intrinsic::xcore_testwct:
+      // Result is in the range 0 - 4.
+      KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(),
+                                        KnownZero.getBitWidth() - 3);
+      break;
       }
     }
     break;
Index: llvm/lib/Target/XCore/XCoreInstrInfo.td
===================================================================
--- llvm/lib/Target/XCore/XCoreInstrInfo.td
+++ llvm/lib/Target/XCore/XCoreInstrInfo.td
@@ -91,13 +91,13 @@
 // Instruction Pattern Stuff
 //===----------------------------------------------------------------------===//
 
-def div4_xform : SDNodeXForm<imm, [{
+def div4_xform : ConstIntSDNodeXForm<[{
   // Transformation function: imm/4
   assert(N->getZExtValue() % 4 == 0);
   return getI32Imm(N->getZExtValue()/4, SDLoc(N));
 }]>;
 
-def msksize_xform : SDNodeXForm<imm, [{
+def msksize_xform : ConstIntSDNodeXForm<[{
   // Transformation function: get the size of a mask
   assert(isMask_32(N->getZExtValue()));
   // look for the first non-zero bit
@@ -105,19 +105,19 @@
                    SDLoc(N));
 }]>;
 
-def neg_xform : SDNodeXForm<imm, [{
+def neg_xform : ConstIntSDNodeXForm<[{
   // Transformation function: -imm
   uint32_t value = N->getZExtValue();
   return getI32Imm(-value, SDLoc(N));
 }]>;
 
-def bpwsub_xform : SDNodeXForm<imm, [{
+def bpwsub_xform : ConstIntSDNodeXForm<[{
   // Transformation function: 32-imm
   uint32_t value = N->getZExtValue();
   return getI32Imm(32 - value, SDLoc(N));
 }]>;
 
-def div4neg_xform : SDNodeXForm<imm, [{
+def div4neg_xform : ConstIntSDNodeXForm<[{
   // Transformation function: -imm/4
   uint32_t value = N->getZExtValue();
   assert(-value % 4 == 0);
Index: llvm/utils/TableGen/CodeGenDAGPatterns.h
===================================================================
--- llvm/utils/TableGen/CodeGenDAGPatterns.h
+++ llvm/utils/TableGen/CodeGenDAGPatterns.h
@@ -718,8 +718,12 @@
   CodeGenIntrinsicTable Intrinsics;
   CodeGenIntrinsicTable TgtIntrinsics;
 
+public:
+  typedef std::tuple<Record*, bool, std::string> NodeXForm;
+
+private:
   std::map<Record*, SDNodeInfo, LessRecordByID> SDNodes;
-  std::map<Record*, std::pair<Record*, std::string>, LessRecordByID> SDNodeXForms;
+  std::map<Record*, NodeXForm, LessRecordByID> SDNodeXForms;
   std::map<Record*, ComplexPattern, LessRecordByID> ComplexPatterns;
   std::map<Record *, std::unique_ptr<TreePattern>, LessRecordByID>
       PatternFragments;
@@ -748,7 +752,6 @@
   }
 
   // Node transformation lookups.
-  typedef std::pair<Record*, std::string> NodeXForm;
   const NodeXForm &getSDNodeTransform(Record *R) const {
     assert(SDNodeXForms.count(R) && "Invalid transform!");
     return SDNodeXForms.find(R)->second;
Index: llvm/utils/TableGen/CodeGenDAGPatterns.cpp
===================================================================
--- llvm/utils/TableGen/CodeGenDAGPatterns.cpp
+++ llvm/utils/TableGen/CodeGenDAGPatterns.cpp
@@ -766,13 +766,12 @@
   // Handle immediate predicates first.
   std::string ImmCode = getImmCode();
   if (!ImmCode.empty()) {
-    std::string Result;
+    std::string Result = "    auto *N = dyn_cast<ConstantIntSDNode>(Node);\n"
+                         "    if (!N) return false;\n";
     if (PatFragRec->getRecord()->getValueAsBit("Signed"))
-      Result =
-        "    int64_t Imm = cast<ConstantSDNode>(Node)->getSExtValue();\n";
+      Result += "    int64_t Imm = N->getSExtValue();\n";
     else
-      Result =
-        "    uint64_t Imm = cast<ConstantSDNode>(Node)->getZExtValue();\n";
+      Result += "    uint64_t Imm = N->getZExtValue();\n";
     return Result + ImmCode;
   }
   
@@ -805,7 +804,7 @@
 static unsigned getPatternSize(const TreePatternNode *P,
                                const CodeGenDAGPatterns &CGP) {
   unsigned Size = 3;  // The node itself.
-  // If the root node is a ConstantSDNode, increases its size.
+  // If the root node is a ConstantIntSDNode, increases its size.
   // e.g. (set R32:$dst, 0).
   if (P->isLeaf() && isa<IntInit>(P->getLeafValue()))
     Size += 2;
@@ -836,7 +835,8 @@
       Size += getPatternSize(Child, CGP);
     else if (Child->isLeaf()) {
       if (isa<IntInit>(Child->getLeafValue()))
-        Size += 5;  // Matches a ConstantSDNode (+3) and a specific value (+2).
+        Size +=
+            5; // Matches a ConstantIntSDNode (+3) and a specific value (+2).
       else if (Child->getComplexPatternInfo(CGP))
         Size += getPatternSize(Child, CGP);
       else if (!Child->getPredicateFns().empty())
@@ -2435,8 +2435,10 @@
   while (!Xforms.empty()) {
     Record *XFormNode = Xforms.back();
     Record *SDNode = XFormNode->getValueAsDef("Opcode");
+    bool ConstantInt = XFormNode->getValueAsBit("ConstantInt");
     std::string Code = XFormNode->getValueAsString("XFormFunction");
-    SDNodeXForms.insert(std::make_pair(XFormNode, NodeXForm(SDNode, Code)));
+    SDNodeXForms.insert(
+        std::make_pair(XFormNode, NodeXForm(SDNode, ConstantInt, Code)));
 
     Xforms.pop_back();
   }
@@ -2516,7 +2518,7 @@
     // If there is a node transformation corresponding to this, keep track of
     // it.
     Record *Transform = Frag->getValueAsDef("OperandTransform");
-    if (!getSDNodeTransform(Transform).second.empty())    // not noop xform?
+    if (!std::get<2>(getSDNodeTransform(Transform)).empty())    // not noop xform?
       P->getOnlyTree()->setTransformFn(Transform);
   }
 
Index: llvm/utils/TableGen/DAGISelMatcher.h
===================================================================
--- llvm/utils/TableGen/DAGISelMatcher.h
+++ llvm/utils/TableGen/DAGISelMatcher.h
@@ -555,7 +555,8 @@
 
 
 /// CheckIntegerMatcher - This checks to see if the current node is a
-/// ConstantSDNode with the specified integer value, if not it fails to match.
+/// ConstantIntSDNode with the specified integer value, if not it fails to
+/// match.
 class CheckIntegerMatcher : public Matcher {
   int64_t Value;
 public:
@@ -577,7 +578,7 @@
 };
 
 /// CheckChildIntegerMatcher - This checks to see if the child node is a
-/// ConstantSDNode with a specified integer value, if not it fails to match.
+/// ConstantIntSDNode with a specified integer value, if not it fails to match.
 class CheckChildIntegerMatcher : public Matcher {
   unsigned ChildNo;
   int64_t Value;
Index: llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
===================================================================
--- llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
+++ llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
@@ -722,8 +722,9 @@
       const CodeGenDAGPatterns::NodeXForm &Entry =
         CGP.getSDNodeTransform(NodeXForms[i]);
 
-      Record *SDNode = Entry.first;
-      const std::string &Code = Entry.second;
+      Record *SDNode = std::get<0>(Entry);
+      bool ConstantInt = std::get<1>(Entry);
+      const std::string &Code = std::get<2>(Entry);
 
       OS << "  case " << i << ": {  ";
       if (!OmitComments)
@@ -731,6 +732,8 @@
       OS << '\n';
 
       std::string ClassName = CGP.getSDNodeInfo(SDNode).getSDClassName();
+      if (ConstantInt)
+        ClassName = "ConstantIntSDNode";
       if (ClassName == "SDNode")
         OS << "    SDNode *N = V.getNode();\n";
       else