Index: lib/Target/AMDGPU/AMDGPUSubtarget.h
===================================================================
--- lib/Target/AMDGPU/AMDGPUSubtarget.h
+++ lib/Target/AMDGPU/AMDGPUSubtarget.h
@@ -504,6 +504,17 @@
     return getGeneration() >= VOLCANIC_ISLANDS;
   }
 
+  /// \returns true if scalar instructions always use a 64-bit encoding.
+  bool usesSMEMEncoding64() const {
+    return getGeneration() >= VOLCANIC_ISLANDS;
+  }
+
+  /// \returns ture if the subtarget has SMRD instructions with a 32-bit
+  /// immediate offset available.
+  bool hasSMRDOffset32Imm() const {
+    return getGeneration() == SEA_ISLANDS;
+  }
+
   bool enableSIScheduler() const {
     return EnableSIScheduler;
   }
Index: lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.cpp
+++ lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -3288,6 +3288,21 @@
     return 4;
   }
 
+  if (isSMRD(MI)) {
+    // VI switched to using a 64-bit encoding for scalar memory operations.
+    if (ST.usesSMEMEncoding64())
+      return 8;
+
+    if (ST.hasSMRDOffset32Imm()) {
+      // CI can use a 32-bit literal dword offset.
+      const MachineOperand *Offset = getNamedOperand(MI, AMDGPU::OpName::offset);
+      if (Offset && !isUInt<8>(Offset->getImm() / 4))
+        return 8;
+    }
+
+    return 4;
+  }
+
   switch (Opc) {
   case TargetOpcode::IMPLICIT_DEF:
   case TargetOpcode::KILL: