Index: llvm/include/llvm/CodeGen/FastISel.h
===================================================================
--- llvm/include/llvm/CodeGen/FastISel.h
+++ llvm/include/llvm/CodeGen/FastISel.h
@@ -354,7 +354,7 @@
   /// instruction with the given type, opcode, and register and immediate
   // operands be emitted.
   virtual unsigned fastEmit_ri(MVT VT, MVT RetVT, unsigned Opcode, unsigned Op0,
-                               bool Op0IsKill, uint64_t Imm);
+                               bool Op0IsKill, int64_t Imm);
 
   /// \brief This method is a wrapper of fastEmit_ri.
   ///
@@ -362,11 +362,11 @@
   /// fastEmit_ri.  If that fails, it materializes the immediate into a register
   /// and try fastEmit_rr instead.
   unsigned fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill,
-                        uint64_t Imm, MVT ImmType);
+                        int64_t Imm, MVT ImmType);
 
   /// \brief This method is called by target-independent code to request that an
   /// instruction with the given type, opcode, and immediate operand be emitted.
-  virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, uint64_t Imm);
+  virtual unsigned fastEmit_i(MVT VT, MVT RetVT, unsigned Opcode, int64_t Imm);
 
   /// \brief This method is called by target-independent code to request that an
   /// instruction with the given type, opcode, and floating-point immediate
Index: llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -212,7 +212,7 @@
   unsigned Reg = 0;
   if (const auto *CI = dyn_cast<ConstantInt>(V)) {
     if (CI->getValue().getActiveBits() <= 64)
-      Reg = fastEmit_i(VT, VT, ISD::Constant, CI->getZExtValue());
+      Reg = fastEmit_i(VT, VT, ISD::Constant, CI->getSExtValue());
   } else if (isa<AllocaInst>(V))
     Reg = fastMaterializeAlloca(cast<AllocaInst>(V));
   else if (isa<ConstantPointerNull>(V))
@@ -413,7 +413,7 @@
 
       unsigned ResultReg =
           fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, Op1IsKill,
-                       CI->getZExtValue(), VT.getSimpleVT());
+                       CI->getSExtValue(), VT.getSimpleVT());
       if (!ResultReg)
         return false;
 
@@ -429,7 +429,7 @@
 
   // Check if the second operand is a constant and handle it appropriately.
   if (const auto *CI = dyn_cast<ConstantInt>(I->getOperand(1))) {
-    uint64_t Imm = CI->getSExtValue();
+    int64_t Imm = CI->getSExtValue();
 
     // Transform "sdiv exact X, 8" -> "sra X, 3".
     if (ISDOpcode == ISD::SDIV && isa<BinaryOperator>(I) &&
@@ -1700,7 +1700,7 @@
   return 0;
 }
 
-unsigned FastISel::fastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
+unsigned FastISel::fastEmit_i(MVT, MVT, unsigned, int64_t /*Imm*/) {
   return 0;
 }
 
@@ -1710,7 +1710,7 @@
 }
 
 unsigned FastISel::fastEmit_ri(MVT, MVT, unsigned, unsigned /*Op0*/,
-                               bool /*Op0IsKill*/, uint64_t /*Imm*/) {
+                               bool /*Op0IsKill*/, int64_t /*Imm*/) {
   return 0;
 }
 
@@ -1719,7 +1719,7 @@
 /// If that fails, it materializes the immediate into a register and try
 /// fastEmit_rr instead.
 unsigned FastISel::fastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0,
-                                bool Op0IsKill, uint64_t Imm, MVT ImmType) {
+                                bool Op0IsKill, int64_t Imm, MVT ImmType) {
   // If this is a multiply by a power of two, emit this as a shift left.
   if (Opcode == ISD::MUL && isPowerOf2_64(Imm)) {
     Opcode = ISD::SHL;
@@ -1733,7 +1733,7 @@
   // Horrible hack (to be removed), check to make sure shift amounts are
   // in-range.
   if ((Opcode == ISD::SHL || Opcode == ISD::SRA || Opcode == ISD::SRL) &&
-      Imm >= VT.getSizeInBits())
+      ((uint64_t)Imm) >= VT.getSizeInBits())
     return 0;
 
   // First check if immediate type is legal. If not, we can't use the ri form.
Index: llvm/lib/Target/PowerPC/PPCFastISel.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCFastISel.cpp
+++ llvm/lib/Target/PowerPC/PPCFastISel.cpp
@@ -111,7 +111,7 @@
     bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
                              const LoadInst *LI) override;
     bool fastLowerArguments() override;
-    unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
+    unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, int64_t Imm) override;
     unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
                              const TargetRegisterClass *RC,
                              unsigned Op0, bool Op0IsKill,
@@ -2279,7 +2279,7 @@
 
 // Handle materializing integer constants into a register.  This is not
 // automatically generated for PowerPC, so must be explicitly created here.
-unsigned PPCFastISel::fastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) {
+unsigned PPCFastISel::fastEmit_i(MVT Ty, MVT VT, unsigned Opc, int64_t Imm) {
 
   if (Opc != ISD::Constant)
     return 0;
Index: llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll
===================================================================
--- llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll
+++ llvm/test/CodeGen/AArch64/arm64-fast-isel-call.ll
@@ -84,7 +84,7 @@
 ; CHECK:       orr [[REG2:w[0-9]+]], wzr, #0x3ff
 ; CHECK:       orr [[REG3:w[0-9]+]], wzr, #0x2
 ; CHECK:       mov [[REG4:w[0-9]+]], wzr
-; CHECK:       orr [[REG5:w[0-9]+]], wzr, #0x1
+; CHECK:       mov [[REG5:w[0-9]+]], #-1
 ; CHECK:       mov x0, [[REG1]]
 ; CHECK:       uxth w2, [[REG2]]
 ; CHECK:       sxtb w3, [[REG3]]
Index: llvm/utils/TableGen/FastISelEmitter.cpp
===================================================================
--- llvm/utils/TableGen/FastISelEmitter.cpp
+++ llvm/utils/TableGen/FastISelEmitter.cpp
@@ -287,7 +287,7 @@
       if (Operands[i].isReg()) {
         OS << "unsigned Op" << i << ", bool Op" << i << "IsKill";
       } else if (Operands[i].isImm()) {
-        OS << "uint64_t imm" << i;
+        OS << "int64_t imm" << i;
       } else if (Operands[i].isFP()) {
         OS << "const ConstantFP *f" << i;
       } else {