This is an archive of the discontinued LLVM Phabricator instance.

AMDGPU/SI: LowerParameter() should be computing align based on memory type
ClosedPublic

Authored by • tstellarAMD on Oct 3 2016, 11:24 AM.

Download Raw Diff

Details

Reviewers

Commits

rG083f1626f540: AMDGPU/SI: LowerParameter() should be computing align based on memory type
rL284398: AMDGPU/SI: LowerParameter() should be computing align based on memory type

Diff Detail

Repository: rL LLVM

Event Timeline

• tstellarAMD updated this revision to Diff 73310.Oct 3 2016, 11:24 AM

• tstellarAMD retitled this revision from to AMDGPU/SI: LowerParameter() should be computing align based on memory type.

• tstellarAMD updated this object.

• tstellarAMD added a reviewer: arsenm.

• tstellarAMD added a subscriber: llvm-commits.

Herald added subscribers: tony-tye, yaxunl, nhaehnle and 2 others. · View Herald TranscriptOct 3 2016, 11:24 AM

LGTM

This revision is now accepted and ready to land.Oct 3 2016, 5:57 PM

Closed by commit rL284398: AMDGPU/SI: LowerParameter() should be computing align based on memory type (authored by tstellar). · Explain WhyOct 17 2016, 10:05 AM

This revision was automatically updated to reflect the committed changes.

Revision Contents

Path

Size

llvm/

trunk/

lib/

Target/

AMDGPU/

SIISelLowering.cpp

2 lines

Diff 74866

llvm/trunk/lib/Target/AMDGPU/SIISelLowering.cpp

Show First 20 Lines • Show All 580 Lines • ▼ Show 20 Lines	SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
MRI.getLiveInVirtReg(InputPtrReg), PtrVT);		MRI.getLiveInVirtReg(InputPtrReg), PtrVT);
return DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,		return DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
DAG.getConstant(Offset, SL, PtrVT));		DAG.getConstant(Offset, SL, PtrVT));
}		}
SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,		SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
const SDLoc &SL, SDValue Chain,		const SDLoc &SL, SDValue Chain,
unsigned Offset, bool Signed) const {		unsigned Offset, bool Signed) const {
const DataLayout &DL = DAG.getDataLayout();		const DataLayout &DL = DAG.getDataLayout();
Type Ty = VT.getTypeForEVT(DAG.getContext());		Type Ty = MemVT.getTypeForEVT(DAG.getContext());
PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);		PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));		MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));

unsigned Align = DL.getABITypeAlignment(Ty);		unsigned Align = DL.getABITypeAlignment(Ty);

SDValue Ptr = LowerParameterPtr(DAG, SL, Chain, Offset);		SDValue Ptr = LowerParameterPtr(DAG, SL, Chain, Offset);
SDValue Load = DAG.getLoad(MemVT, SL, Chain, Ptr, PtrInfo, Align,		SDValue Load = DAG.getLoad(MemVT, SL, Chain, Ptr, PtrInfo, Align,
MachineMemOperand::MONonTemporal \|		MachineMemOperand::MONonTemporal \|
▲ Show 20 Lines • Show All 3,472 Lines • Show Last 20 Lines