[x86][inline-asm][AVX512][clang][PART-1] Introducing "k" and "Yk" constraints for extended inline assembly, enabling use of AVX512 masked vectorized instructions.

[mharoush]

Summary

Extending inline assembly support, compatible with GCC as folowing:
"k" constraint hints the compiler to select any of AVX512 k0-k7 registers.
"Yk" constraint is a subset of "k" excluding k0 which is not allowd to be used as a mask.

This patch is complimented by the following review:
D25062

[rnk]

test/CodeGen/avx512-mask-op-inline_asm_specific.c

1 ↗

(On Diff #72953)

Please check the generated LLVM IR, not the assembly.

[mharoush]

I renamed the test file to be more informative, added LLVM_FALLTHROUGH, removed check of {z} and changed the test to check LLVM IR.

[rnk]

test/CodeGen/avx512-kconstraints-att_inline_asm.c

6 ↗

(On Diff #75277)

The LLVM IR won't have #APP markers in it. Does this test really pass?

[mharoush]

Only test affected(correct version this time: checking LLVM IR instead of x86 asm),
This test depends on D25012 being applied.

test/CodeGen/avx512-kconstraints-att_inline_asm.c

6 ↗

(On Diff #75277)

Sorry I uploaded the wrong patch file.

[rnk]

lgtm

cfe/trunk/lib/Basic/Targets.cpp

case 'Y': // 'Y' is the first character for several 2-character constraints.
     Name++;
     switch (*Name) {
     default:
       return false;
     case '0': // First SSE register.
     case 't': // Any SSE register, when SSE2 is enabled.
     case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled.
     case 'm': // Any MMX register, when inter-unit moves enabled.
+    case 'k': // AVX512 arch mask registers: k1-k7.
       Info.setAllowsRegister();
       return true;
     }
   case 'f': // Any x87 floating point stack register.
     // Constraint 'f' cannot be used for output operands.
     if (Info.ConstraintStr[0] == '=')
       return false;
     Info.setAllowsRegister();
     return true;
   case 'a': // eax.
   case 'b': // ebx.
   case 'c': // ecx.
   case 'd': // edx.
   case 'S': // esi.
   case 'D': // edi.
   case 'A': // edx:eax.
   case 't': // Top of floating point stack.
   case 'u': // Second from top of floating point stack.
   case 'q': // Any register accessible as [r]l: a, b, c, and d.
   case 'y': // Any MMX register.
   case 'x': // Any SSE register.
+  case 'k': // Any AVX512 mask register (same as Yk, additionaly allows k0
+            // for intermideate k reg operations).
   case 'Q': // Any register accessible as [r]h: a, b, c, and d.
   case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp.
   case 'l': // "Index" registers: any general register that can be used as an
             // index in a base+index memory access.
     Info.setAllowsRegister();
     return true;
   // Floating point constant constraints.
   case 'C': // SSE floating point constant.
bool X86TargetInfo::validateInputSize(StringRef Constraint,
                                       unsigned Size) const {
   return validateOperandSize(Constraint, Size);
 }
 
 bool X86TargetInfo::validateOperandSize(StringRef Constraint,
                                         unsigned Size) const {
   switch (Constraint[0]) {
   default: break;
+  case 'k':
+  // Registers k0-k7 (AVX512) size limit is 64 bit.
   case 'y':
     return Size <= 64;
   case 'f':
   case 't':
   case 'u':
     return Size <= 128;
   case 'x':
     if (SSELevel >= AVX512F)
       // 512-bit zmm registers can be used if target supports AVX512F.
       return Size <= 512U;
     else if (SSELevel >= AVX)
       // 256-bit ymm registers can be used if target supports AVX.
       return Size <= 256U;
     return Size <= 128U;
   case 'Y':
     // 'Y' is the first character for several 2-character constraints.
     switch (Constraint[1]) {
     default: break;
     case 'm':
       // 'Ym' is synonymous with 'y'.
+    case 'k':
       return Size <= 64;
     case 'i':
     case 't':
       // 'Yi' and 'Yt' are synonymous with 'x' when SSE2 is enabled.
       if (SSELevel >= AVX512F)
         return Size <= 512U;
       else if (SSELevel >= AVX)
         return Size <= 256U;
X86TargetInfo::convertConstraint(const char *&Constraint) const {
   case 'S': return std::string("{si}");
   case 'D': return std::string("{di}");
   case 'p': // address
     return std::string("im");
   case 't': // top of floating point stack.
     return std::string("{st}");
   case 'u': // second from top of floating point stack.
     return std::string("{st(1)}"); // second from top of floating point stack.
+  case 'Y':
+    switch (Constraint[1]) {
+    default:
+      // Break from inner switch and fall through (copy single char),
+      // continue parsing after copying the current constraint into 
+      // the return string.
+      break;
+    case 'k':
+      // "^" hints llvm that this is a 2 letter constraint.
+      // "Constraint++" is used to promote the string iterator 
+      // to the next constraint.
+      return std::string("^") + std::string(Constraint++, 2);
+    } 
+    LLVM_FALLTHROUGH;
   default:
     return std::string(1, *Constraint);
   }
 }
 
 // X86-32 generic target
 class X86_32TargetInfo : public X86TargetInfo {
 public:

cfe/trunk/test/CodeGen/avx512-kconstraints-att_inline_asm.c

+// RUN: %clang_cc1 %s -triple=x86_64-apple-darwin -target-cpu skylake-avx512 -O0  -emit-llvm -S -o - -Wall -Werror | FileCheck %s
+// This test checks validity of att\gcc style inline assmebly for avx512 k and Yk constraints.
+// Also checks mask register allows flexible type (size <= 64 bit)
+
+void mask_Yk_i8(char msk){ 
+//CHECK: vpaddb %xmm1, %xmm0, %xmm1 {%k1}
+ asm ("vpaddb\t %%xmm1, %%xmm0, %%xmm1 %{%0%}\t"
+       :                //output
+       : "Yk" (msk));   //inputs
+}
+
+void mask_Yk_i16(short msk){
+//CHECK: vpaddb %xmm1, %xmm0, %xmm1 {%k1}
+ asm ("vpaddb\t %%xmm1, %%xmm0, %%xmm1 %{%0%}\t"
+       :                //output
+       :  "Yk" (msk));  //inputs
+}
+
+void mask_Yk_i32(int msk){
+//CHECK: vpaddb %xmm1, %xmm0, %xmm1 {%k1}
+    asm ("vpaddb\t %%xmm1, %%xmm0, %%xmm1 %{%0%}\t"
+       :                //output
+       :  "Yk" (msk));   //inputs
+}
+
+void mask_Yk_i64(long long msk){
+//CHECK: vpaddb %xmm1, %xmm0, %xmm1 {%k1}
+ asm ("vpaddb\t %%xmm1, %%xmm0, %%xmm1 %{%0%}\t"
+       :                //output
+       :  "Yk" (msk));   //inputs
+}
+
+void k_wise_op_i8(char msk_dst,char msk_src1,char msk_src2){
+//CHECK: kandw %k1, %k0, %k0
+ asm ("kandw\t%2, %1, %0"
+       : "=k" (msk_dst)
+       : "k" (msk_src1), "k" (msk_src2));
+}
+
+void k_wise_op_i16(short msk_dst, short msk_src1, short msk_src2){
+//CHECK: kandw %k1, %k0, %k0
+  asm ("kandw\t%2, %1, %0"
+       : "=k" (msk_dst)
+       : "k" (msk_src1), "k" (msk_src2));
+}
+
+void k_wise_op_i32(int msk_dst, int msk_src1, int msk_src2){
+//CHECK: kandw %k1, %k0, %k0
+  asm ("kandw\t%2, %1, %0"
+       : "=k" (msk_dst)
+       : "k" (msk_src1), "k" (msk_src2));
+}
+
+void k_wise_op_i64(long long msk_dst, long long msk_src1, long long msk_src2){
+//CHECK: kandw %k1, %k0, %k0
+  asm ("kandw\t%2, %1, %0"
+       : "=k" (msk_dst)
+       : "k" (msk_src1), "k" (msk_src2));
+}