Index: lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- lib/Target/X86/X86ISelLowering.cpp
+++ lib/Target/X86/X86ISelLowering.cpp
@@ -31957,6 +31957,7 @@
     case 'u':
     case 'y':
     case 'x':
+    case 'v':
     case 'Y':
     case 'l':
       return C_RegisterClass;
@@ -32026,6 +32027,10 @@
     if (type->isX86_MMXTy() && Subtarget.hasMMX())
       weight = CW_SpecificReg;
     break;
+  case 'v':
+    if ((type->getPrimitiveSizeInBits() == 512) && Subtarget.hasAVX512())
+      weight = CW_Register;
+    LLVM_FALLTHROUGH;
   case 'x':
   case 'Y':
     if (((type->getPrimitiveSizeInBits() == 128) && Subtarget.hasSSE1()) ||
@@ -32362,17 +32367,23 @@
     case 'Y':   // SSE_REGS if SSE2 allowed
       if (!Subtarget.hasSSE2()) break;
       LLVM_FALLTHROUGH;
+    case 'v':
     case 'x':   // SSE_REGS if SSE1 allowed or AVX_REGS if AVX allowed
       if (!Subtarget.hasSSE1()) break;
+      bool VConstraint = (Constraint[0] == 'v');
 
       switch (VT.SimpleTy) {
       default: break;
       // Scalar SSE types.
       case MVT::f32:
       case MVT::i32:
+        if (VConstraint && Subtarget.hasAVX512() && Subtarget.hasVLX())
+          return std::make_pair(0U, &X86::FR32XRegClass);
         return std::make_pair(0U, &X86::FR32RegClass);
       case MVT::f64:
       case MVT::i64:
+        if (VConstraint && Subtarget.hasAVX512() && Subtarget.hasVLX())
+          return std::make_pair(0U, &X86::FR64XRegClass);
         return std::make_pair(0U, &X86::FR64RegClass);
       // TODO: Handle f128 and i128 in FR128RegClass after it is tested well.
       // Vector types.
@@ -32382,6 +32393,8 @@
       case MVT::v2i64:
       case MVT::v4f32:
       case MVT::v2f64:
+        if (VConstraint && Subtarget.hasAVX512() && Subtarget.hasVLX())
+          return std::make_pair(0U, &X86::VR128XRegClass);
         return std::make_pair(0U, &X86::VR128RegClass);
       // AVX types.
       case MVT::v32i8:
@@ -32390,6 +32403,8 @@
       case MVT::v4i64:
       case MVT::v8f32:
       case MVT::v4f64:
+        if (VConstraint && Subtarget.hasAVX512() && Subtarget.hasVLX())
+          return std::make_pair(0U, &X86::VR256XRegClass);
         return std::make_pair(0U, &X86::VR256RegClass);
       case MVT::v8f64:
       case MVT::v16f32:
Index: test/CodeGen/X86/inline-asm-avx-v-constraint.ll
===================================================================
--- test/CodeGen/X86/inline-asm-avx-v-constraint.ll
+++ test/CodeGen/X86/inline-asm-avx-v-constraint.ll
@@ -0,0 +1,16 @@
+; RUN: llc < %s -march x86-64 -mtriple x86_64-unknown-linux-gnu -mattr +avx | FileCheck %s
+
+; CHECK: vmovhlps        %xmm1, %xmm0, %xmm0
+define <4 x float> @testXMM(<4 x float> %_xmm0, i64 %_l) local_unnamed_addr {
+entry:
+  %0 = tail call <4 x float> asm "vmovhlps $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(i64 %_l, <4 x float> %_xmm0)
+  ret <4 x float> %0
+}
+
+; CHECK: vmovsldup       %ymm0, %ymm0
+define <8 x float> @testYMM(<8 x float> %_ymm0) local_unnamed_addr {
+entry:
+  %0 = tail call <8 x float> asm "vmovsldup $1, $0", "=v,v,~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm0)
+  ret <8 x float> %0
+}
+
Index: test/CodeGen/X86/inline-asm-avx512f-v-constraint.ll
===================================================================
--- test/CodeGen/X86/inline-asm-avx512f-v-constraint.ll
+++ test/CodeGen/X86/inline-asm-avx512f-v-constraint.ll
@@ -0,0 +1,10 @@
+; RUN: llc < %s -march x86-64 -mtriple x86_64-unknown-linux-gnu -mattr +avx512vl | FileCheck %s
+; RUN: llc < %s -march x86-64 -mtriple x86_64-unknown-linux-gnu -mattr +avx512f -mattr -avx512vl | FileCheck %s
+
+; CHECK: vpternlogd      $0, %zmm1, %zmm0
+define <16 x float> @testZMM(<16 x float> %_zmm0, <16 x float> %_zmm1) local_unnamed_addr {
+entry:
+  %0 = tail call <16 x float> asm "vpternlogd $$0, $1, $2, $0", "=v,v,v,~{dirflag},~{fpsr},~{flags}"(<16 x float> %_zmm1, <16 x float> %_zmm0)
+  ret <16 x float> %0
+}
+
Index: test/CodeGen/X86/inline-asm-avx512vl-v-constraint.ll
===================================================================
--- test/CodeGen/X86/inline-asm-avx512vl-v-constraint.ll
+++ test/CodeGen/X86/inline-asm-avx512vl-v-constraint.ll
@@ -0,0 +1,17 @@
+; RUN: llc < %s -march x86-64 -mtriple x86_64-unknown-linux-gnu -mattr +avx512VL | FileCheck %s
+
+; CHECK: vmovhlps        %xmm17, %xmm16, %xmm16
+define <4 x float> @testXMM(<4 x float> %_xmm0, i64 %_l) local_unnamed_addr {
+entry:
+  %0 = tail call <4 x float> asm "vmovhlps $1, $2, $0", "=v,v,v,~{xmm0},~{xmm1},~{xmm2},~{xmm3},~{xmm4},~{xmm5},~{xmm6},~{xmm7},~{xmm8},~{xmm9},~{xmm10},~{xmm11},~{xmm12},~{xmm13},~{xmm14},~{xmm15},~{dirflag},~{fpsr},~{flags}"(i64 %_l, <4 x float> %_xmm0)
+  ret <4 x float> %0
+}
+
+; CHECK: vmovsldup       %ymm16, %ymm16
+define <8 x float> @testYMM(<8 x float> %_ymm0) local_unnamed_addr {
+entry:
+  %0 = tail call <8 x float> asm "vmovsldup $1, $0", "=v,v,~{ymm0},~{ymm1},~{ymm2},~{ymm3},~{ymm4},~{ymm5},~{ymm6},~{ymm7},~{ymm8},~{ymm9},~{ymm10},~{ymm11},~{ymm12},~{ymm13},~{ymm14},~{ymm15},~{dirflag},~{fpsr},~{flags}"(<8 x float> %_ymm0)
+  ret <8 x float> %0
+}
+
+