Index: llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -41,6 +41,7 @@
 #include "llvm/Support/MathExtras.h"
 
 using namespace llvm;
+using namespace llvm::AMDGPU;
 
 namespace {
 
@@ -2008,15 +2009,16 @@
   int CntShift;
   int CntMask;
 
+  IsaVersion IV = getIsaVersion(getSTI().getFeatureBits());
   if (CntName == "vmcnt") {
-    CntMask = 0xf;
-    CntShift = 0;
+    CntMask = getVmcntMask(IV);
+    CntShift = getVmcntShift(IV);
   } else if (CntName == "expcnt") {
-    CntMask = 0x7;
-    CntShift = 4;
+    CntMask = getExpcntMask(IV);
+    CntShift = getExpcntShift(IV);
   } else if (CntName == "lgkmcnt") {
-    CntMask = 0xf;
-    CntShift = 8;
+    CntMask = getLgkmcntMask(IV);
+    CntShift = getLgkmcntShift(IV);
   } else {
     return true;
   }
Index: llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
+++ llvm/trunk/lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
@@ -9,19 +9,22 @@
 //===----------------------------------------------------------------------===//
 
 #include "AMDGPUInstPrinter.h"
-#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 #include "SIDefines.h"
+#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 #include "Utils/AMDGPUAsmUtils.h"
+#include "Utils/AMDGPUBaseInfo.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrInfo.h"
 #include "llvm/MC/MCRegisterInfo.h"
+#include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 
 #include <string>
 
 using namespace llvm;
+using namespace llvm::AMDGPU;
 
 void AMDGPUInstPrinter::printInst(const MCInst *MI, raw_ostream &OS,
                                   StringRef Annot, const MCSubtargetInfo &STI) {
@@ -864,10 +867,12 @@
 void AMDGPUInstPrinter::printWaitFlag(const MCInst *MI, unsigned OpNo,
                                       const MCSubtargetInfo &STI,
                                       raw_ostream &O) {
+  IsaVersion IV = getIsaVersion(STI.getFeatureBits());
+
   unsigned SImm16 = MI->getOperand(OpNo).getImm();
-  unsigned Vmcnt = SImm16 & 0xF;
-  unsigned Expcnt = (SImm16 >> 4) & 0x7;
-  unsigned Lgkmcnt = (SImm16 >> 8) & 0xF;
+  unsigned Vmcnt = (SImm16 >> getVmcntShift(IV)) & getVmcntMask(IV);
+  unsigned Expcnt = (SImm16 >> getExpcntShift(IV)) & getExpcntMask(IV);
+  unsigned Lgkmcnt = (SImm16 >> getLgkmcntShift(IV)) & getLgkmcntMask(IV);
 
   bool NeedSpace = false;
 
Index: llvm/trunk/lib/Target/AMDGPU/SIInsertWaits.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/SIInsertWaits.cpp
+++ llvm/trunk/lib/Target/AMDGPU/SIInsertWaits.cpp
@@ -21,6 +21,7 @@
 #include "SIDefines.h"
 #include "SIInstrInfo.h"
 #include "SIMachineFunctionInfo.h"
+#include "Utils/AMDGPUBaseInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
@@ -29,6 +30,7 @@
 #define DEBUG_TYPE "si-insert-waits"
 
 using namespace llvm;
+using namespace llvm::AMDGPU;
 
 namespace {
 
@@ -59,6 +61,7 @@
   const SIInstrInfo *TII;
   const SIRegisterInfo *TRI;
   const MachineRegisterInfo *MRI;
+  IsaVersion IV;
 
   /// \brief Constant hardware limits
   static const Counters WaitCounts;
@@ -410,9 +413,9 @@
 
   // Build the wait instruction
   BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::S_WAITCNT))
-          .addImm((Counts.Named.VM & 0xF) |
-                  ((Counts.Named.EXP & 0x7) << 4) |
-                  ((Counts.Named.LGKM & 0xF) << 8));
+    .addImm(((Counts.Named.VM & getVmcntMask(IV)) << getVmcntShift(IV)) |
+            ((Counts.Named.EXP & getExpcntMask(IV)) << getExpcntShift(IV)) |
+            ((Counts.Named.LGKM & getLgkmcntMask(IV)) << getLgkmcntShift(IV)));
 
   LastOpcodeType = OTHER;
   LastInstWritesM0 = false;
@@ -440,9 +443,9 @@
   unsigned Imm = I->getOperand(0).getImm();
   Counters Counts, WaitOn;
 
-  Counts.Named.VM = Imm & 0xF;
-  Counts.Named.EXP = (Imm >> 4) & 0x7;
-  Counts.Named.LGKM = (Imm >> 8) & 0xF;
+  Counts.Named.VM = (Imm >> getVmcntShift(IV)) & getVmcntMask(IV);
+  Counts.Named.EXP = (Imm >> getExpcntShift(IV)) & getExpcntMask(IV);
+  Counts.Named.LGKM = (Imm >> getLgkmcntShift(IV)) & getLgkmcntMask(IV);
 
   for (unsigned i = 0; i < 3; ++i) {
     if (Counts.Array[i] <= LastIssued.Array[i])
@@ -518,6 +521,7 @@
   TII = ST->getInstrInfo();
   TRI = &TII->getRegisterInfo();
   MRI = &MF.getRegInfo();
+  IV = getIsaVersion(ST->getFeatureBits());
 
   WaitedOn = ZeroCounts;
   DelayedWaitOn = ZeroCounts;
Index: llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -69,6 +69,24 @@
                                             std::pair<int, int> Default,
                                             bool OnlyFirstRequired = false);
 
+/// \returns VMCNT bit mask for given isa \p Version.
+unsigned getVmcntMask(IsaVersion Version);
+
+/// \returns VMCNT bit shift for given isa \p Version.
+unsigned getVmcntShift(IsaVersion Version);
+
+/// \returns EXPCNT bit mask for given isa \p Version.
+unsigned getExpcntMask(IsaVersion Version);
+
+/// \returns EXPCNT bit shift for given isa \p Version.
+unsigned getExpcntShift(IsaVersion Version);
+
+/// \returns LGKMCNT bit mask for given isa \p Version.
+unsigned getLgkmcntMask(IsaVersion Version);
+
+/// \returns LGKMCNT bit shift for given isa \p Version.
+unsigned getLgkmcntShift(IsaVersion Version);
+
 unsigned getInitialPSInputAddr(const Function &F);
 
 bool isShader(CallingConv::ID cc);
Index: llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ llvm/trunk/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -152,6 +152,30 @@
   return Ints;
 }
 
+unsigned getVmcntMask(IsaVersion Version) {
+  return 0xf;
+}
+
+unsigned getVmcntShift(IsaVersion Version) {
+  return 0;
+}
+
+unsigned getExpcntMask(IsaVersion Version) {
+  return 0x7;
+}
+
+unsigned getExpcntShift(IsaVersion Version) {
+  return 4;
+}
+
+unsigned getLgkmcntMask(IsaVersion Version) {
+  return 0xf;
+}
+
+unsigned getLgkmcntShift(IsaVersion Version) {
+  return 8;
+}
+
 unsigned getInitialPSInputAddr(const Function &F) {
   return getIntegerAttribute(F, "InitialPSInputAddr", 0);
 }