Index: lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
===================================================================
--- lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
+++ lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
@@ -12,6 +12,7 @@
 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
 #include "SIDefines.h"
 #include "Utils/AMDGPUAsmUtils.h"
+#include "Utils/AMDGPUBaseInfo.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCInst.h"
 #include "llvm/MC/MCInstrInfo.h"
@@ -390,10 +391,10 @@
     const MCInstrDesc &Desc = MII.get(MI->getOpcode());
     int RCID = Desc.OpInfo[OpNo].RegClass;
     if (RCID != -1) {
-      const MCRegisterClass &ImmRC = MRI.getRegClass(RCID);
-      if (ImmRC.getSize() == 4)
+      unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
+      if (RCBits == 32)
         printImmediate32(Op.getImm(), O);
-      else if (ImmRC.getSize() == 8)
+      else if (RCBits == 64)
         printImmediate64(Op.getImm(), O);
       else
         llvm_unreachable("Invalid register class size");
@@ -411,11 +412,11 @@
       O << "0.0";
     else {
       const MCInstrDesc &Desc = MII.get(MI->getOpcode());
-      const MCRegisterClass &ImmRC = MRI.getRegClass(Desc.OpInfo[OpNo].RegClass);
-
-      if (ImmRC.getSize() == 4)
+      int RCID = Desc.OpInfo[OpNo].RegClass;
+      unsigned RCBits = AMDGPU::getRegBitWidth(MRI.getRegClass(RCID));
+      if (RCBits == 32)
         printImmediate32(FloatToBits(Op.getFPImm()), O);
-      else if (ImmRC.getSize() == 8)
+      else if (RCBits == 64)
         printImmediate64(DoubleToBits(Op.getFPImm()), O);
       else
         llvm_unreachable("Invalid register class size");
Index: lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
===================================================================
--- lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
+++ lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
@@ -214,7 +214,7 @@
 
     // Is this operand a literal immediate?
     const MCOperand &Op = MI.getOperand(i);
-    if (getLitEncoding(Op, RC.getSize(), STI) != 255)
+    if (getLitEncoding(Op, AMDGPU::getRegBitWidth(RC)/8, STI) != 255)
       continue;
 
     // Yes! Encode it
Index: lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
===================================================================
--- lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
+++ lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
@@ -20,6 +20,7 @@
 class GlobalValue;
 class MCContext;
 class MCInstrDesc;
+class MCRegisterClass;
 class MCRegisterInfo;
 class MCSection;
 class MCSubtargetInfo;
@@ -91,6 +92,9 @@
 /// \brief Does this opearnd support only inlinable literals?
 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
 
+/// \brief Get the size in bits of a register from the register class \p RC.
+unsigned getRegBitWidth(const MCRegisterClass &RC);
+
 /// \brief Get size of register operand
 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
                            unsigned OpNo);
Index: lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
===================================================================
--- lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
+++ lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
@@ -226,11 +226,76 @@
          OpType == AMDGPU::OPERAND_REG_INLINE_C_FP;
 }
 
+// Avoid using MCRegisterClass::getSize, since that function will go away
+// (move from MC* level to Target* level). Return size in bits.
+unsigned getRegBitWidth(const MCRegisterClass &RC) {
+  switch (RC.getID()) {
+  case AMDGPU::SCC_CLASSRegClassID:
+    return 1;
+  case AMDGPU::SGPR_32RegClassID:
+  case AMDGPU::TTMP_32RegClassID:
+  case AMDGPU::VGPR_32RegClassID:
+  case AMDGPU::SReg_32_XM0RegClassID:
+  case AMDGPU::SReg_32RegClassID:
+  case AMDGPU::VReg_1RegClassID:
+  case AMDGPU::VS_32RegClassID:
+  case AMDGPU::R600_ArrayBaseRegClassID:
+  case AMDGPU::R600_AddrRegClassID:
+  case AMDGPU::R600_Addr_YRegClassID:
+  case AMDGPU::R600_Addr_ZRegClassID:
+  case AMDGPU::R600_Addr_WRegClassID:
+  case AMDGPU::R600_LDS_SRC_REGRegClassID:
+  case AMDGPU::R600_KC0_XRegClassID:
+  case AMDGPU::R600_KC0_YRegClassID:
+  case AMDGPU::R600_KC0_ZRegClassID:
+  case AMDGPU::R600_KC0_WRegClassID:
+  case AMDGPU::R600_KC0RegClassID:
+  case AMDGPU::R600_KC1_XRegClassID:
+  case AMDGPU::R600_KC1_YRegClassID:
+  case AMDGPU::R600_KC1_ZRegClassID:
+  case AMDGPU::R600_KC1_WRegClassID:
+  case AMDGPU::R600_KC1RegClassID:
+  case AMDGPU::R600_TReg32_XRegClassID:
+  case AMDGPU::R600_TReg32_YRegClassID:
+  case AMDGPU::R600_TReg32_ZRegClassID:
+  case AMDGPU::R600_TReg32_WRegClassID:
+  case AMDGPU::R600_TReg32RegClassID:
+  case AMDGPU::R600_Reg32RegClassID:
+  case AMDGPU::R600_PredicateRegClassID:
+  case AMDGPU::R600_Predicate_BitRegClassID:
+  case AMDGPU::R600_Reg128RegClassID:
+    return 32;
+  case AMDGPU::SGPR_64RegClassID:
+  case AMDGPU::TTMP_64RegClassID:
+  case AMDGPU::SReg_64RegClassID:
+  case AMDGPU::VReg_64RegClassID:
+  case AMDGPU::VS_64RegClassID:
+  case AMDGPU::R600_Reg64RegClassID:
+  case AMDGPU::R600_Reg64VerticalRegClassID:
+    return 64;
+  case AMDGPU::VReg_96RegClassID:
+    return 96;
+  case AMDGPU::SGPR_128RegClassID:
+  case AMDGPU::TTMP_128RegClassID:
+  case AMDGPU::SReg_128RegClassID:
+  case AMDGPU::VReg_128RegClassID:
+  case AMDGPU::R600_Reg128VerticalRegClassID:
+    return 128;
+  case AMDGPU::VReg_256RegClassID:
+  case AMDGPU::SReg_256RegClassID:
+    return 256;
+  case AMDGPU::SReg_512RegClassID:
+  case AMDGPU::VReg_512RegClassID:
+    return 512;
+  default:
+    llvm_unreachable("Unexpected register class");
+  }
+}
+
 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
                            unsigned OpNo) {
-  int RCID = Desc.OpInfo[OpNo].RegClass;
-  const MCRegisterClass &RC = MRI->getRegClass(RCID);
-  return RC.getSize();
+  unsigned RCID = Desc.OpInfo[OpNo].RegClass;
+  return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
 }
 
 bool isInlinableLiteral64(int64_t Literal, bool IsVI) {