Index: llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/trunk/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -13064,13 +13064,6 @@
     Mask[i] = Vec2Offset + ExtIndex;
   }
 
-  // Avoid introducing illegal shuffles with zero.
-  // TODO: This doesn't actually do anything smart at the moment.
-  // We should either delete this, or check legality for all the shuffles
-  // we create.
-  if (UsesZeroVector && !TLI.isVectorClearMaskLegal(Mask, VT))
-    return SDValue();
-
   // The type the input vectors may have changed above.
   InVT1 = VecIn1.getValueType();
 
Index: llvm/trunk/test/CodeGen/AMDGPU/r600-export-fix.ll
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/r600-export-fix.ll
+++ llvm/trunk/test/CodeGen/AMDGPU/r600-export-fix.ll
@@ -3,9 +3,9 @@
 ;CHECK:	EXPORT T{{[0-9]}}.XYZW
 ;CHECK:	EXPORT T{{[0-9]}}.0000
 ;CHECK: EXPORT T{{[0-9]}}.0000
-;CHECK: EXPORT T{{[0-9]}}.0XYZ
+;CHECK: EXPORT T{{[0-9]}}.0YZW
 ;CHECK: EXPORT T{{[0-9]}}.XYZW
-;CHECK: EXPORT T{{[0-9]}}.YZ00
+;CHECK: EXPORT T{{[0-9]}}.XY00
 ;CHECK: EXPORT T{{[0-9]}}.0000
 ;CHECK: EXPORT T{{[0-9]}}.0000
 
Index: llvm/trunk/test/CodeGen/SystemZ/vec-perm-13.ll
===================================================================
--- llvm/trunk/test/CodeGen/SystemZ/vec-perm-13.ll
+++ llvm/trunk/test/CodeGen/SystemZ/vec-perm-13.ll
@@ -19,8 +19,8 @@
 ; CHECK-VECTOR-NEXT: .space  1                                        
 ; CHECK-VECTOR-NEXT: .byte   6
 ; CHECK-VECTOR-NEXT: .byte   7
-; CHECK-VECTOR-NEXT: .byte   16
-; CHECK-VECTOR-NEXT: .byte   17
+; CHECK-VECTOR-NEXT: .byte   22
+; CHECK-VECTOR-NEXT: .byte   23
 ; CHECK-VECTOR-NEXT: .space  1                                        
 ; CHECK-VECTOR-NEXT: .space  1                                        
 ; CHECK-VECTOR-NEXT: .space  1