Index: lib/Target/AAP/CMakeLists.txt
===================================================================
--- lib/Target/AAP/CMakeLists.txt
+++ lib/Target/AAP/CMakeLists.txt
@@ -2,15 +2,18 @@
 
 tablegen(LLVM AAPGenRegisterInfo.inc       -gen-register-info)
 tablegen(LLVM AAPGenInstrInfo.inc          -gen-instr-info)
+tablegen(LLVM AAPGenDisassemblerTables.inc -gen-disassembler)
 tablegen(LLVM AAPGenMCCodeEmitter.inc      -gen-emitter)
 tablegen(LLVM AAPGenAsmWriter.inc          -gen-asm-writer)
 tablegen(LLVM AAPGenAsmMatcher.inc         -gen-asm-matcher)
+tablegen(LLVM AAPGenSubtargetInfo.inc      -gen-subtarget)
 add_public_tablegen_target(AAPCommonTableGen)
 
 add_llvm_target(AAPCodeGen
   AAPTargetMachine.cpp
 )
 
+add_subdirectory(Disassembler)
 add_subdirectory(InstPrinter)
 add_subdirectory(MCTargetDesc)
 add_subdirectory(TargetInfo)
Index: lib/Target/AAP/Disassembler/AAPDisassembler.h
===================================================================
--- /dev/null
+++ lib/Target/AAP/Disassembler/AAPDisassembler.h
@@ -0,0 +1,36 @@
+//===-- AAPDisassembler.h - AAP Disassembler ----------------------*- C++ -*--//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef AAPDISASSEMBLER_H
+#define AAPDISASSEMBLER_H
+
+#include "llvm/MC/MCDisassembler/MCDisassembler.h"
+
+// Pull DecodeStatus and its enum values into the global namespace.
+typedef llvm::MCDisassembler::DecodeStatus DecodeStatus;
+
+namespace llvm {
+class MCInst;
+class MemoryObject;
+class raw_ostream;
+
+class AAPDisassembler : public MCDisassembler {
+
+public:
+  AAPDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
+      : MCDisassembler(STI, Ctx) {}
+
+  DecodeStatus getInstruction(MCInst &instr, uint64_t &size,
+                              ArrayRef<uint8_t> Bytes, uint64_t address,
+                              raw_ostream &vStream,
+                              raw_ostream &cStream) const override;
+};
+} // namespace llvm
+
+#endif
Index: lib/Target/AAP/Disassembler/AAPDisassembler.cpp
===================================================================
--- /dev/null
+++ lib/Target/AAP/Disassembler/AAPDisassembler.cpp
@@ -0,0 +1,177 @@
+//===-- AAPDisassembler.cpp - Disassembler for AAP ------------*- C++ -*-===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file is part of the AAP Disassembler.
+//
+//===----------------------------------------------------------------------===//
+
+#include "AAPDisassembler.h"
+#include "AAP.h"
+#include "MCTargetDesc/AAPMCTargetDesc.h"
+#include "llvm/MC/MCDisassembler/MCDisassembler.h"
+#include "llvm/MC/MCFixedLenDisassembler.h"
+#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCSubtargetInfo.h"
+#include "llvm/Support/MathExtras.h"
+#include "llvm/Support/TargetRegistry.h"
+
+#define DEBUG_TYPE "AAP-disassembler"
+
+using namespace llvm;
+
+typedef MCDisassembler::DecodeStatus DecodeStatus;
+
+static MCDisassembler *createAAPDisassembler(const Target &T,
+                                             const MCSubtargetInfo &STI,
+                                             MCContext &Ctx) {
+  return new AAPDisassembler(STI, Ctx);
+}
+
+extern "C" void LLVMInitializeAAPDisassembler() {
+  // Register the disassembler
+  TargetRegistry::RegisterMCDisassembler(getTheAAPTarget(),
+                                         createAAPDisassembler);
+}
+
+// Forward declare because the autogenerated code will reference this.
+// Definition is further down.
+DecodeStatus DecodeGR8RegisterClass(MCInst &Inst, unsigned RegNo,
+                                    uint64_t Address, const void *Decoder);
+DecodeStatus DecodeGR64RegisterClass(MCInst &Inst, unsigned RegNo,
+                                     uint64_t Address, const void *Decoder);
+
+DecodeStatus decodeMemSrc3Operand(MCInst &Inst, unsigned Operand,
+                                  uint64_t Address, const void *Decoder);
+DecodeStatus decodeMemSrc10Operand(MCInst &Inst, unsigned Operand,
+                                   uint64_t Address, const void *Decoder);
+
+DecodeStatus decodeOff3Operand(MCInst &Inst, unsigned Operand,
+                               uint64_t Address, const void *Decoder);
+DecodeStatus decodeOff10Operand(MCInst &Inst, unsigned Operand,
+                                uint64_t Address, const void *Decoder);
+
+DecodeStatus decodeShiftOperand(MCInst &Inst, unsigned RegNo, uint64_t Address,
+                                const void *Decoder);
+
+#include "AAPGenDisassemblerTables.inc"
+
+DecodeStatus AAPDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
+                                             ArrayRef<uint8_t> Bytes,
+                                             uint64_t Address, raw_ostream &os,
+                                             raw_ostream &cs) const {
+  uint32_t Insn;
+  DecodeStatus Result;
+
+  // First try a 16-bit instruction
+  if (Bytes.size() < 2) {
+    Size = 0;
+    return MCDisassembler::Fail;
+  }
+  Insn = (Bytes[1] << 8) | (Bytes[0] << 0);
+
+  // Next try generic 16-bit instructions
+  Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);
+  if (Result != MCDisassembler::Fail) {
+    Size = 2;
+    return Result;
+  }
+
+  // Finally try a 32-bit instruction
+  if (Bytes.size() < 4) {
+    Size = 0;
+    return MCDisassembler::Fail;
+  }
+  Insn = (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) |
+         (Bytes[0] << 0);
+
+  // Call auto-generated decoder function
+  Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
+  if (Result != MCDisassembler::Fail) {
+    Size = 4;
+    return Result;
+  }
+
+  // In case of invalid decode, assume it was a short instruction
+  Size = 2;
+  return MCDisassembler::Fail;
+}
+
+static const unsigned AAPRegs8[] = {AAP::R0, AAP::R1, AAP::R2, AAP::R3,
+                                    AAP::R4, AAP::R5, AAP::R6, AAP::R7};
+static const unsigned AAPRegs64[] = {
+    AAP::R0,  AAP::R1,  AAP::R2,  AAP::R3,  AAP::R4,  AAP::R5,  AAP::R6,
+    AAP::R7,  AAP::R8,  AAP::R9,  AAP::R10, AAP::R11, AAP::R12, AAP::R13,
+    AAP::R14, AAP::R15, AAP::R16, AAP::R17, AAP::R18, AAP::R19, AAP::R20,
+    AAP::R21, AAP::R22, AAP::R23, AAP::R24, AAP::R25, AAP::R26, AAP::R27,
+    AAP::R28, AAP::R29, AAP::R30, AAP::R31, AAP::R32, AAP::R33, AAP::R34,
+    AAP::R35, AAP::R36, AAP::R37, AAP::R38, AAP::R39, AAP::R40, AAP::R41,
+    AAP::R42, AAP::R43, AAP::R44, AAP::R45, AAP::R46, AAP::R47, AAP::R48,
+    AAP::R49, AAP::R50, AAP::R51, AAP::R52, AAP::R53, AAP::R54, AAP::R55,
+    AAP::R56, AAP::R57, AAP::R58, AAP::R59, AAP::R60, AAP::R61, AAP::R62,
+    AAP::R63};
+
+template <std::size_t N>
+static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
+                                        const unsigned (&Regs)[N]) {
+  if (RegNo >= N)
+    return MCDisassembler::Fail;
+  Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
+  return MCDisassembler::Success;
+}
+
+DecodeStatus DecodeGR8RegisterClass(MCInst &Inst, unsigned RegNo,
+                                    uint64_t Address, const void *Decoder) {
+  return decodeRegisterClass(Inst, RegNo, AAPRegs8);
+}
+DecodeStatus DecodeGR64RegisterClass(MCInst &Inst, unsigned RegNo,
+                                     uint64_t Address, const void *Decoder) {
+  return decodeRegisterClass(Inst, RegNo, AAPRegs64);
+}
+
+DecodeStatus decodeMemSrc3Operand(MCInst &Inst, unsigned Operand,
+                                  uint64_t Address, const void *Decoder) {
+  unsigned Reg = (Operand >> 16) & 0x7;
+  int32_t Offset = SignExtend32<3>(Operand & 0xffff);
+
+  if (decodeRegisterClass(Inst, Reg, AAPRegs8) == MCDisassembler::Fail)
+    return MCDisassembler::Fail;
+
+  Inst.addOperand(MCOperand::createImm(Offset));
+  return MCDisassembler::Success;
+}
+
+DecodeStatus decodeMemSrc10Operand(MCInst &Inst, unsigned Operand,
+                                   uint64_t Address, const void *Decoder) {
+  unsigned Reg = (Operand >> 16) & 0x3f;
+  int32_t Offset = SignExtend32<10>(Operand & 0xffff);
+
+  if (decodeRegisterClass(Inst, Reg, AAPRegs64) == MCDisassembler::Fail)
+    return MCDisassembler::Fail;
+
+  Inst.addOperand(MCOperand::createImm(Offset));
+  return MCDisassembler::Success;
+}
+
+DecodeStatus decodeOff3Operand(MCInst &Inst, unsigned Operand,
+                               uint64_t Address, const void *Decoder) {
+  Inst.addOperand(MCOperand::createImm(SignExtend32<3>(Operand)));
+  return MCDisassembler::Success;
+}
+
+DecodeStatus decodeOff10Operand(MCInst &Inst, unsigned Operand,
+                                uint64_t Address, const void *Decoder) {
+  Inst.addOperand(MCOperand::createImm(SignExtend32<10>(Operand)));
+  return MCDisassembler::Success;
+}
+
+DecodeStatus decodeShiftOperand(MCInst &Inst, unsigned Operand,
+                                uint64_t Address, const void *Decoder) {
+  Inst.addOperand(MCOperand::createImm(Operand + 1));
+  return MCDisassembler::Success;
+}
Index: lib/Target/AAP/Disassembler/CMakeLists.txt
===================================================================
--- /dev/null
+++ lib/Target/AAP/Disassembler/CMakeLists.txt
@@ -0,0 +1,7 @@
+include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. )
+
+add_llvm_library(LLVMAAPDisassembler
+  AAPDisassembler.cpp
+  )
+
+add_dependencies(LLVMAAPDisassembler AAPCommonTableGen)
Index: lib/Target/AAP/Disassembler/LLVMBuild.txt
===================================================================
--- /dev/null
+++ lib/Target/AAP/Disassembler/LLVMBuild.txt
@@ -0,0 +1,23 @@
+;===- ./lib/Target/AAP/Disassembler/LLVMBuild.txt --------------*- Conf -*--===;
+;
+;                     The LLVM Compiler Infrastructure
+;
+; This file is distributed under the University of Illinois Open Source
+; License. See LICENSE.TXT for details.
+;
+;===------------------------------------------------------------------------===;
+;
+; This is an LLVMBuild description file for the components in this subdirectory.
+;
+; For more information on the LLVMBuild system, please see:
+;
+;   http://llvm.org/docs/LLVMBuild.html
+;
+;===------------------------------------------------------------------------===;
+
+[component_0]
+type = Library
+name = AAPDisassembler
+parent = AAP
+required_libraries = MCDisassembler Support AAPInfo AAPDesc
+add_to_library_groups = AAP
Index: lib/Target/AAP/LLVMBuild.txt
===================================================================
--- lib/Target/AAP/LLVMBuild.txt
+++ lib/Target/AAP/LLVMBuild.txt
@@ -16,7 +16,7 @@
 ;===------------------------------------------------------------------------===;
 
 [common]
-subdirectories = AsmParser InstPrinter MCTargetDesc TargetInfo
+subdirectories = AsmParser Disassembler InstPrinter MCTargetDesc TargetInfo
 
 [component_0]
 type = TargetGroup
@@ -24,6 +24,7 @@
 parent = Target
 has_asmprinter = 1
 has_asmparser = 1
+has_disassembler = 1
 
 [component_1]
 type = Library
Index: lib/Target/AAP/MCTargetDesc/AAPMCTargetDesc.h
===================================================================
--- lib/Target/AAP/MCTargetDesc/AAPMCTargetDesc.h
+++ lib/Target/AAP/MCTargetDesc/AAPMCTargetDesc.h
@@ -53,4 +53,7 @@
 #define GET_INSTRINFO_ENUM
 #include "AAPGenInstrInfo.inc"
 
+#define GET_SUBTARGETINFO_ENUM
+#include "AAPGenSubtargetInfo.inc"
+
 #endif
Index: lib/Target/AAP/MCTargetDesc/AAPMCTargetDesc.cpp
===================================================================
--- lib/Target/AAP/MCTargetDesc/AAPMCTargetDesc.cpp
+++ lib/Target/AAP/MCTargetDesc/AAPMCTargetDesc.cpp
@@ -25,6 +25,9 @@
 #define GET_INSTRINFO_MC_DESC
 #include "AAPGenInstrInfo.inc"
 
+#define GET_SUBTARGETINFO_MC_DESC
+#include "AAPGenSubtargetInfo.inc"
+
 #define GET_REGINFO_MC_DESC
 #include "AAPGenRegisterInfo.inc"
 
@@ -40,6 +43,11 @@
   return X;
 }
 
+static MCSubtargetInfo *createAAPMCSubtargetInfo(const Triple &TT,
+                                                 StringRef CPU, StringRef FS) {
+  return createAAPMCSubtargetInfoImpl(TT, CPU, FS);
+}
+
 static void adjustCodeGenOpts(const Triple &TT, Reloc::Model RM,
                               CodeModel::Model &CM) {
   return;
@@ -71,6 +79,9 @@
   // Register the MC Code Emitter
   TargetRegistry::RegisterMCCodeEmitter(getTheAAPTarget(),
                                         createAAPMCCodeEmitter);
+  // Register the MC subtarget info.
+  TargetRegistry::RegisterMCSubtargetInfo(getTheAAPTarget(),
+                                          createAAPMCSubtargetInfo);
   // Register the MCInstPrinter.
   TargetRegistry::RegisterMCInstPrinter(getTheAAPTarget(),
                                         createAAPMCInstPrinter);
Index: test/MC/Disassembler/AAP/alu.txt
===================================================================
--- /dev/null
+++ test/MC/Disassembler/AAP/alu.txt
@@ -0,0 +1,86 @@
+#RUN: llvm-mc -triple=aap -disassemble -show-encoding < %s | FileCheck %s
+
+# short encodings
+#CHECK: add  $r0, $r0, $r0 ; encoding: [0x00,0x02]
+0x00,0x02
+#CHECK: sub  $r7, $r4, $r3 ; encoding: [0xe3,0x05]
+0xe3,0x05
+#CHECK: and  $r3, $r7, $r0 ; encoding: [0xf8,0x06]
+0xf8,0x06
+#CHECK: or   $r0, $r6, $r6 ; encoding: [0x36,0x08]
+0x36,0x08
+#CHECK: xor  $r7, $r7, $r7 ; encoding: [0xff,0x0b]
+0xff,0x0b
+#CHECK: asr  $r3, $r5, $r1 ; encoding: [0xe9,0x0c]
+0xe9,0x0c
+#CHECK: lsl  $r1, $r1, $r4 ; encoding: [0x4c,0x0e]
+0x4c,0x0e
+#CHECK: lsr  $r3, $r5, $r4 ; encoding: [0xec,0x10]
+0xec,0x10
+
+#CHECK: addi $r0, $r3, 1 ; encoding: [0x19,0x14]
+0x19,0x14
+#CHECK: addi $r7, $r1, 3 ; encoding: [0xcb,0x15]
+0xcb,0x15
+#CHECK: addi $r5, $r3, 7 ; encoding: [0x5f,0x15]
+0x5f,0x15
+#CHECK: subi $r0, $r0, 5 ; encoding: [0x05,0x16]
+0x05,0x16
+#CHECK: subi $r6, $r3, 7 ; encoding: [0x9f,0x17]
+0x9f,0x17
+#CHECK: asri $r3, $r0, 1 ; encoding: [0xc0,0x18]
+0xc0,0x18
+#CHECK: lsli $r7, $r2, 6 ; encoding: [0xd5,0x1b]
+0xd5,0x1b
+#CHECK: lsri $r0, $r7, 8 ; encoding: [0x3f,0x1c]
+0x3f,0x1c
+
+# long encodings
+#CHECK: add  $r7,  $r7,  $r7  ; encoding: [0xff,0x83,0x00,0x00]
+0xff,0x83,0x00,0x00
+#CHECK: sub  $r0,  $r0,  $r8  ; encoding: [0x00,0x84,0x01,0x00]
+0x00,0x84,0x01,0x00
+#CHECK: and  $r15, $r5,  $r2  ; encoding: [0xea,0x87,0x40,0x00]
+0xea,0x87,0x40,0x00
+#CHECK: or   $r12, $r10, $r4  ; encoding: [0x14,0x89,0x48,0x00]
+0x14,0x89,0x48,0x00
+#CHECK: xor  $r63, $r63, $r63 ; encoding: [0xff,0x8b,0xff,0x01]
+0xff,0x8b,0xff,0x01
+#CHECK: asr  $r14, $r32, $r26 ; encoding: [0x82,0x8d,0x63,0x00]
+0x82,0x8d,0x63,0x00
+#CHECK: lsl  $r8,  $r5,  $r21 ; encoding: [0x2d,0x8e,0x42,0x00]
+0x2d,0x8e,0x42,0x00
+#CHECK: lsr  $r44, $r1,  $r0  ; encoding: [0x08,0x91,0x40,0x01]
+0x08,0x91,0x40,0x01
+#CHECK: addc $r0,  $r23, $r0  ; encoding: [0x38,0x82,0x10,0x02]
+0x38,0x82,0x10,0x02
+#CHECK: subc $r32, $r31, $r11 ; encoding: [0x3b,0x84,0x19,0x03]
+0x3b,0x84,0x19,0x03
+
+#CHECK: addi $r5,  $r5,  0    ; encoding: [0x68,0x95,0x00,0x00]
+0x68,0x95,0x00,0x00
+#CHECK: addi $r53, $r63, 567  ; encoding: [0x7f,0x95,0xbe,0x11]
+0x7f,0x95,0xbe,0x11
+#CHECK: addi $r3,  $r12, 1023 ; encoding: [0xe7,0x94,0x0f,0x1e]
+0xe7,0x94,0x0f,0x1e
+#CHECK: subi $r0,  $r16, 11   ; encoding: [0x03,0x96,0x11,0x00]
+0x03,0x96,0x11,0x00
+#CHECK: subi $r33, $r29, 281  ; encoding: [0x69,0x96,0x1b,0x09]
+0x69,0x96,0x1b,0x09
+
+#CHECK: asri $r0,  $r0,  4  ; encoding: [0x03,0x98,0x00,0x00]
+0x03,0x98,0x00,0x00
+#CHECK: lsli $r63, $r63, 63 ; encoding: [0xfe,0x9b,0xff,0x01]
+0xfe,0x9b,0xff,0x01
+#CHECK: lsri $r25, $r16, 15 ; encoding: [0x46,0x9c,0xd1,0x00]
+0x46,0x9c,0xd1,0x00
+
+#CHECK: andi $r5,  $r3,  1   ; encoding: [0x59,0x87,0x00,0x02]
+0x59,0x87,0x00,0x02
+#CHECK: andi $r0,  $r0,  511 ; encoding: [0x07,0x86,0x07,0x1e]
+0x07,0x86,0x07,0x1e
+#CHECK: ori  $r32, $r12, 93  ; encoding: [0x25,0x88,0x0b,0x07]
+0x25,0x88,0x0b,0x07
+#CHECK: xori $r21, $r33, 127 ; encoding: [0x4f,0x8b,0xa7,0x06]
+0x4f,0x8b,0xa7,0x06
+
Index: test/MC/Disassembler/AAP/lit.local.cfg
===================================================================
--- /dev/null
+++ test/MC/Disassembler/AAP/lit.local.cfg
@@ -0,0 +1,2 @@
+if not 'AAP' in config.root.targets:
+    config.unsupported = True
Index: test/MC/Disassembler/AAP/load.txt
===================================================================
--- /dev/null
+++ test/MC/Disassembler/AAP/load.txt
@@ -0,0 +1,55 @@
+#RUN: llvm-mc -triple=aap -disassemble -show-encoding < %s | FileCheck %s
+
+# short encodings
+#CHECK: ldb $r0, [$r0,  0] ; encoding: [0x00,0x20]
+0x00,0x20
+#CHECK: ldb $r2, [$r3,  1] ; encoding: [0x99,0x20]
+0x99,0x20
+#CHECK: ldb $r7, [$r1, -3] ; encoding: [0xcd,0x21]
+0xcd,0x21
+#CHECK: ldb $r3, [$r3, -4] ; encoding: [0xdc,0x20]
+0xdc,0x20
+#CHECK: ldb $r5, [$r7,  3] ; encoding: [0x7b,0x21]
+0x7b,0x21
+
+#CHECK: ldw $r0, [$r3, -3] ; encoding: [0x1d,0x28]
+0x1d,0x28
+#CHECK: ldw $r1, [$r4,  1] ; encoding: [0x61,0x28]
+0x61,0x28
+#CHECK: ldw $r7, [$r7,  2] ; encoding: [0xfa,0x29]
+0xfa,0x29
+#CHECK: ldw $r7, [$r6,  3] ; encoding: [0xf3,0x29]
+0xf3,0x29
+
+#CHECK: ldb $r2, [$r3+,  1] ; encoding: [0x99,0x22]
+0x99,0x22
+#CHECK: ldb $r0, [-$r7,  2] ; encoding: [0x3a,0x24]
+0x3a,0x24
+#CHECK: ldw $r3, [$r0+, -4] ; encoding: [0xc4,0x2a]
+0xc4,0x2a
+#CHECK: ldw $r6, [-$r2,  1] ; encoding: [0x91,0x2d]
+0x91,0x2d
+
+# long encodings
+#CHECK: ldb $r0,  [$r0,     0] ; encoding: [0x00,0xa0,0x00,0x00]
+0x00,0xa0,0x00,0x00
+#CHECK: ldb $r54, [$r3,   111] ; encoding: [0x9f,0xa1,0x85,0x03]
+0x9f,0xa1,0x85,0x03
+#CHECK: ldb $r63, [$r11, -512] ; encoding: [0xd8,0xa1,0xc8,0x11]
+0xd8,0xa1,0xc8,0x11
+
+#CHECK: ldw $r32, [$r7,   -12] ; encoding: [0x3c,0xa8,0x06,0x1f]
+0x3c,0xa8,0x06,0x1f
+#CHECK: ldw $r23, [$r60, -106] ; encoding: [0xe6,0xa9,0xba,0x1c]
+0xe6,0xa9,0xba,0x1c
+#CHECK: ldw $r2,  [$r5,   511] ; encoding: [0xaf,0xa8,0x07,0x0e]
+0xaf,0xa8,0x07,0x0e
+
+#CHECK: ldb $r0,  [$r1+,     4] ; encoding: [0x0c,0xa2,0x00,0x00]
+0x0c,0xa2,0x00,0x00
+#CHECK: ldb $r18, [-$r9,   106] ; encoding: [0x8a,0xa4,0x8d,0x02]
+0x8a,0xa4,0x8d,0x02
+#CHECK: ldw $r3,  [$r50+,  -28] ; encoding: [0xd4,0xaa,0x34,0x1e]
+0xd4,0xaa,0x34,0x1e
+#CHECK: ldw $r6,  [-$r12, -512] ; encoding: [0xa0,0xad,0x08,0x10]
+0xa0,0xad,0x08,0x10
Index: test/MC/Disassembler/AAP/move.txt
===================================================================
--- /dev/null
+++ test/MC/Disassembler/AAP/move.txt
@@ -0,0 +1,35 @@
+#RUN: llvm-mc -triple=aap -disassemble -show-encoding < %s | FileCheck %s
+
+# short encodings
+#CHECK: mov $r0, $r5 ; encoding: [0x28,0x12]
+0x28,0x12
+#CHECK: mov $r3, $r7 ; encoding: [0xf8,0x12]
+0xf8,0x12
+#CHECK: mov $r7, $r7 ; encoding: [0xf8,0x13]
+0xf8,0x13
+
+#CHECK: movi $r0,  0 ; encoding: [0x00,0x1e]
+0x00,0x1e
+#CHECK: movi $r7,  7 ; encoding: [0xc7,0x1f]
+0xc7,0x1f
+#CHECK: movi $r2, 63 ; encoding: [0xbf,0x1e]
+0xbf,0x1e
+
+# long encodings
+#CHECK: mov $r0,  $r3  ; encoding: [0x18,0x92,0x00,0x00]
+0x18,0x92,0x00,0x00
+#CHECK: mov $r27, $r9  ; encoding: [0xc8,0x92,0xc8,0x00]
+0xc8,0x92,0xc8,0x00
+#CHECK: mov $r11, $r37 ; encoding: [0xe8,0x92,0x60,0x00]
+0xe8,0x92,0x60,0x00
+
+#CHECK: movi $r1,      0 ; encoding: [0x40,0x9e,0x00,0x00]
+0x40,0x9e,0x00,0x00
+#CHECK: movi $r33,    53 ; encoding: [0x75,0x9e,0x00,0x01]
+0x75,0x9e,0x00,0x01
+#CHECK: movi $r57,   580 ; encoding: [0x44,0x9e,0xc9,0x01]
+0x44,0x9e,0xc9,0x01
+#CHECK: movi $r2,   2716 ; encoding: [0x9c,0x9e,0x2a,0x00]
+0x9c,0x9e,0x2a,0x00
+#CHECK: movi $r17, 65535 ; encoding: [0x7f,0x9e,0xbf,0x1e]
+0x7f,0x9e,0xbf,0x1e
Index: test/MC/Disassembler/AAP/noop.txt
===================================================================
--- /dev/null
+++ test/MC/Disassembler/AAP/noop.txt
@@ -0,0 +1,18 @@
+#RUN: llvm-mc -triple=aap -disassemble -show-encoding < %s | FileCheck %s
+
+# Short encodings
+#CHECK: nop $r0, 0 ; encoding: [0x00,0x00]
+0x00 0x00
+#CHECK: nop $r0, 63 ; encoding: [0x3f,0x00]
+0x3f 0x00
+#CHECK: nop $r7, 17 ; encoding: [0xd1,0x01]
+0xd1 0x01
+
+# Long encodings
+#CHECK: nop $r0, 0 ; encoding: [0x00,0x80,0x00,0x00]
+0x00,0x80,0x00,0x00
+#CHECK: nop $r33, 874 ; encoding: [0x6a,0x80,0x0d,0x01]
+0x6a,0x80,0x0d,0x01
+#CHECK: nop $r9, 15 ; encoding: [0x4f,0x80,0x40,0x00]
+0x4f,0x80,0x40,0x00
+
Index: test/MC/Disassembler/AAP/store.txt
===================================================================
--- /dev/null
+++ test/MC/Disassembler/AAP/store.txt
@@ -0,0 +1,55 @@
+#RUN: llvm-mc -triple=aap -disassemble -show-encoding < %s | FileCheck %s
+
+# short encodings
+#CHECK: stb [$r0,  0], $r5 ; encoding: [0x28,0x30]
+0x28,0x30
+#CHECK: stb [$r5, -1], $r0 ; encoding: [0x47,0x31]
+0x47,0x31
+#CHECK: stb [$r5, -2], $r7 ; encoding: [0x7e,0x31]
+0x7e,0x31
+#CHECK: stb [$r5, -2], $r2 ; encoding: [0x56,0x31]
+0x56,0x31
+#CHECK: stb [$r7,  1], $r2 ; encoding: [0xd1,0x31]
+0xd1,0x31
+
+#CHECK: stw [$r2, -3], $r4 ; encoding: [0xa5,0x38]
+0xa5,0x38
+#CHECK: stw [$r2,  3], $r4 ; encoding: [0xa3,0x38]
+0xa3,0x38
+#CHECK: stw [$r3, -3], $r7 ; encoding: [0xfd,0x38]
+0xfd,0x38
+#CHECK: stw [$r7,  3], $r0 ; encoding: [0xc3,0x39]
+0xc3,0x39
+
+#CHECK: stb [$r5+,  1], $r1 ; encoding: [0x49,0x33]
+0x49,0x33
+#CHECK: stb [-$r0,  1], $r3 ; encoding: [0x19,0x34]
+0x19,0x34
+#CHECK: stw [$r2+, -2], $r5 ; encoding: [0xae,0x3a]
+0xae,0x3a
+#CHECK: stw [-$r3,  3], $r7 ; encoding: [0xfb,0x3c]
+0xfb,0x3c
+
+# long encodings
+#CHECK: stb [$r0,     3], $r2  ; encoding: [0x13,0xb0,0x00,0x00]
+0x13,0xb0,0x00,0x00
+#CHECK: stb [$r17,  511], $r7  ; encoding: [0x7f,0xb0,0x87,0x0e]
+0x7f,0xb0,0x87,0x0e
+#CHECK: stb [$r5,  -261], $r54 ; encoding: [0x73,0xb1,0x37,0x16]
+0x73,0xb1,0x37,0x16
+
+#CHECK: stw [$r38,  -90], $r11 ; encoding: [0x9e,0xb9,0x0c,0x1d]
+0x9e,0xb9,0x0c,0x1d
+#CHECK: stw [$r22, -333], $r15 ; encoding: [0xbb,0xb9,0x8e,0x14]
+0xbb,0xb9,0x8e,0x14
+#CHECK: stw [$r51,  171], $r3  ; encoding: [0xdb,0xb8,0x85,0x05]
+0xdb,0xb8,0x85,0x05
+
+#CHECK: stb [$r5+,     5], $r15 ; encoding: [0x7d,0xb3,0x08,0x00]
+0x7d,0xb3,0x08,0x00
+#CHECK: stb [-$r11,  271], $r32 ; encoding: [0xc7,0xb4,0x61,0x08]
+0xc7,0xb4,0x61,0x08
+#CHECK: stw [$r27+,  -99], $r32 ; encoding: [0xc5,0xba,0xe3,0x1c]
+0xc5,0xba,0xe3,0x1c
+#CHECK: stw [-$r32, -171], $r63 ; encoding: [0x3d,0xbc,0x3a,0x1b]
+0x3d,0xbc,0x3a,0x1b