Index: test/CodeGen/MIR/AArch64/inst-size-patchpoint.mir =================================================================== --- test/CodeGen/MIR/AArch64/inst-size-patchpoint.mir +++ /dev/null @@ -1,95 +0,0 @@ -# RUN: llc -mtriple=aarch64-unknown -run-pass aarch64-branch-relax -aarch64-tbz-offset-bits=4 %s -o - | FileCheck %s ---- | - ; ModuleID = '/tmp/test.ll' - source_filename = "test.ll" - target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" - target triple = "aarch64-unknown" - - define void @test_patchpoint_length(i32 %in) { - %val = and i32 %in, 1 - %tst = icmp eq i32 %val, 0 - br i1 %tst, label %true, label %false - - true: ; preds = %0 - tail call void (i64, i32, i8*, i32, ...) @llvm.experimental.patchpoint.void(i64 0, i32 32, i8* null, i32 0) - ret void - - false: ; preds = %0 - ret void - } - - declare void @llvm.experimental.patchpoint.void(i64, i32, i8*, i32, ...) -... ---- -# CHECK-LABEL: name:{{.*}}test_patchpoint_length -# If the size of the patchpoint is computed correctly, that will push -# the bb.2.false block too far away from the TBNZW, so the branch will -# have to be relaxed (note that we're using -aarch64-tbz-offset-bits to -# constrain the range that can be reached with the TBNZW to something smaller -# than what the patchpoint is lowered to). -# CHECK: TBZW killed %w0, 0, %bb.1.true -# CHECK: B %bb.2.false -name: test_patchpoint_length -alignment: 2 -exposesReturnsTwice: false -legalized: false -regBankSelected: false -selected: false -tracksRegLiveness: false -liveins: - - { reg: '%w0' } -calleeSavedRegisters: [ '%fp', '%lr', '%b8', '%b9', '%b10', '%b11', '%b12', - '%b13', '%b14', '%b15', '%d8', '%d9', '%d10', '%d11', - '%d12', '%d13', '%d14', '%d15', '%h8', '%h9', '%h10', - '%h11', '%h12', '%h13', '%h14', '%h15', '%s8', - '%s9', '%s10', '%s11', '%s12', '%s13', '%s14', - '%s15', '%w19', '%w20', '%w21', '%w22', '%w23', - '%w24', '%w25', '%w26', '%w27', '%w28', '%w29', - '%w30', '%x19', '%x20', '%x21', '%x22', '%x23', - '%x24', '%x25', '%x26', '%x27', '%x28', '%d8_d9', - '%d9_d10', '%d10_d11', '%d11_d12', '%d12_d13', - '%d13_d14', '%d14_d15', '%d8_d9_d10_d11', '%d9_d10_d11_d12', - '%d10_d11_d12_d13', '%d11_d12_d13_d14', '%d12_d13_d14_d15', - '%d8_d9_d10', '%d9_d10_d11', '%d10_d11_d12', '%d11_d12_d13', - '%d12_d13_d14', '%d13_d14_d15', '%w19_w20', '%w20_w21', - '%w21_w22', '%w22_w23', '%w23_w24', '%w24_w25', - '%w25_w26', '%w26_w27', '%w27_w28', '%w28_w29', - '%w29_w30', '%fp_lr', '%x28_fp', '%x19_x20', '%x20_x21', - '%x21_x22', '%x22_x23', '%x23_x24', '%x24_x25', - '%x25_x26', '%x26_x27', '%x27_x28' ] -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: false - hasPatchPoint: true - stackSize: 16 - offsetAdjustment: 0 - maxAlignment: 8 - adjustsStack: true - hasCalls: true - maxCallFrameSize: 0 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false -stack: - - { id: 0, type: spill-slot, offset: -8, size: 8, alignment: 8, callee-saved-register: '%lr' } - - { id: 1, type: spill-slot, offset: -16, size: 8, alignment: 8, callee-saved-register: '%fp' } -body: | - bb.0 (%ir-block.0): - successors: %bb.1.true, %bb.2.false - liveins: %w0, %lr, %fp - - TBNZW killed %w0, 0, %bb.2.false - - bb.1.true: - successors: %bb.2.false - liveins: %lr, %fp - - PATCHPOINT 0, 32, 0, 0, 0, csr_aarch64_aapcs, implicit-def dead early-clobber %x16, implicit-def dead early-clobber %x17, implicit-def dead early-clobber %lr, implicit-def %sp - - bb.2.false: - liveins: %lr, %fp - - RET killed %lr - -... Index: test/CodeGen/MIR/AArch64/inst-size-stackmap.mir =================================================================== --- test/CodeGen/MIR/AArch64/inst-size-stackmap.mir +++ /dev/null @@ -1,75 +0,0 @@ -# RUN: llc -mtriple=aarch64-unknown -run-pass aarch64-branch-relax -aarch64-tbz-offset-bits=4 %s -o - | FileCheck %s ---- | - ; ModuleID = 'test.ll' - source_filename = "test.ll" - target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" - target triple = "aarch64-unknown" - - define void @test_stackmap_length(i32 %in) { - %val = and i32 %in, 1 - %tst = icmp eq i32 %val, 0 - br i1 %tst, label %true, label %false - - true: ; preds = %0 - tail call void (i64, i32, ...) @llvm.experimental.stackmap(i64 0, i32 32) - ret void - - false: ; preds = %0 - ret void - } - - declare void @llvm.experimental.stackmap(i64, i32, ...) -... ---- -# CHECK-LABEL: name:{{.*}}test_stackmap_length -# If the size of the stackmap is computed correctly, that will push -# the bb.2.false block too far away from the TBNZW, so the branch will -# have to be relaxed (note that we're using -aarch64-tbz-offset-bits to -# constrain the range that can be reached with the TBNZW to something smaller -# than what the stackmap is lowered to). -# CHECK: TBZW killed %w0, 0, %bb.1.true -# CHECK: B %bb.2.false -name: test_stackmap_length -alignment: 2 -exposesReturnsTwice: false -legalized: false -regBankSelected: false -selected: false -tracksRegLiveness: false -liveins: - - { reg: '%w0' } -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: true - hasPatchPoint: false - stackSize: 16 - offsetAdjustment: 0 - maxAlignment: 8 - adjustsStack: true - hasCalls: true - maxCallFrameSize: 0 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false -stack: - - { id: 0, type: spill-slot, offset: -8, size: 8, alignment: 8, callee-saved-register: '%lr' } - - { id: 1, type: spill-slot, offset: -16, size: 8, alignment: 8, callee-saved-register: '%fp' } -body: | - bb.0 (%ir-block.0): - successors: %bb.1.true, %bb.2.false - liveins: %w0, %lr, %fp - - TBNZW killed %w0, 0, %bb.2.false - - bb.1.true: - successors: %bb.2.false - liveins: %lr, %fp - - STACKMAP 0, 32, implicit-def dead early-clobber %x16, implicit-def dead early-clobber %x17, implicit-def dead early-clobber %lr - - bb.2.false: - liveins: %lr, %fp - - RET killed %lr - Index: test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir =================================================================== --- test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir +++ /dev/null @@ -1,80 +0,0 @@ -# RUN: llc -mtriple=aarch64-unknown -run-pass aarch64-branch-relax -aarch64-tbz-offset-bits=4 %s -o - | FileCheck %s ---- | - ; ModuleID = 'test.ll' - source_filename = "test.ll" - target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" - target triple = "aarch64-unknown" - - @ThreadLocalGlobal = external thread_local local_unnamed_addr global i32, align 8 - - define i32 @test_tlsdesc_callseq_length(i32 %in) { - %val = and i32 %in, 1 - %tst = icmp eq i32 %val, 0 - br i1 %tst, label %true, label %false - - true: ; preds = %0 - %1 = load i32, i32* @ThreadLocalGlobal, align 8 - ret i32 %1 - - false: ; preds = %0 - ret i32 0 - } - -... ---- -# CHECK-LABEL: name:{{.*}}test_tlsdesc_callseq_length -# If the size of TLSDESC_CALLSEQ is computed correctly, that will push -# the bb.2.false block too far away from the TBNZW, so the branch will -# have to be relaxed (note that we're using -aarch64-tbz-offset-bits to -# constrain the range that can be reached with the TBNZW to something smaller -# than what TLSDESC_CALLSEQ is lowered to). -# CHECK: TBZW killed %w0, 0, %bb.1.true -# CHECK: B %bb.2.false -name: test_tlsdesc_callseq_length -alignment: 2 -exposesReturnsTwice: false -tracksRegLiveness: false -liveins: - - { reg: '%w0' } -frameInfo: - isFrameAddressTaken: false - isReturnAddressTaken: false - hasStackMap: false - hasPatchPoint: false - stackSize: 16 - offsetAdjustment: 0 - maxAlignment: 16 - adjustsStack: false - hasCalls: true - maxCallFrameSize: 0 - hasOpaqueSPAdjustment: false - hasVAStart: false - hasMustTailInVarArgFunc: false -stack: - - { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '%lr' } -body: | - bb.0 (%ir-block.0): - successors: %bb.1.true, %bb.2.false - liveins: %w0, %lr - - TBNZW killed %w0, 0, %bb.2.false - - bb.1.true: - liveins: %lr - - early-clobber %sp = frame-setup STRXpre killed %lr, %sp, -16 :: (store 8 into %stack.0) - frame-setup CFI_INSTRUCTION def_cfa_offset 16 - frame-setup CFI_INSTRUCTION offset %w30, -16 - TLSDESC_CALLSEQ target-flags(aarch64-tls) @ThreadLocalGlobal, implicit-def dead %lr, implicit-def %x0, implicit-def dead %x1 - %x8 = MRS 56962 - %w0 = LDRWroX killed %x8, killed %x0, 0, 0 :: (load 4 from @ThreadLocalGlobal, align 8) - early-clobber %sp, %lr = LDRXpost %sp, 16 :: (load 8 from %stack.0) - RET killed %lr, implicit killed %w0 - - bb.2.false: - liveins: %lr - - %w0 = ORRWrs %wzr, %wzr, 0 - RET killed %lr, implicit killed %w0 - -... Index: unittests/CMakeLists.txt =================================================================== --- unittests/CMakeLists.txt +++ unittests/CMakeLists.txt @@ -25,4 +25,5 @@ add_subdirectory(Option) add_subdirectory(ProfileData) add_subdirectory(Support) +add_subdirectory(Target) add_subdirectory(Transforms) Index: unittests/Target/AArch64/CMakeLists.txt =================================================================== --- /dev/null +++ unittests/Target/AArch64/CMakeLists.txt @@ -0,0 +1,23 @@ +include_directories( + ${CMAKE_SOURCE_DIR}/lib/Target/AArch64 + ${CMAKE_BINARY_DIR}/lib/Target/AArch64 + ) + +# FIXME: We're really requiring way too many components here, and a lot of it is +# because of the TargetOptions +set(LLVM_LINK_COMPONENTS + AArch64CodeGen + AArch64Desc + AArch64Info + CodeGen + Core + MC + MIRParser + SelectionDAG + Support + Target + ) + +add_llvm_unittest(AArch64Tests + InstSizes.cpp + ) Index: unittests/Target/AArch64/InstSizes.cpp =================================================================== --- /dev/null +++ unittests/Target/AArch64/InstSizes.cpp @@ -0,0 +1,122 @@ +#include "AArch64Subtarget.h" +#include "AArch64TargetMachine.h" +#include "llvm/CodeGen/MIRParser/MIRParser.h" +#include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Support/TargetSelect.h" + +#include "gtest/gtest.h" + +using namespace llvm; + +namespace { +std::unique_ptr createTargetMachine() { + auto TT(Triple::normalize("aarch64--")); + std::string CPU("generic"); + std::string FS(""); + + LLVMInitializeAArch64TargetInfo(); + LLVMInitializeAArch64Target(); + LLVMInitializeAArch64TargetMC(); + + std::string Error; + const Target *TheTarget = TargetRegistry::lookupTarget(TT, Error); + assert(TheTarget && "Target not registered"); + + return std::unique_ptr( + TheTarget->createTargetMachine(TT, CPU, FS, TargetOptions(), None, + CodeModel::Default, CodeGenOpt::Default)); +} + +std::unique_ptr createInstrInfo(TargetMachine *TM) { + AArch64Subtarget ST(TM->getTargetTriple(), TM->getTargetCPU(), + TM->getTargetFeatureString(), *TM, /* isLittle */ false); + return llvm::make_unique(ST); +} + +/// The \p InputIRSnippet is only needed for things that can't be expressed in +/// the \p InputMIRSnippet (global variables etc) +/// TODO: Some of this might be useful for other architectures as well - extract +/// the platform-independent parts somewhere they can be reused. +void runChecks( + TargetMachine *TM, AArch64InstrInfo *II, const StringRef InputIRSnippet, + const StringRef InputMIRSnippet, + std::function Checks) { + LLVMContext Context; + + auto MIRString = + "--- |\n" + " declare void @sizes()\n" + + InputIRSnippet.str() + + "...\n" + "---\n" + "name: sizes\n" + "body: |\n" + " bb.0:\n" + + InputMIRSnippet.str(); + + std::unique_ptr MBuffer = MemoryBuffer::getMemBuffer(MIRString); + std::unique_ptr MParser = + createMIRParser(std::move(MBuffer), Context); + assert(MParser && "Couldn't create MIR parser"); + + std::unique_ptr M = MParser->parseLLVMModule(); + assert(M && "Couldn't parse module"); + + M->setTargetTriple(TM->getTargetTriple().getTriple()); + M->setDataLayout(TM->createDataLayout()); + + auto F = M->getFunction("sizes"); + assert(F && "Couldn't find intended function"); + + MachineModuleInfo MMI(TM); + MMI.setMachineFunctionInitializer(MParser.get()); + auto &MF = MMI.getMachineFunction(*F); + + Checks(*II, MF); +} + +} // anonymous namespace + +TEST(InstSizes, STACKMAP) { + std::unique_ptr TM = createTargetMachine(); + std::unique_ptr II = createInstrInfo(TM.get()); + + runChecks(TM.get(), II.get(), "", " STACKMAP 0, 16\n" + " STACKMAP 1, 32\n", + [](AArch64InstrInfo &II, MachineFunction &MF) { + auto I = MF.begin()->begin(); + EXPECT_EQ(16u, II.getInstSizeInBytes(*I)); + ++I; + EXPECT_EQ(32u, II.getInstSizeInBytes(*I)); + }); +} + +TEST(InstSizes, PATCHPOINT) { + std::unique_ptr TM = createTargetMachine(); + std::unique_ptr II = createInstrInfo(TM.get()); + + runChecks(TM.get(), II.get(), "", + " PATCHPOINT 0, 16, 0, 0, 0, csr_aarch64_aapcs\n" + " PATCHPOINT 1, 32, 0, 0, 0, csr_aarch64_aapcs\n", + [](AArch64InstrInfo &II, MachineFunction &MF) { + auto I = MF.begin()->begin(); + EXPECT_EQ(16u, II.getInstSizeInBytes(*I)); + ++I; + EXPECT_EQ(32u, II.getInstSizeInBytes(*I)); + }); +} + +TEST(InstSizes, TLSDESC_CALLSEQ) { + std::unique_ptr TM = createTargetMachine(); + std::unique_ptr II = createInstrInfo(TM.get()); + + runChecks( + TM.get(), II.get(), + " @ThreadLocalGlobal = external thread_local global i32, align 8\n", + " TLSDESC_CALLSEQ target-flags(aarch64-tls) @ThreadLocalGlobal\n", + [](AArch64InstrInfo &II, MachineFunction &MF) { + auto I = MF.begin()->begin(); + EXPECT_EQ(16u, II.getInstSizeInBytes(*I)); + }); +} Index: unittests/Target/CMakeLists.txt =================================================================== --- /dev/null +++ unittests/Target/CMakeLists.txt @@ -0,0 +1,5 @@ +foreach(t ${LLVM_TARGETS_TO_BUILD}) + if(IS_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/${t}) + add_subdirectory(${t}) + endif() +endforeach()