Index: include/llvm/Support/ARMTargetParser.def
===================================================================
--- include/llvm/Support/ARMTargetParser.def
+++ include/llvm/Support/ARMTargetParser.def
@@ -224,6 +224,8 @@
               ARM::AEK_HWDIVTHUMB))
 ARM_CPU_NAME("krait", ARMV7A, FK_NEON_VFPV4, false,
              (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB))
+ARM_CPU_NAME("marvell-pj4", ARMV7A, FK_VFPV3, false,
+             (ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB))
 ARM_CPU_NAME("cortex-r4", ARMV7R, FK_NONE, true, ARM::AEK_NONE)
 ARM_CPU_NAME("cortex-r4f", ARMV7R, FK_VFPV3_D16, false, ARM::AEK_NONE)
 ARM_CPU_NAME("cortex-r5", ARMV7R, FK_VFPV3_D16, false,
Index: lib/Support/Host.cpp
===================================================================
--- lib/Support/Host.cpp
+++ lib/Support/Host.cpp
@@ -247,6 +247,25 @@
     }
   }
 
+  if (Implementer == "0x56") { // Marvell Technology Group Ltd.
+    // Look for the CPU architecture line.
+    for (unsigned I = 0, E = Lines.size(); I != E; ++I)
+      if (Lines[I].startswith("CPU architecture"))
+        // Architecture must be ARMv7.
+        if (Lines[I].substr(16).ltrim("\t :") != "7")
+          return "generic";
+    // Look for the CPU part line.
+    for (unsigned I = 0, E = Lines.size(); I != E; ++I)
+      if (Lines[I].startswith("CPU part"))
+        // The CPU part is a 3 digit hexadecimal number with a 0x prefix. The
+        // values correspond to the "Part number" in the CP15/c0 register. The
+        // contents are specified in the various processor manuals.
+        return StringSwitch<const char *>(Lines[I].substr(8).ltrim("\t :"))
+            .Case("0x581", "marvell-pj4") // Sheeva PJ4 / PJ4B
+            .Case("0x584", "marvell-pj4") // Sheeva PJ4B-MP / PJ4C
+            .Default("generic");
+  }
+
   return "generic";
 }
 
Index: unittests/Support/Host.cpp
===================================================================
--- unittests/Support/Host.cpp
+++ unittests/Support/Host.cpp
@@ -92,6 +92,18 @@
   EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x51\n"
                                               "CPU part        : 0x06f"),
             "krait");
+  EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x56\n"
+                                              "CPU architecture: 7\n"
+                                              "CPU part        : 0x581"),
+            "marvell-pj4");
+  EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x56\n"
+                                              "CPU architecture: 7\n"
+                                              "CPU part        : 0x584"),
+            "marvell-pj4");
+  EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x56\n"
+                                              "CPU architecture: 6\n"
+                                              "CPU part        : 0x584"),
+            "generic");
 }
 
 TEST(getLinuxHostCPUName, AArch64) {
Index: unittests/Support/TargetParserTest.cpp
===================================================================
--- unittests/Support/TargetParserTest.cpp
+++ unittests/Support/TargetParserTest.cpp
@@ -175,6 +175,9 @@
   EXPECT_TRUE(testARMCPU("krait", "armv7-a", "neon-vfpv4",
                          ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
                          "7-A"));
+  EXPECT_TRUE(testARMCPU("marvell-pj4", "armv7-a", "vfpv3",
+                         ARM::AEK_HWDIVARM | ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP,
+                         "7-A"));
   EXPECT_TRUE(testARMCPU("cortex-r4", "armv7-r", "none",
                          ARM::AEK_HWDIVTHUMB | ARM::AEK_DSP, "7-R"));
   EXPECT_TRUE(testARMCPU("cortex-r4f", "armv7-r", "vfpv3-d16",
@@ -279,7 +282,7 @@
                          "7-S"));
 }
 
-static constexpr unsigned NumARMCPUArchs = 82;
+static constexpr unsigned NumARMCPUArchs = 83;
 
 TEST(TargetParserTest, testARMCPUArchList) {
   SmallVector<StringRef, NumARMCPUArchs> List;