Index: lib/Target/PowerPC/PPCFrameLowering.cpp =================================================================== --- lib/Target/PowerPC/PPCFrameLowering.cpp +++ lib/Target/PowerPC/PPCFrameLowering.cpp @@ -1190,6 +1190,7 @@ // Do we have a frame pointer and/or base pointer for this function? bool HasFP = hasFP(MF); bool HasBP = RegInfo->hasBasePointer(MF); + bool HasRedZone = Subtarget.isPPC64() || !Subtarget.isSVR4ABI(); unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1; unsigned BPReg = RegInfo->getBaseRegister(MF); @@ -1223,7 +1224,6 @@ if (HasFP) { if (isSVR4ABI) { - MachineFrameInfo &MFI = MF.getFrameInfo(); int FPIndex = FI->getFramePointerSaveIndex(); assert(FPIndex && "No Frame Pointer Save Slot!"); FPOffset = MFI.getObjectOffset(FPIndex); @@ -1235,7 +1235,6 @@ int BPOffset = 0; if (HasBP) { if (isSVR4ABI) { - MachineFrameInfo &MFI = MF.getFrameInfo(); int BPIndex = FI->getBasePointerSaveIndex(); assert(BPIndex && "No Base Pointer Save Slot!"); BPOffset = MFI.getObjectOffset(BPIndex); @@ -1246,7 +1245,6 @@ int PBPOffset = 0; if (FI->usesPICBase()) { - MachineFrameInfo &MFI = MF.getFrameInfo(); int PBPIndex = FI->getPICBasePointerSaveIndex(); assert(PBPIndex && "No PIC Base Pointer Save Slot!"); PBPOffset = MFI.getObjectOffset(PBPIndex); @@ -1282,9 +1280,25 @@ // indexed into with a simple LD/LWZ immediate offset operand. bool isLargeFrame = !isInt<16>(FrameSize); + // On targets without red zone, the SP needs to be restored last, so that + // all live contents of the stack frame are upwards of the SP. This means + // that we cannot restore SP just now, since there may be more registers + // to restore from the stack frame (e.g. R31). If the frame size is not + // a simple immediate value, we will need a spare register to hold the + // restored SP. If the frame size is known and small, we can simply adjust + // the offsets of the registers to be restored, and still use SP to restore + // them. In such case, the final update of SP will be to add the frame + // size to it. + // To simplify the code, set RBReg to the base register used to restore + // values from the stack, and set SPAdd to the value that needs to be added + // to the SP at the end. The default values are as if red zone was present. + unsigned RBReg = SPReg; + unsigned SPAdd = 0; + if (FrameSize) { - // In the prologue, the loaded (or persistent) stack pointer value is offset - // by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now. + // In the prologue, the loaded (or persistent) stack pointer value is + // offset by the STDU/STDUX/STWU/STWUX instruction. For targets with red + // zone add this offset back now. // If this function contained a fastcc call and GuaranteedTailCallOpt is // enabled (=> hasFastCall()==true) the fastcc call might contain a tail @@ -1292,8 +1306,10 @@ // value of R31 in this case. if (FI->hasFastCall()) { assert(HasFP && "Expecting a valid frame pointer."); + if (!HasRedZone) + RBReg = FPReg; if (!isLargeFrame) { - BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) + BuildMI(MBB, MBBI, dl, AddImmInst, RBReg) .addReg(FPReg).addImm(FrameSize); } else { BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg) @@ -1302,27 +1318,55 @@ .addReg(ScratchReg, RegState::Kill) .addImm(FrameSize & 0xFFFF); BuildMI(MBB, MBBI, dl, AddInst) - .addReg(SPReg) + .addReg(RBReg) .addReg(FPReg) .addReg(ScratchReg); } } else if (!isLargeFrame && !HasBP && !MFI.hasVarSizedObjects()) { - BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) - .addReg(SPReg) - .addImm(FrameSize); + if (HasRedZone) { + BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) + .addReg(SPReg) + .addImm(FrameSize); + } else { + // Make sure that adding FrameSize will not overflow the max offset + // size. + assert(FPOffset <= 0 && BPOffset <= 0 && PBPOffset <= 0 && + "Local offsets should be negative"); + SPAdd = FrameSize; + FPOffset += FrameSize; + BPOffset += FrameSize; + PBPOffset += FrameSize; + } } else { - BuildMI(MBB, MBBI, dl, LoadInst, SPReg) + // We don't want to use ScratchReg as a base register, because it + // could happen to be R0. Use FP instead, but make sure to preserve it. + if (!HasRedZone) { + // If FP is not saved, copy it to ScratchReg. + if (!HasFP) + BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg) + .addReg(FPReg) + .addImm(0); + RBReg = FPReg; + } + BuildMI(MBB, MBBI, dl, LoadInst, RBReg) .addImm(0) .addReg(SPReg); } } + assert(RBReg != ScratchReg && "Should have avoided ScratchReg"); + // If there is no red zone, ScratchReg may be needed for holding a useful + // value (although not the base register). Make sure it is not overwritten + // too early. assert((isPPC64 || !MustSaveCR) && "Epilogue CR restoring supported only in 64-bit mode"); - // If we need to save both the LR and the CR and we only have one available - // scratch register, we must do them one at a time. + // If we need to restore both the LR and the CR and we only have one + // available scratch register, we must do them one at a time. if (MustSaveCR && SingleScratchReg && MustSaveLR) { + // Here TempReg == ScratchReg, and in the absence of red zone ScratchReg + // is live here. + assert(HasRedZone && "Expecting red zone"); BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg) .addImm(8) .addReg(SPReg); @@ -1331,33 +1375,71 @@ .addReg(TempReg, getKillRegState(i == e-1)); } - if (MustSaveLR) + // Delay restoring of the LR if ScratchReg is needed. This is ok, since + // LR is stored in the caller's stack frame. ScratchReg will be needed + // if RBReg is anything other than SP. We shouldn't use ScratchReg as + // a base register anyway, because it may happen to be R0. + bool LoadedLR = false; + if (MustSaveLR && RBReg == SPReg && isInt<16>(LROffset+SPAdd)) { BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg) - .addImm(LROffset) - .addReg(SPReg); + .addImm(LROffset+SPAdd) + .addReg(RBReg); + LoadedLR = true; + } - if (MustSaveCR && - !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64 + if (MustSaveCR && !(SingleScratchReg && MustSaveLR)) { + // This will only occur for PPC64. + assert(isPPC64 && "Expecting 64-bit mode"); + assert(RBReg == SPReg && "Should be using SP as a base register"); BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg) .addImm(8) - .addReg(SPReg); + .addReg(RBReg); + } - if (HasFP) - BuildMI(MBB, MBBI, dl, LoadInst, FPReg) - .addImm(FPOffset) - .addReg(SPReg); + if (HasFP) { + // If there is red zone, restore FP directly, since SP has already been + // restored. Otherwise, restore the value of FP into ScratchReg. + if (HasRedZone || RBReg == SPReg) + BuildMI(MBB, MBBI, dl, LoadInst, FPReg) + .addImm(FPOffset) + .addReg(SPReg); + else + BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg) + .addImm(FPOffset) + .addReg(RBReg); + } if (FI->usesPICBase()) - // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe. BuildMI(MBB, MBBI, dl, LoadInst) .addReg(PPC::R30) .addImm(PBPOffset) - .addReg(SPReg); + .addReg(RBReg); if (HasBP) BuildMI(MBB, MBBI, dl, LoadInst, BPReg) .addImm(BPOffset) - .addReg(SPReg); + .addReg(RBReg); + + // There is nothing more to be loaded from the stack, so now we can + // restore SP. + if (RBReg != SPReg || SPAdd != 0) { + assert(!HasRedZone && "This should not happen with red zone"); + BuildMI(MBB, MBBI, dl, AddImmInst, SPReg) + .addReg(RBReg) + .addImm(SPAdd); + + assert(RBReg != ScratchReg && "Should be using FP or SP as base register"); + if (RBReg == FPReg) + BuildMI(MBB, MBBI, dl, OrImmInst, FPReg) + .addReg(ScratchReg) + .addImm(0); + + // Now load the LR from the caller's stack frame. + if (MustSaveLR && !LoadedLR) + BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg) + .addImm(LROffset) + .addReg(SPReg); + } if (MustSaveCR && !(SingleScratchReg && MustSaveLR)) // will only occur for PPC64 Index: test/CodeGen/PowerPC/ppc32-pic-large.ll =================================================================== --- test/CodeGen/PowerPC/ppc32-pic-large.ll +++ test/CodeGen/PowerPC/ppc32-pic-large.ll @@ -25,7 +25,7 @@ ; LARGE-BSS-DAG: lwz [[VREG:[0-9]+]], [[VREF:\.LC[0-9]+]]-.LTOC(30) ; LARGE-BSS-DAG: lwz {{[0-9]+}}, 0([[VREG]]) ; LARGE-BSS-DAG: stw {{[0-9]+}}, 8(1) -; LARGE-BSS: lwz 30, -8(1) +; LARGE-BSS: lwz 30, 24(1) ; LARGE-BSS: [[VREF]]: ; LARGE-BSS-NEXT: .p2align 2 ; LARGE-BSS-NEXT: .long bar Index: test/CodeGen/PowerPC/ppc32-pic.ll =================================================================== --- test/CodeGen/PowerPC/ppc32-pic.ll +++ test/CodeGen/PowerPC/ppc32-pic.ll @@ -21,4 +21,4 @@ ; SMALL-BSS-DAG: lwz [[VREG:[0-9]+]], bar@GOT(30) ; SMALL-BSS-DAG: lwz {{[0-9]+}}, 0([[VREG]]) ; SMALL-BSS: bl call_foo@PLT -; SMALL-BSS: lwz 30, -8(1) +; SMALL-BSS: lwz 30, 24(1)