Index: lib/Target/ARM/ARMTargetMachine.cpp
===================================================================
--- lib/Target/ARM/ARMTargetMachine.cpp
+++ lib/Target/ARM/ARMTargetMachine.cpp
@@ -89,7 +89,9 @@
 
   // We have 128 and 64 bit vectors. The APCS ABI aligns them to 32 bits, others
   // to 64. We always ty to give them natural alignment.
-  if (ST.isAPCS_ABI())
+  if (ST.isTargetNaCl())
+    Ret += "-v128:32";
+  else if (ST.isAPCS_ABI())
     Ret += "-v64:32:64-v128:32:128";
   else
     Ret += "-v128:64:128";
@@ -99,14 +101,16 @@
   if (ST.isThumb() || ST.isAPCS_ABI())
     Ret += "-a:0:32";
 
-  // Integer registers are 32 bits.
-  Ret += "-n32";
+  if (!ST.isTargetNaCl()) {
+    // Integer registers are 32 bits.
+    Ret += "-n32";
 
-  // The stack is 64 bit aligned on AAPCS and 32 bit aligned everywhere else.
-  if (ST.isAAPCS_ABI())
-    Ret += "-S64";
-  else
-    Ret += "-S32";
+    // The stack is 64 bit aligned on AAPCS and 32 bit aligned everywhere else.
+    if (ST.isAAPCS_ABI())
+      Ret += "-S64";
+    else
+      Ret += "-S32";
+  }
 
   return Ret;
 }
Index: lib/Target/X86/X86Subtarget.h
===================================================================
--- lib/Target/X86/X86Subtarget.h
+++ lib/Target/X86/X86Subtarget.h
@@ -246,7 +246,8 @@
 
   /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
   bool isTarget64BitILP32() const {
-    return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32);
+    return In64BitMode && (TargetTriple.getEnvironment() == Triple::GNUX32 ||
+                           TargetTriple.getOS() == Triple::NaCl);
   }
 
   /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
Index: lib/Target/X86/X86TargetMachine.cpp
===================================================================
--- lib/Target/X86/X86TargetMachine.cpp
+++ lib/Target/X86/X86TargetMachine.cpp
@@ -39,32 +39,40 @@
     Ret += "-p:32:32";
 
   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
-  if (ST.is64Bit() || ST.isTargetCygMing() || ST.isTargetWindows())
+  if (ST.is64Bit() || ST.isTargetCygMing() || ST.isTargetWindows() ||
+      ST.isTargetNaCl())
     Ret += "-i64:64";
   else
     Ret += "-f64:32:64";
 
   // Some ABIs align long double to 128 bits, others to 32.
-  if (ST.is64Bit() || ST.isTargetDarwin())
+  if (ST.isTargetNaCl())
+    ; // No f80
+  else if (ST.is64Bit() || ST.isTargetDarwin())
     Ret += "-f80:128";
   else
     Ret += "-f80:32";
 
-  // Objects on the stack ore aligned to 64 bits.
-  if (ST.is64Bit())
-    Ret += "-s:64";
-
-  // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
-  if (ST.is64Bit())
-    Ret += "-n8:16:32:64";
-  else
-    Ret += "-n8:16:32";
-
-  // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
-  if (!ST.is64Bit() && (ST.isTargetCygMing() || ST.isTargetWindows()))
-    Ret += "-S32";
-  else
-    Ret += "-S128";
+  if (ST.isTargetNaCl())
+    Ret += "-v128:32";
+
+  if (!ST.isTargetNaCl()) {
+    // Objects on the stack ore aligned to 64 bits.
+    if (ST.is64Bit())
+      Ret += "-s:64";
+
+    // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
+    if (ST.is64Bit())
+      Ret += "-n8:16:32:64";
+    else
+      Ret += "-n8:16:32";
+
+    // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
+    if (!ST.is64Bit() && (ST.isTargetCygMing() || ST.isTargetWindows()))
+      Ret += "-S32";
+    else
+      Ret += "-S128";
+  }
 
   return Ret;
 }