Index: lib/CodeGen/MIRParser/MILexer.cpp
===================================================================
--- lib/CodeGen/MIRParser/MILexer.cpp
+++ lib/CodeGen/MIRParser/MILexer.cpp
@@ -436,6 +436,22 @@
   return C;
 }
 
+static Cursor maybeLexHexIntegerLiteral(Cursor C, MIToken &Token) {
+  if (C.peek() != '0' || C.peek(1) != 'x')
+    return None;
+
+  C.advance(2); // Skip '0x'
+
+  Cursor Range = C;
+  while (isxdigit(C.peek()))
+    C.advance();
+
+  StringRef StrVal = Range.upto(C);
+  Token.reset(MIToken::IntegerLiteral, StrVal)
+    .setIntegerValue(APSInt(APInt(64, StrVal, 16)));
+  return C;
+}
+
 static Cursor lexFloatingPointLiteral(Cursor Range, Cursor C, MIToken &Token) {
   C.advance();
   // Skip over [0-9]*([eE][-+]?[0-9]+)?
@@ -608,6 +624,8 @@
     return R.remaining();
   if (Cursor R = maybeLexExternalSymbol(C, Token, ErrorCallback))
     return R.remaining();
+  if (Cursor R = maybeLexHexIntegerLiteral(C, Token))
+    return R.remaining();
   if (Cursor R = maybeLexHexFloatingPointLiteral(C, Token))
     return R.remaining();
   if (Cursor R = maybeLexNumericalLiteral(C, Token))
Index: lib/CodeGen/MIRParser/MIParser.cpp
===================================================================
--- lib/CodeGen/MIRParser/MIParser.cpp
+++ lib/CodeGen/MIRParser/MIParser.cpp
@@ -441,8 +441,18 @@
     unsigned Reg = 0;
     if (parseRegister(Reg))
       return true;
-    MBB.addLiveIn(Reg);
     lex();
+
+    LaneBitmask LaneMask = ~0u;
+    if (consumeIfPresent(MIToken::colon)) {
+      if (Token.isNot(MIToken::IntegerLiteral))
+        return error("expected an integer literal for lane mask");
+      if (getUnsigned(LaneMask))
+        return true;
+      lex();
+    }
+
+    MBB.addLiveIn(Reg, LaneMask);
   } while (consumeIfPresent(MIToken::comma));
   return false;
 }
Index: lib/CodeGen/MIRPrinter.cpp
===================================================================
--- lib/CodeGen/MIRPrinter.cpp
+++ lib/CodeGen/MIRPrinter.cpp
@@ -497,7 +497,7 @@
       First = false;
       printReg(LI.PhysReg, OS, TRI);
       if (LI.LaneMask != ~0u)
-        OS << ':' << PrintLaneMask(LI.LaneMask);
+        OS << ":0x" << PrintLaneMask(LI.LaneMask);
     }
     OS << "\n";
     HasLineAttributes = true;
Index: test/CodeGen/MIR/AMDGPU/lane-mask-livein.mir
===================================================================
--- /dev/null
+++ test/CodeGen/MIR/AMDGPU/lane-mask-livein.mir
@@ -0,0 +1,59 @@
+# RUN: llc -verify-machineinstrs -march=amdgcn -run-pass none -o - %s | FIleCheck %s
+--- |
+  target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
+
+  define void @lane_mask_livein(i32 addrspace(1)* %out, i32 %cond) #0 {
+  entry:
+    br i1 undef, label %if, label %endif
+
+  if:
+    store i32 0, i32 addrspace(1)* undef
+    br label %endif
+
+  endif:
+    ret void
+  }
+
+  attributes #0 = { nounwind }
+
+...
+---
+# CHECK-LABEL: name: lane_mask_livein
+# CHECK: bb.0.entry:
+# CHECK: liveins: %vgpr0, %sgpr0_sgpr1
+
+# CHECK:  bb.1.if:
+# CHECK: liveins: %sgpr0_sgpr1, %sgpr2_sgpr3, %sgpr4_sgpr5_sgpr6_sgpr7:0x0000000F
+
+# CHECK: bb.2.endif:
+# CHECK: liveins: %sgpr4_sgpr5_sgpr6_sgpr7:0x00000001, %sgpr2_sgpr3
+
+name:            lane_mask_livein
+alignment:       0
+tracksRegLiveness: true
+liveins:
+  - { reg: '%sgpr0_sgpr1' }
+  - { reg: '%vgpr0' }
+body:             |
+  bb.0.entry:
+    successors: %bb.1.if, %bb.3.endif
+    liveins: %vgpr0, %sgpr0_sgpr1
+    S_CMP_LT_I32 killed %sgpr0, 1, implicit-def %scc
+    S_CBRANCH_SCC1 %bb.3.endif, implicit killed %scc
+
+  bb.1.if:
+    successors: %bb.3.endif
+    liveins: %sgpr0_sgpr1, %sgpr2_sgpr3, %sgpr4_sgpr5_sgpr6_sgpr7:0x0000000F
+    %sgpr4_sgpr5 = S_LOAD_DWORDX2_IMM %sgpr0_sgpr1, 36 :: (non-temporal invariant load 8 from `i64 addrspace(2)* undef`)
+    %sgpr0 = S_LOAD_DWORD_IMM killed %sgpr0_sgpr1, 44 :: (non-temporal invariant load 4 from `i32 addrspace(2)* undef`)
+    %sgpr7 = S_MOV_B32 61440
+    %sgpr6 = S_MOV_B32 -1
+    %vgpr0 = V_MOV_B32_e32 0, implicit %exec
+    BUFFER_STORE_DWORD_OFFSET killed %vgpr0, %sgpr4_sgpr5_sgpr6_sgpr7, 0, 0, 0, 0, 0, implicit %exec :: (store 4 into %ir.out)
+
+
+  bb.3.endif:
+    liveins: %sgpr4_sgpr5_sgpr6_sgpr7:0x00000001, %sgpr2_sgpr3
+    S_ENDPGM
+
+...