Index: lib/Transforms/Scalar/GVN.cpp
===================================================================
--- lib/Transforms/Scalar/GVN.cpp
+++ lib/Transforms/Scalar/GVN.cpp
@@ -1259,7 +1259,7 @@
 
     // Check to see if we have something like this:
     //    load i32* P
-    //    load i8* (P+1)
+    //    load i8* P
     // if we have this, replace the later with an extraction from the former.
     if (LoadInst *DepLI = dyn_cast<LoadInst>(DepInfo.getInst())) {
       // If this is a clobber and L is the first instruction in its block, then
@@ -1269,7 +1269,7 @@
         int Offset =
           AnalyzeLoadFromClobberingLoad(LI->getType(), Address, DepLI, DL);
 
-        if (Offset != -1) {
+        if (Offset == 0) {
           Res = AvailableValue::getLoad(DepLI, Offset);
           return true;
         }
Index: test/Instrumentation/AddressSanitizer/asan-vs-gvn.ll
===================================================================
--- test/Instrumentation/AddressSanitizer/asan-vs-gvn.ll
+++ test/Instrumentation/AddressSanitizer/asan-vs-gvn.ll
@@ -34,7 +34,7 @@
   ret void
 }
 
-;; Accessing bytes 4 and 5. Ok to widen to i16.
+;; Accessing bytes 4 and 5. No widen to i16.
 
 define i32 @test_widening_ok(i8* %P) nounwind ssp noredzone sanitize_address {
 entry:
@@ -45,7 +45,8 @@
   %add = add nsw i32 %conv, %conv2
   ret i32 %add
 ; CHECK: @test_widening_ok
-; CHECK: __asan_report_load2
+; CHECK: __asan_report_load1
+; CHECK: __asan_report_load1
 ; CHECK-NOT: __asan_report
 ; CHECK: end_test_widening_ok
 }
Index: test/Transforms/GVN/PRE/load-pre-nonlocal.ll
===================================================================
--- test/Transforms/GVN/PRE/load-pre-nonlocal.ll
+++ test/Transforms/GVN/PRE/load-pre-nonlocal.ll
@@ -51,15 +51,16 @@
 }
 
 ; %1 is partially redundant if %0 can be widened to a 64-bit load.
+; But we should not widen %0 to 64-bit load.
 
 ; CHECK-LABEL: define i32 @overaligned_load
 ; CHECK: if.then:
-; CHECK:   %0 = load i64
-; CHECK:   [[LSHR:%[0-9]+]] = lshr i64 %0, 32, !dbg [[LSHR_LOC:![0-9]+]]
-; CHECK:   trunc i64 [[LSHR]] to i32
+; CHECK-NOT:   %0 = load i64
+; CHECK-NOT:   [[LSHR:%[0-9]+]] = lshr i64 %0, 32, !dbg [[LSHR_LOC:![0-9]+]]
+; CHECK-NOT:   trunc i64 [[LSHR]] to i32
 ; CHECK: if.end:
-; CHECK-NOT: %1 = load i32, i32*
-; CHECK: [[LSHR_LOC]] = !DILocation(line: 101, column: 1, scope: !{{.*}})
+; CHECK: %1 = load i32, i32*
+; CHECK-NOT: [[LSHR_LOC]] = !DILocation(line: 101, column: 1, scope: !{{.*}})
 
 define i32 @overaligned_load(i32 %a, i32* nocapture %b) !dbg !13 {
 entry:
Index: test/Transforms/GVN/PRE/rle.ll
===================================================================
--- test/Transforms/GVN/PRE/rle.ll
+++ test/Transforms/GVN/PRE/rle.ll
@@ -640,7 +640,8 @@
   ret i32 %add
 ; CHECK-LABEL: @test_widening1(
 ; CHECK-NOT: load
-; CHECK: load i16, i16*
+; CHECK: load i8, i8*
+; CHECK: load i8, i8*
 ; CHECK-NOT: load
 ; CHECK: ret i32
 }
@@ -664,7 +665,10 @@
   ret i32 %add3
 ; CHECK-LABEL: @test_widening2(
 ; CHECK-NOT: load
-; CHECK: load i32, i32*
+; CHECK: load i8, i8*
+; CHECK: load i8, i8*
+; CHECK: load i8, i8*
+; CHECK: load i8, i8*
 ; CHECK-NOT: load
 ; CHECK: ret i32
 }
Index: test/Transforms/GVN/big-endian.ll
===================================================================
--- test/Transforms/GVN/big-endian.ll
+++ test/Transforms/GVN/big-endian.ll
@@ -7,9 +7,9 @@
 ;; loads reusing a load value.
 define i64 @test1({ i1, i8 }* %predA, { i1, i8 }* %predB) {
 ; CHECK-LABEL: @test1
-; CHECK: [[V1:%.*]] = load i16, i16* %{{.*}}
-; CHECK: [[V2:%.*]] = lshr i16 [[V1]], 8
-; CHECK: trunc i16 [[V2]] to i1
+; CHECK-NOT: [[V1:%.*]] = load i16, i16* %{{.*}}
+; CHECK-NOT: [[V2:%.*]] = lshr i16 [[V1]], 8
+; CHECK-NOT: trunc i16 [[V2]] to i1
 
   %valueLoadA.fca.0.gep = getelementptr inbounds { i1, i8 }, { i1, i8 }* %predA, i64 0, i32 0
   %valueLoadA.fca.0.load = load i1, i1* %valueLoadA.fca.0.gep, align 8
Index: test/Transforms/GVN/no_speculative_loads_with_asan.ll
===================================================================
--- test/Transforms/GVN/no_speculative_loads_with_asan.ll
+++ test/Transforms/GVN/no_speculative_loads_with_asan.ll
@@ -25,9 +25,8 @@
 }
 
 ; CHECK-LABEL: @TestNoAsan
-; CHECK: %[[LOAD:[^ ]+]] = load i32
-; CHECK: {{.*}} = ashr i32 %[[LOAD]]
-; CHECK-NOT: {{.*}} = phi
+; CHECK-NOT: %[[LOAD:[^ ]+]] = load i32
+; CHECK: {{.*}} = phi
 
 define i32 @TestAsan() sanitize_address {
   %1 = tail call noalias i8* @_Znam(i64 2)
Index: test/Transforms/GVN/pr25440.ll
===================================================================
--- test/Transforms/GVN/pr25440.ll
+++ test/Transforms/GVN/pr25440.ll
@@ -19,7 +19,7 @@
   %x.tr = phi %struct.a* [ %x, %entry ], [ null, %land.lhs.true ]
   %code1 = getelementptr inbounds %struct.a, %struct.a* %x.tr, i32 0, i32 0
   %0 = load i16, i16* %code1, align 4
-; CHECK: load i32, i32*
+; CHECK: load i16, i16*
   %conv = zext i16 %0 to i32
   switch i32 %conv, label %if.end.50 [
     i32 43, label %cleanup
@@ -38,7 +38,7 @@
 
 cond.false:                                       ; preds = %if.then.26
 ; CHECK: cond.false:
-; CHECK-NOT: load
+; CHECK: load i16
   %mode = getelementptr inbounds %struct.a, %struct.a* %x.tr.lcssa163, i32 0, i32 1
   %bf.load = load i16, i16* %mode, align 2
   %bf.shl = shl i16 %bf.load, 8