Index: lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
===================================================================
--- lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
+++ lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
@@ -263,7 +263,7 @@
 
   ++MCNumFixups;
 
-  return 0;
+  return ShiftVal == 0 ? 0 : (1 << ShiftVal);
 }
 
 /// getCondBranchTargetOpValue - Return the encoded value for a conditional
Index: test/MC/AArch64/darwin-reloc-addsubimm.s
===================================================================
--- /dev/null
+++ test/MC/AArch64/darwin-reloc-addsubimm.s
@@ -0,0 +1,12 @@
+// RUN: llvm-mc -triple=aarch64-darwin -filetype=obj %s -o - | \
+// RUN:   llvm-objdump -r -d - | FileCheck -check-prefix=OBJ %s
+
+// OBJ-LABEL: Disassembly of section __TEXT,__text:
+
+  add x2, x3, _data@pageoff
+// OBJ: [[addr:[0-9a-f]+]]: 62 00 00 91 add x2, x3, #0
+// OBJ-NEXT: [[addr]]: ARM64_RELOC_PAGEOFF12	_data
+
+  add x2, x3, #_data@pageoff, lsl #12
+// OBJ: [[addr:[0-9a-f]+]]: 62 00 40 91 add x2, x3, #0, lsl #12
+// OBJ-NEXT: [[addr]]: ARM64_RELOC_PAGEOFF12	_data
Index: test/MC/AArch64/elf-reloc-addsubimm.s
===================================================================
--- test/MC/AArch64/elf-reloc-addsubimm.s
+++ test/MC/AArch64/elf-reloc-addsubimm.s
@@ -1,10 +1,13 @@
 // RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj %s -o - | \
-// RUN:   llvm-readobj -r | FileCheck -check-prefix=OBJ %s
+// RUN:   llvm-objdump -r -d - | FileCheck -check-prefix=OBJ %s
+
+// OBJ-LABEL: Disassembly of section .text:
 
         add x2, x3, #:lo12:some_label
+// OBJ: [[addr:[0-9a-f]+]]: 62 00 00 91 add x2, x3, #0
+// OBJ-NEXT: [[addr]]: R_AARCH64_ADD_ABS_LO12_NC	some_label
+
+        add x2, x3, #:lo12:some_label, lsl #12
+// OBJ: [[addr:[0-9a-f]+]]: 62 00 40 91 add x2, x3, #0, lsl #12
+// OBJ-NEXT: [[addr]]: R_AARCH64_ADD_ABS_LO12_NC	some_label
 
-// OBJ:      Relocations [
-// OBJ-NEXT:   Section {{.*}} .rela.text {
-// OBJ-NEXT:     0x0 R_AARCH64_ADD_ABS_LO12_NC some_label 0x0
-// OBJ-NEXT:   }
-// OBJ-NEXT: ]
Index: test/MC/AArch64/label-arithmetic-darwin.s
===================================================================
--- test/MC/AArch64/label-arithmetic-darwin.s
+++ test/MC/AArch64/label-arithmetic-darwin.s
@@ -23,6 +23,11 @@
   // CHECK: sub w0, w1, #8
   // CHECK: sub x0, x1, #8
 
+  add w0, w1, #(Lend - Lstart), lsl #12
+  cmp w0, #(Lend - Lstart), lsl #12
+  // CHECK: add w0, w1, #8, lsl #12
+  // CHECK: cmp w0, #8, lsl #12
+
   add w0, w1, #((Lend - Lstart) >> 2)
   cmp w0, #((Lend - Lstart) >> 2)
   // CHECK: add w0, w1, #2
Index: test/MC/AArch64/label-arithmetic-elf.s
===================================================================
--- test/MC/AArch64/label-arithmetic-elf.s
+++ test/MC/AArch64/label-arithmetic-elf.s
@@ -22,6 +22,11 @@
   // CHECK: sub w0, w1, #8
   // CHECK: sub x0, x1, #8
 
+  add w0, w1, #(end - start), lsl #12
+  cmp w0, #(end - start), lsl #12
+  // CHECK: add w0, w1, #8, lsl #12
+  // CHECK: cmp w0, #8, lsl #12
+
   add w0, w1, #((end - start) >> 2)
   cmp w0, #((end - start) >> 2)
   // CHECK: add w0, w1, #2
Index: test/MC/AArch64/tls-relocs.s
===================================================================
--- test/MC/AArch64/tls-relocs.s
+++ test/MC/AArch64/tls-relocs.s
@@ -92,9 +92,9 @@
         add x17, x18, #:dtprel_hi12:var, lsl #12
         add w19, w20, #:dtprel_hi12:var, lsl #12
 
-// CHECK: add    x17, x18, :dtprel_hi12:var, lsl #12 // encoding: [0x51,0bAAAAAA10,0b00AAAAAA,0x91]
+// CHECK: add    x17, x18, :dtprel_hi12:var, lsl #12 // encoding: [0x51,0bAAAAAA10,0b01AAAAAA,0x91]
 // CHECK:                                            //   fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_aarch64_add_imm12
-// CHECK: add    w19, w20, :dtprel_hi12:var, lsl #12 // encoding: [0x93,0bAAAAAA10,0b00AAAAAA,0x11]
+// CHECK: add    w19, w20, :dtprel_hi12:var, lsl #12 // encoding: [0x93,0bAAAAAA10,0b01AAAAAA,0x11]
 // CHECK:                                            //   fixup A - offset: 0, value: :dtprel_hi12:var, kind: fixup_aarch64_add_imm12
 
 // CHECK-ELF-NEXT:     0x40 R_AARCH64_TLSLD_ADD_DTPREL_HI12 [[VARSYM]]
@@ -294,9 +294,9 @@
         add x17, x18, #:tprel_hi12:var, lsl #12
         add w19, w20, #:tprel_hi12:var, lsl #12
 
-// CHECK: add    x17, x18, :tprel_hi12:var, lsl #12 // encoding: [0x51,0bAAAAAA10,0b00AAAAAA,0x91]
+// CHECK: add    x17, x18, :tprel_hi12:var, lsl #12 // encoding: [0x51,0bAAAAAA10,0b01AAAAAA,0x91]
 // CHECK:                                           //   fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_aarch64_add_imm12
-// CHECK: add    w19, w20, :tprel_hi12:var, lsl #12 // encoding: [0x93,0bAAAAAA10,0b00AAAAAA,0x11]
+// CHECK: add    w19, w20, :tprel_hi12:var, lsl #12 // encoding: [0x93,0bAAAAAA10,0b01AAAAAA,0x11]
 // CHECK:                                           //   fixup A - offset: 0, value: :tprel_hi12:var, kind: fixup_aarch64_add_imm12
 
 // CHECK-ELF-NEXT:     0xCC R_AARCH64_TLSLE_ADD_TPREL_HI12 [[VARSYM]]