Index: lib/CodeGen/LiveIntervalAnalysis.cpp
===================================================================
--- lib/CodeGen/LiveIntervalAnalysis.cpp
+++ lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -948,8 +948,12 @@
         LiveInterval &LI = LIS.getInterval(Reg);
         if (LI.hasSubRanges()) {
           unsigned SubReg = MO.getSubReg();
+          LaneBitmask WholeMask = MRI.getMaxLaneMaskForVReg(Reg);
           LaneBitmask LaneMask = SubReg ? TRI.getSubRegIndexLaneMask(SubReg)
-                                        : MRI.getMaxLaneMaskForVReg(Reg);
+                                        : WholeMask;
+          // A non-undef subreg def reads other lanes.
+          if (SubReg != 0 && MO.isDef() && !MO.isUndef())
+            LaneMask = WholeMask;
           for (LiveInterval::SubRange &S : LI.subranges()) {
             if ((S.LaneMask & LaneMask) == 0)
               continue;
Index: test/CodeGen/AMDGPU/gs-array-copy.ll
===================================================================
--- /dev/null
+++ test/CodeGen/AMDGPU/gs-array-copy.ll
@@ -0,0 +1,172 @@
+; RUN: llc -march=amdgcn < %s | FileCheck %s
+
+; Check for a sane output instead of a crash.
+; CHECK: s_endpgm
+
+target triple = "amdgcn--"
+
+define amdgpu_gs void @main([17 x <16 x i8>] addrspace(2)* byval dereferenceable(18446744073709551615), [16 x <16 x i8>] addrspace(2)* byval dereferenceable(18446744073709551615), [32 x <8 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615), [16 x <8 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615), [16 x <4 x i32>] addrspace(2)* byval dereferenceable(18446744073709551615), i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) {
+main_body:
+  %15 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %1, i64 0, i64 0, !amdgpu.uniform !0
+  %16 = load <16 x i8>, <16 x i8> addrspace(2)* %15, align 16, !invariant.load !0
+  %17 = call float @llvm.SI.load.const(<16 x i8> %16, i32 0)
+  %18 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %1, i64 0, i64 1, !amdgpu.uniform !0
+  %19 = load <16 x i8>, <16 x i8> addrspace(2)* %18, align 16, !invariant.load !0
+  %20 = call float @llvm.SI.load.const(<16 x i8> %19, i32 16)
+  %21 = call float @llvm.SI.load.const(<16 x i8> %19, i32 20)
+  %22 = call float @llvm.SI.load.const(<16 x i8> %19, i32 24)
+  %23 = call float @llvm.SI.load.const(<16 x i8> %19, i32 28)
+  %24 = call float @llvm.SI.load.const(<16 x i8> %19, i32 32)
+  %25 = call float @llvm.SI.load.const(<16 x i8> %19, i32 36)
+  %26 = call float @llvm.SI.load.const(<16 x i8> %19, i32 40)
+  %27 = call float @llvm.SI.load.const(<16 x i8> %19, i32 44)
+  %28 = call float @llvm.SI.load.const(<16 x i8> %19, i32 48)
+  %29 = call float @llvm.SI.load.const(<16 x i8> %19, i32 52)
+  %30 = call float @llvm.SI.load.const(<16 x i8> %19, i32 56)
+  %31 = call float @llvm.SI.load.const(<16 x i8> %19, i32 60)
+  %32 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %0, i64 0, i64 3, !amdgpu.uniform !0
+  %33 = load <16 x i8>, <16 x i8> addrspace(2)* %32, align 16, !invariant.load !0
+  %34 = getelementptr [17 x <16 x i8>], [17 x <16 x i8>] addrspace(2)* %0, i64 0, i64 4, !amdgpu.uniform !0
+  %35 = load <16 x i8>, <16 x i8> addrspace(2)* %34, align 16, !invariant.load !0
+  %36 = bitcast float %17 to i32
+  %array_vector1 = insertelement <4 x float> <float 1.000000e+00, float undef, float undef, float undef>, float %20, i32 1
+  %array_vector2 = insertelement <4 x float> %array_vector1, float %24, i32 2
+  %array_vector3 = insertelement <4 x float> %array_vector2, float %28, i32 3
+  %array_vector5 = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, float %21, i32 1
+  %array_vector6 = insertelement <4 x float> %array_vector5, float %25, i32 2
+  %array_vector7 = insertelement <4 x float> %array_vector6, float %29, i32 3
+  %array_vector9 = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, float %22, i32 1
+  %array_vector10 = insertelement <4 x float> %array_vector9, float %26, i32 2
+  %array_vector11 = insertelement <4 x float> %array_vector10, float %30, i32 3
+  %array_vector13 = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, float %23, i32 1
+  %array_vector14 = insertelement <4 x float> %array_vector13, float %27, i32 2
+  %array_vector15 = insertelement <4 x float> %array_vector14, float %31, i32 3
+  %37 = shl i32 %7, 2
+  %38 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %33, i32 %37, i32 4096, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0)
+  %39 = shl i32 %7, 2
+  %40 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %33, i32 %39, i32 4352, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0)
+  %41 = shl i32 %7, 2
+  %42 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %33, i32 %41, i32 4608, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0)
+  %43 = shl i32 %7, 2
+  %44 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %33, i32 %43, i32 4864, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0)
+  call void @llvm.AMDGPU.kill(float 1.000000e+00)
+  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %35, i32 %38, i32 1, i32 0, i32 %5, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
+  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %35, i32 %40, i32 1, i32 12, i32 %5, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
+  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %35, i32 %42, i32 1, i32 24, i32 %5, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
+  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %35, i32 %44, i32 1, i32 36, i32 %5, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
+  %bc = bitcast <4 x float> %array_vector3 to <4 x i32>
+  %45 = extractelement <4 x i32> %bc, i32 %36
+  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %35, i32 %45, i32 1, i32 48, i32 %5, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
+  %bc48 = bitcast <4 x float> %array_vector7 to <4 x i32>
+  %46 = extractelement <4 x i32> %bc48, i32 %36
+  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %35, i32 %46, i32 1, i32 60, i32 %5, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
+  %bc49 = bitcast <4 x float> %array_vector11 to <4 x i32>
+  %47 = extractelement <4 x i32> %bc49, i32 %36
+  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %35, i32 %47, i32 1, i32 72, i32 %5, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
+  %bc50 = bitcast <4 x float> %array_vector15 to <4 x i32>
+  %48 = extractelement <4 x i32> %bc50, i32 %36
+  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %35, i32 %48, i32 1, i32 84, i32 %5, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
+  call void @llvm.SI.sendmsg(i32 34, i32 %6)
+  %49 = bitcast float %17 to i32
+  %array_vector17 = insertelement <4 x float> <float 1.000000e+00, float undef, float undef, float undef>, float %20, i32 1
+  %array_vector18 = insertelement <4 x float> %array_vector17, float %24, i32 2
+  %array_vector19 = insertelement <4 x float> %array_vector18, float %28, i32 3
+  %array_vector21 = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, float %21, i32 1
+  %array_vector22 = insertelement <4 x float> %array_vector21, float %25, i32 2
+  %array_vector23 = insertelement <4 x float> %array_vector22, float %29, i32 3
+  %array_vector25 = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, float %22, i32 1
+  %array_vector26 = insertelement <4 x float> %array_vector25, float %26, i32 2
+  %array_vector27 = insertelement <4 x float> %array_vector26, float %30, i32 3
+  %array_vector29 = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, float %23, i32 1
+  %array_vector30 = insertelement <4 x float> %array_vector29, float %27, i32 2
+  %array_vector31 = insertelement <4 x float> %array_vector30, float %31, i32 3
+  %50 = shl i32 %8, 2
+  %51 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %33, i32 %50, i32 4096, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0)
+  %52 = shl i32 %8, 2
+  %53 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %33, i32 %52, i32 4352, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0)
+  %54 = shl i32 %8, 2
+  %55 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %33, i32 %54, i32 4608, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0)
+  %56 = shl i32 %8, 2
+  %57 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %33, i32 %56, i32 4864, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0)
+  call void @llvm.AMDGPU.kill(float 1.000000e+00)
+  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %35, i32 %51, i32 1, i32 4, i32 %5, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
+  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %35, i32 %53, i32 1, i32 16, i32 %5, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
+  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %35, i32 %55, i32 1, i32 28, i32 %5, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
+  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %35, i32 %57, i32 1, i32 40, i32 %5, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
+  %bc51 = bitcast <4 x float> %array_vector19 to <4 x i32>
+  %58 = extractelement <4 x i32> %bc51, i32 %49
+  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %35, i32 %58, i32 1, i32 52, i32 %5, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
+  %bc52 = bitcast <4 x float> %array_vector23 to <4 x i32>
+  %59 = extractelement <4 x i32> %bc52, i32 %49
+  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %35, i32 %59, i32 1, i32 64, i32 %5, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
+  %bc53 = bitcast <4 x float> %array_vector27 to <4 x i32>
+  %60 = extractelement <4 x i32> %bc53, i32 %49
+  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %35, i32 %60, i32 1, i32 76, i32 %5, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
+  %bc54 = bitcast <4 x float> %array_vector31 to <4 x i32>
+  %61 = extractelement <4 x i32> %bc54, i32 %49
+  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %35, i32 %61, i32 1, i32 88, i32 %5, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
+  call void @llvm.SI.sendmsg(i32 34, i32 %6)
+  %62 = bitcast float %17 to i32
+  %array_vector33 = insertelement <4 x float> <float 1.000000e+00, float undef, float undef, float undef>, float %20, i32 1
+  %array_vector34 = insertelement <4 x float> %array_vector33, float %24, i32 2
+  %array_vector35 = insertelement <4 x float> %array_vector34, float %28, i32 3
+  %array_vector37 = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, float %21, i32 1
+  %array_vector38 = insertelement <4 x float> %array_vector37, float %25, i32 2
+  %array_vector39 = insertelement <4 x float> %array_vector38, float %29, i32 3
+  %array_vector41 = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, float %22, i32 1
+  %array_vector42 = insertelement <4 x float> %array_vector41, float %26, i32 2
+  %array_vector43 = insertelement <4 x float> %array_vector42, float %30, i32 3
+  %array_vector45 = insertelement <4 x float> <float 0.000000e+00, float undef, float undef, float undef>, float %23, i32 1
+  %array_vector46 = insertelement <4 x float> %array_vector45, float %27, i32 2
+  %array_vector47 = insertelement <4 x float> %array_vector46, float %31, i32 3
+  %63 = shl i32 %10, 2
+  %64 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %33, i32 %63, i32 4096, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0)
+  %65 = shl i32 %10, 2
+  %66 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %33, i32 %65, i32 4352, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0)
+  %67 = shl i32 %10, 2
+  %68 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %33, i32 %67, i32 4608, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0)
+  %69 = shl i32 %10, 2
+  %70 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8> %33, i32 %69, i32 4864, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0)
+  call void @llvm.AMDGPU.kill(float 1.000000e+00)
+  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %35, i32 %64, i32 1, i32 8, i32 %5, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
+  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %35, i32 %66, i32 1, i32 20, i32 %5, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
+  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %35, i32 %68, i32 1, i32 32, i32 %5, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
+  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %35, i32 %70, i32 1, i32 44, i32 %5, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
+  %bc55 = bitcast <4 x float> %array_vector35 to <4 x i32>
+  %71 = extractelement <4 x i32> %bc55, i32 %62
+  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %35, i32 %71, i32 1, i32 56, i32 %5, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
+  %bc56 = bitcast <4 x float> %array_vector39 to <4 x i32>
+  %72 = extractelement <4 x i32> %bc56, i32 %62
+  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %35, i32 %72, i32 1, i32 68, i32 %5, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
+  %bc57 = bitcast <4 x float> %array_vector43 to <4 x i32>
+  %73 = extractelement <4 x i32> %bc57, i32 %62
+  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %35, i32 %73, i32 1, i32 80, i32 %5, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
+  %bc58 = bitcast <4 x float> %array_vector47 to <4 x i32>
+  %74 = extractelement <4 x i32> %bc58, i32 %62
+  call void @llvm.SI.tbuffer.store.i32(<16 x i8> %35, i32 %74, i32 1, i32 92, i32 %5, i32 0, i32 4, i32 4, i32 1, i32 0, i32 1, i32 1, i32 0)
+  call void @llvm.SI.sendmsg(i32 34, i32 %6)
+  call void @llvm.SI.sendmsg(i32 3, i32 %6)
+  ret void
+}
+
+; Function Attrs: nounwind readnone
+declare float @llvm.SI.load.const(<16 x i8>, i32) #0
+
+; Function Attrs: nounwind readonly
+declare i32 @llvm.SI.buffer.load.dword.i32.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32) #1
+
+; Function Attrs: nounwind
+declare void @llvm.AMDGPU.kill(float) #2
+
+; Function Attrs: nounwind
+declare void @llvm.SI.tbuffer.store.i32(<16 x i8>, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32) #2
+
+; Function Attrs: nounwind
+declare void @llvm.SI.sendmsg(i32, i32) #2
+
+attributes #0 = { nounwind readnone }
+attributes #1 = { nounwind readonly }
+attributes #2 = { nounwind }
+
+!0 = !{}
+