Index: llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h
===================================================================
--- llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h
+++ llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h
@@ -381,8 +381,6 @@
StringRef Name;
unsigned Alignment = 0;
bool ExposesReturnsTwice = false;
- // MachineFunctionProperties
- bool AllVRegsAllocated = false;
// GISel MachineFunctionProperties.
bool Legalized = false;
bool RegBankSelected = false;
@@ -407,7 +405,6 @@
YamlIO.mapRequired("name", MF.Name);
YamlIO.mapOptional("alignment", MF.Alignment);
YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice);
- YamlIO.mapOptional("allVRegsAllocated", MF.AllVRegsAllocated);
YamlIO.mapOptional("legalized", MF.Legalized);
YamlIO.mapOptional("regBankSelected", MF.RegBankSelected);
YamlIO.mapOptional("selected", MF.Selected);
Index: llvm/trunk/include/llvm/CodeGen/MachineFunction.h
===================================================================
--- llvm/trunk/include/llvm/CodeGen/MachineFunction.h
+++ llvm/trunk/include/llvm/CodeGen/MachineFunction.h
@@ -79,7 +79,6 @@
/// Each of these has checking code in the MachineVerifier, and passes can
/// require that a property be set.
class MachineFunctionProperties {
- // TODO: Add MachineVerifier checks for AllVRegsAllocated
// Possible TODO: Allow targets to extend this (perhaps by allowing the
// constructor to specify the size of the bit vector)
// Possible TODO: Allow requiring the negative (e.g. VRegsAllocated could be
@@ -100,8 +99,7 @@
// that affect the values in registers, for example by the register
// scavenger.
// When this property is clear, liveness is no longer reliable.
- // AllVRegsAllocated: All virtual registers have been allocated; i.e. all
- // register operands are physical registers.
+ // NoVRegs: The machine function does not use any virtual registers.
// Legalized: In GlobalISel: the MachineLegalizer ran and all pre-isel generic
// instructions have been legalized; i.e., all instructions are now one of:
// - generic and always legal (e.g., COPY)
@@ -120,7 +118,7 @@
IsSSA,
NoPHIs,
TracksLiveness,
- AllVRegsAllocated,
+ NoVRegs,
Legalized,
RegBankSelected,
Selected,
Index: llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp
+++ llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp
@@ -172,7 +172,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
const char *getPassName() const override {
Index: llvm/trunk/lib/CodeGen/FuncletLayout.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/FuncletLayout.cpp
+++ llvm/trunk/lib/CodeGen/FuncletLayout.cpp
@@ -30,7 +30,7 @@
bool runOnMachineFunction(MachineFunction &F) override;
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
};
}
Index: llvm/trunk/lib/CodeGen/IfConversion.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/IfConversion.cpp
+++ llvm/trunk/lib/CodeGen/IfConversion.cpp
@@ -203,7 +203,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
private:
Index: llvm/trunk/lib/CodeGen/ImplicitNullChecks.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/ImplicitNullChecks.cpp
+++ llvm/trunk/lib/CodeGen/ImplicitNullChecks.cpp
@@ -129,7 +129,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
};
Index: llvm/trunk/lib/CodeGen/LiveDebugValues.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/LiveDebugValues.cpp
+++ llvm/trunk/lib/CodeGen/LiveDebugValues.cpp
@@ -217,7 +217,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
/// Print to ostream with a message.
Index: llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
+++ llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
@@ -312,6 +312,10 @@
Properties.set(MachineFunctionProperties::Property::IsSSA);
else
Properties.clear(MachineFunctionProperties::Property::IsSSA);
+
+ const MachineRegisterInfo &MRI = MF.getRegInfo();
+ if (MRI.getNumVirtRegs() == 0)
+ Properties.set(MachineFunctionProperties::Property::NoVRegs);
}
bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
@@ -324,8 +328,6 @@
if (YamlMF.Alignment)
MF.setAlignment(YamlMF.Alignment);
MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice);
- if (YamlMF.AllVRegsAllocated)
- MF.getProperties().set(MachineFunctionProperties::Property::AllVRegsAllocated);
if (YamlMF.Legalized)
MF.getProperties().set(MachineFunctionProperties::Property::Legalized);
Index: llvm/trunk/lib/CodeGen/MIRPrinter.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp
@@ -174,8 +174,6 @@
YamlMF.Name = MF.getName();
YamlMF.Alignment = MF.getAlignment();
YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
- YamlMF.AllVRegsAllocated = MF.getProperties().hasProperty(
- MachineFunctionProperties::Property::AllVRegsAllocated);
YamlMF.Legalized = MF.getProperties().hasProperty(
MachineFunctionProperties::Property::Legalized);
Index: llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp
+++ llvm/trunk/lib/CodeGen/MachineCopyPropagation.cpp
@@ -56,7 +56,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
private:
Index: llvm/trunk/lib/CodeGen/MachineFunction.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/MachineFunction.cpp
+++ llvm/trunk/lib/CodeGen/MachineFunction.cpp
@@ -57,10 +57,10 @@
static const char *getPropertyName(MachineFunctionProperties::Property Prop) {
typedef MachineFunctionProperties::Property P;
switch(Prop) {
- case P::AllVRegsAllocated: return "AllVRegsAllocated";
case P::IsSSA: return "IsSSA";
case P::Legalized: return "Legalized";
case P::NoPHIs: return "NoPHIs";
+ case P::NoVRegs: return "NoVRegs";
case P::RegBankSelected: return "RegBankSelected";
case P::Selected: return "Selected";
case P::TracksLiveness: return "TracksLiveness";
Index: llvm/trunk/lib/CodeGen/MachineVerifier.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/MachineVerifier.cpp
+++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp
@@ -314,15 +314,12 @@
void MachineVerifier::verifyProperties(const MachineFunction &MF) {
// If a pass has introduced virtual registers without clearing the
- // AllVRegsAllocated property (or set it without allocating the vregs)
+ // NoVRegs property (or set it without allocating the vregs)
// then report an error.
if (MF.getProperties().hasProperty(
- MachineFunctionProperties::Property::AllVRegsAllocated) &&
- MRI->getNumVirtRegs()) {
- report(
- "Function has AllVRegsAllocated property but there are VReg operands",
- &MF);
- }
+ MachineFunctionProperties::Property::NoVRegs) &&
+ MRI->getNumVirtRegs())
+ report("Function has NoVRegs property but there are VReg operands", &MF);
}
unsigned MachineVerifier::verify(MachineFunction &MF) {
Index: llvm/trunk/lib/CodeGen/PatchableFunction.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/PatchableFunction.cpp
+++ llvm/trunk/lib/CodeGen/PatchableFunction.cpp
@@ -32,7 +32,7 @@
bool runOnMachineFunction(MachineFunction &F) override;
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
};
}
Index: llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
+++ llvm/trunk/lib/CodeGen/PostRASchedulerList.cpp
@@ -98,7 +98,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
bool runOnMachineFunction(MachineFunction &Fn) override;
Index: llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
+++ llvm/trunk/lib/CodeGen/PrologEpilogInserter.cpp
@@ -80,7 +80,7 @@
MachineFunctionProperties getRequiredProperties() const override {
MachineFunctionProperties MFP;
if (UsesCalleeSaves)
- MFP.set(MachineFunctionProperties::Property::AllVRegsAllocated);
+ MFP.set(MachineFunctionProperties::Property::NoVRegs);
return MFP;
}
Index: llvm/trunk/lib/CodeGen/RegAllocFast.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/RegAllocFast.cpp
+++ llvm/trunk/lib/CodeGen/RegAllocFast.cpp
@@ -165,7 +165,7 @@
MachineFunctionProperties getSetProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
private:
Index: llvm/trunk/lib/CodeGen/StackMapLivenessAnalysis.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/StackMapLivenessAnalysis.cpp
+++ llvm/trunk/lib/CodeGen/StackMapLivenessAnalysis.cpp
@@ -63,7 +63,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
/// \brief Calculate the liveness information for the given machine function.
Index: llvm/trunk/lib/CodeGen/VirtRegMap.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/VirtRegMap.cpp
+++ llvm/trunk/lib/CodeGen/VirtRegMap.cpp
@@ -177,7 +177,7 @@
bool runOnMachineFunction(MachineFunction&) override;
MachineFunctionProperties getSetProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
};
} // end anonymous namespace
Index: llvm/trunk/lib/Target/AArch64/AArch64A53Fix835769.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64A53Fix835769.cpp
+++ llvm/trunk/lib/Target/AArch64/AArch64A53Fix835769.cpp
@@ -90,7 +90,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
const char *getPassName() const override {
Index: llvm/trunk/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
+++ llvm/trunk/lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
@@ -122,7 +122,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
const char *getPassName() const override {
Index: llvm/trunk/lib/Target/AArch64/AArch64CollectLOH.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64CollectLOH.cpp
+++ llvm/trunk/lib/Target/AArch64/AArch64CollectLOH.cpp
@@ -177,7 +177,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
const char *getPassName() const override {
Index: llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
+++ llvm/trunk/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
@@ -46,7 +46,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
const char *getPassName() const override { return AARCH64_DEAD_REG_DEF_NAME; }
Index: llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ llvm/trunk/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -162,7 +162,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
const char *getPassName() const override {
Index: llvm/trunk/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
===================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
+++ llvm/trunk/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
@@ -54,7 +54,7 @@
bool runOnMachineFunction(MachineFunction &MF) override;
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
const char *getPassName() const override {
return "AArch64 Redundant Copy Elimination";
Index: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
+++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp
@@ -197,7 +197,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
const char *getPassName() const override {
Index: llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
+++ llvm/trunk/lib/Target/ARM/ARMExpandPseudoInsts.cpp
@@ -53,7 +53,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
const char *getPassName() const override {
Index: llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
+++ llvm/trunk/lib/Target/ARM/ARMLoadStoreOptimizer.cpp
@@ -95,7 +95,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
const char *getPassName() const override {
Index: llvm/trunk/lib/Target/ARM/ARMOptimizeBarriersPass.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/ARMOptimizeBarriersPass.cpp
+++ llvm/trunk/lib/Target/ARM/ARMOptimizeBarriersPass.cpp
@@ -29,7 +29,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
const char *getPassName() const override {
Index: llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp
+++ llvm/trunk/lib/Target/ARM/Thumb2ITBlockPass.cpp
@@ -38,7 +38,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
const char *getPassName() const override {
Index: llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
===================================================================
--- llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
+++ llvm/trunk/lib/Target/ARM/Thumb2SizeReduction.cpp
@@ -148,7 +148,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
const char *getPassName() const override {
Index: llvm/trunk/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
===================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
+++ llvm/trunk/lib/Target/Hexagon/HexagonCFGOptimizer.cpp
@@ -51,7 +51,7 @@
bool runOnMachineFunction(MachineFunction &Fn) override;
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
};
Index: llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp
===================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp
+++ llvm/trunk/lib/Target/Hexagon/HexagonCopyToCombine.cpp
@@ -85,7 +85,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
private:
Index: llvm/trunk/lib/Target/Hexagon/HexagonFixupHwLoops.cpp
===================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonFixupHwLoops.cpp
+++ llvm/trunk/lib/Target/Hexagon/HexagonFixupHwLoops.cpp
@@ -47,7 +47,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
const char *getPassName() const override {
Index: llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ llvm/trunk/lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -182,7 +182,7 @@
bool runOnMachineFunction(MachineFunction &MF) override;
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
};
Index: llvm/trunk/lib/Target/Hexagon/HexagonGenMux.cpp
===================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonGenMux.cpp
+++ llvm/trunk/lib/Target/Hexagon/HexagonGenMux.cpp
@@ -51,7 +51,7 @@
bool runOnMachineFunction(MachineFunction &MF) override;
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
private:
Index: llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp
===================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp
+++ llvm/trunk/lib/Target/Hexagon/HexagonNewValueJump.cpp
@@ -85,7 +85,7 @@
bool runOnMachineFunction(MachineFunction &Fn) override;
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
private:
Index: llvm/trunk/lib/Target/Hexagon/HexagonRDFOpt.cpp
===================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonRDFOpt.cpp
+++ llvm/trunk/lib/Target/Hexagon/HexagonRDFOpt.cpp
@@ -57,7 +57,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
static char ID;
Index: llvm/trunk/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
===================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
+++ llvm/trunk/lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
@@ -49,7 +49,7 @@
bool runOnMachineFunction(MachineFunction &Fn) override;
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
};
}
Index: llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
===================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
+++ llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
@@ -80,7 +80,7 @@
bool runOnMachineFunction(MachineFunction &Fn) override;
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
private:
Index: llvm/trunk/lib/Target/Lanai/LanaiDelaySlotFiller.cpp
===================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiDelaySlotFiller.cpp
+++ llvm/trunk/lib/Target/Lanai/LanaiDelaySlotFiller.cpp
@@ -60,7 +60,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
void insertDefsUses(MachineBasicBlock::instr_iterator MI,
Index: llvm/trunk/lib/Target/Lanai/LanaiMemAluCombiner.cpp
===================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiMemAluCombiner.cpp
+++ llvm/trunk/lib/Target/Lanai/LanaiMemAluCombiner.cpp
@@ -69,7 +69,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
private:
Index: llvm/trunk/lib/Target/MSP430/MSP430BranchSelector.cpp
===================================================================
--- llvm/trunk/lib/Target/MSP430/MSP430BranchSelector.cpp
+++ llvm/trunk/lib/Target/MSP430/MSP430BranchSelector.cpp
@@ -41,7 +41,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
const char *getPassName() const override {
Index: llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp
+++ llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp
@@ -364,7 +364,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
void doInitialPlacement(std::vector<MachineInstr*> &CPEMIs);
Index: llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
+++ llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp
@@ -213,7 +213,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
void getAnalysisUsage(AnalysisUsage &AU) const override {
Index: llvm/trunk/lib/Target/Mips/MipsHazardSchedule.cpp
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsHazardSchedule.cpp
+++ llvm/trunk/lib/Target/Mips/MipsHazardSchedule.cpp
@@ -76,7 +76,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
private:
Index: llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp
+++ llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp
@@ -74,7 +74,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
private:
Index: llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp
===================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp
+++ llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp
@@ -48,7 +48,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
const char *getPassName() const override {
Index: llvm/trunk/lib/Target/PowerPC/PPCEarlyReturn.cpp
===================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCEarlyReturn.cpp
+++ llvm/trunk/lib/Target/PowerPC/PPCEarlyReturn.cpp
@@ -196,7 +196,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
void getAnalysisUsage(AnalysisUsage &AU) const override {
Index: llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp
===================================================================
--- llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp
+++ llvm/trunk/lib/Target/Sparc/DelaySlotFiller.cpp
@@ -64,7 +64,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
void insertCallDefsUses(MachineBasicBlock::iterator MI,
Index: llvm/trunk/lib/Target/SystemZ/SystemZElimCompare.cpp
===================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZElimCompare.cpp
+++ llvm/trunk/lib/Target/SystemZ/SystemZElimCompare.cpp
@@ -66,7 +66,7 @@
bool runOnMachineFunction(MachineFunction &F) override;
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
private:
Index: llvm/trunk/lib/Target/SystemZ/SystemZLongBranch.cpp
===================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZLongBranch.cpp
+++ llvm/trunk/lib/Target/SystemZ/SystemZLongBranch.cpp
@@ -140,7 +140,7 @@
bool runOnMachineFunction(MachineFunction &F) override;
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
private:
Index: llvm/trunk/lib/Target/SystemZ/SystemZShortenInst.cpp
===================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZShortenInst.cpp
+++ llvm/trunk/lib/Target/SystemZ/SystemZShortenInst.cpp
@@ -37,7 +37,7 @@
bool runOnMachineFunction(MachineFunction &F) override;
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
private:
Index: llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
===================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
@@ -196,7 +196,7 @@
// Has no asserts of its own, but was not written to handle virtual regs.
disablePass(&ShrinkWrapID);
- // These functions all require the AllVRegsAllocated property.
+ // These functions all require the NoVRegs property.
disablePass(&MachineCopyPropagationID);
disablePass(&PostRASchedulerID);
disablePass(&FuncletLayoutID);
Index: llvm/trunk/lib/Target/X86/X86ExpandPseudo.cpp
===================================================================
--- llvm/trunk/lib/Target/X86/X86ExpandPseudo.cpp
+++ llvm/trunk/lib/Target/X86/X86ExpandPseudo.cpp
@@ -51,7 +51,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
const char *getPassName() const override {
Index: llvm/trunk/lib/Target/X86/X86FixupBWInsts.cpp
===================================================================
--- llvm/trunk/lib/Target/X86/X86FixupBWInsts.cpp
+++ llvm/trunk/lib/Target/X86/X86FixupBWInsts.cpp
@@ -125,7 +125,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
private:
Index: llvm/trunk/lib/Target/X86/X86FixupLEAs.cpp
===================================================================
--- llvm/trunk/lib/Target/X86/X86FixupLEAs.cpp
+++ llvm/trunk/lib/Target/X86/X86FixupLEAs.cpp
@@ -95,7 +95,7 @@
// This pass runs after regalloc and doesn't support VReg operands.
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
private:
Index: llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
===================================================================
--- llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
+++ llvm/trunk/lib/Target/X86/X86FloatingPoint.cpp
@@ -78,7 +78,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
const char *getPassName() const override { return "X86 FP Stackifier"; }
Index: llvm/trunk/lib/Target/X86/X86PadShortFunction.cpp
===================================================================
--- llvm/trunk/lib/Target/X86/X86PadShortFunction.cpp
+++ llvm/trunk/lib/Target/X86/X86PadShortFunction.cpp
@@ -57,7 +57,7 @@
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
const char *getPassName() const override {
Index: llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp
===================================================================
--- llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp
+++ llvm/trunk/lib/Target/X86/X86VZeroUpper.cpp
@@ -40,7 +40,7 @@
bool runOnMachineFunction(MachineFunction &MF) override;
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
const char *getPassName() const override {return "X86 vzeroupper inserter";}
Index: llvm/trunk/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp
===================================================================
--- llvm/trunk/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp
+++ llvm/trunk/lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp
@@ -29,7 +29,7 @@
bool runOnMachineFunction(MachineFunction &Fn) override;
MachineFunctionProperties getRequiredProperties() const override {
return MachineFunctionProperties().set(
- MachineFunctionProperties::Property::AllVRegsAllocated);
+ MachineFunctionProperties::Property::NoVRegs);
}
const char *getPassName() const override {
Index: llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir
===================================================================
--- llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir
+++ llvm/trunk/test/CodeGen/AArch64/ldst-opt-dbg-limit.mir
@@ -28,7 +28,6 @@
name: promote-load-from-store
alignment: 2
exposesReturnsTwice: false
-allVRegsAllocated: true
tracksRegLiveness: false
liveins:
- { reg: '%x0' }
@@ -83,7 +82,6 @@
name: store-pair
alignment: 2
exposesReturnsTwice: false
-allVRegsAllocated: true
tracksRegLiveness: false
liveins:
- { reg: '%x0' }
Index: llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir
===================================================================
--- llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir
+++ llvm/trunk/test/CodeGen/AArch64/movimm-wzr.mir
@@ -15,7 +15,6 @@
name: test_mov_0
alignment: 2
exposesReturnsTwice: false
-allVRegsAllocated: true
tracksRegLiveness: false
frameInfo:
isFrameAddressTaken: false
Index: llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir
===================================================================
--- llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir
+++ llvm/trunk/test/CodeGen/ARM/ARMLoadStoreDBG.mir
@@ -79,7 +79,6 @@
name: f
alignment: 1
exposesReturnsTwice: false
-allVRegsAllocated: true
tracksRegLiveness: true
liveins:
- { reg: '%r0' }
Index: llvm/trunk/test/CodeGen/Hexagon/ifcvt-impuse-livein.mir
===================================================================
--- llvm/trunk/test/CodeGen/Hexagon/ifcvt-impuse-livein.mir
+++ llvm/trunk/test/CodeGen/Hexagon/ifcvt-impuse-livein.mir
@@ -14,7 +14,6 @@
---
name: foo
tracksRegLiveness: true
-allVRegsAllocated: true
body: |
bb.0:
successors: %bb.1, %bb.2
Index: llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
===================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
+++ llvm/trunk/test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
@@ -33,7 +33,6 @@
name: test_tlsdesc_callseq_length
alignment: 2
exposesReturnsTwice: false
-allVRegsAllocated: true
tracksRegLiveness: false
liveins:
- { reg: '%w0' }
Index: llvm/trunk/test/CodeGen/MIR/AArch64/machine-dead-copy.mir
===================================================================
--- llvm/trunk/test/CodeGen/MIR/AArch64/machine-dead-copy.mir
+++ llvm/trunk/test/CodeGen/MIR/AArch64/machine-dead-copy.mir
@@ -13,9 +13,8 @@
# CHECK-LABEL: name: copyprop1
# CHECK: bb.0:
# CHECK-NOT: %w20 = COPY
-name: copyprop1
-allVRegsAllocated: true
-body: |
+name: copyprop1
+body: |
bb.0:
liveins: %w0, %w1
%w20 = COPY %w1
@@ -28,9 +27,8 @@
# CHECK-LABEL: name: copyprop2
# CHECK: bb.0:
# CHECK: %w20 = COPY
-name: copyprop2
-allVRegsAllocated: true
-body: |
+name: copyprop2
+body: |
bb.0:
liveins: %w0, %w1
%w20 = COPY %w1
@@ -43,9 +41,8 @@
# CHECK-LABEL: name: copyprop3
# CHECK: bb.0:
# CHECK-NOT: COPY
-name: copyprop3
-allVRegsAllocated: true
-body: |
+name: copyprop3
+body: |
bb.0:
liveins: %w0, %w1
%w20 = COPY %w1
@@ -58,9 +55,8 @@
# CHECK-LABEL: name: copyprop4
# CHECK: bb.0:
# CHECK-NOT: COPY
-name: copyprop4
-allVRegsAllocated: true
-body: |
+name: copyprop4
+body: |
bb.0:
liveins: %w0, %w1
%w20 = COPY %w0
Index: llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir
===================================================================
--- llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir
+++ llvm/trunk/test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir
@@ -90,7 +90,6 @@
name: f
alignment: 1
exposesReturnsTwice: false
-allVRegsAllocated: true
tracksRegLiveness: true
liveins:
- { reg: '%r0' }
Index: llvm/trunk/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir
===================================================================
--- llvm/trunk/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir
+++ llvm/trunk/test/CodeGen/MIR/Hexagon/anti-dep-partial.mir
@@ -10,7 +10,6 @@
---
name: foo
tracksRegLiveness: true
-allVRegsAllocated: true
body: |
bb.0:
successors:
Index: llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir
===================================================================
--- llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir
+++ llvm/trunk/test/CodeGen/MIR/Lanai/peephole-compare.mir
@@ -175,7 +175,6 @@
name: test0a
alignment: 2
exposesReturnsTwice: false
-allVRegsAllocated: false
tracksRegLiveness: true
registers:
- { id: 0, class: gpr }
@@ -220,7 +219,6 @@
name: test0b
alignment: 2
exposesReturnsTwice: false
-allVRegsAllocated: false
tracksRegLiveness: true
registers:
- { id: 0, class: gpr }
@@ -263,7 +261,6 @@
name: test1a
alignment: 2
exposesReturnsTwice: false
-allVRegsAllocated: false
tracksRegLiveness: true
registers:
- { id: 0, class: gpr }
@@ -310,7 +307,6 @@
name: test1b
alignment: 2
exposesReturnsTwice: false
-allVRegsAllocated: false
tracksRegLiveness: true
registers:
- { id: 0, class: gpr }
@@ -357,7 +353,6 @@
name: test2a
alignment: 2
exposesReturnsTwice: false
-allVRegsAllocated: false
tracksRegLiveness: true
registers:
- { id: 0, class: gpr }
@@ -404,7 +399,6 @@
name: test2b
alignment: 2
exposesReturnsTwice: false
-allVRegsAllocated: false
tracksRegLiveness: true
registers:
- { id: 0, class: gpr }
@@ -451,7 +445,6 @@
name: test3
alignment: 2
exposesReturnsTwice: false
-allVRegsAllocated: false
tracksRegLiveness: true
registers:
- { id: 0, class: gpr }
@@ -498,7 +491,6 @@
name: test4
alignment: 2
exposesReturnsTwice: false
-allVRegsAllocated: false
tracksRegLiveness: true
registers:
- { id: 0, class: gpr }
@@ -609,7 +601,6 @@
name: testBB
alignment: 2
exposesReturnsTwice: false
-allVRegsAllocated: false
tracksRegLiveness: true
registers:
- { id: 0, class: gpr }
Index: llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir
+++ llvm/trunk/test/CodeGen/PowerPC/aantidep-def-ec.mir
@@ -44,7 +44,6 @@
name: mm_update_next_owner
alignment: 4
exposesReturnsTwice: false
-allVRegsAllocated: true
tracksRegLiveness: true
liveins:
- { reg: '%x3' }
Index: llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
+++ llvm/trunk/test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
@@ -26,7 +26,6 @@
name: test1
alignment: 4
exposesReturnsTwice: false
-allVRegsAllocated: true
tracksRegLiveness: true
frameInfo:
isFrameAddressTaken: false
Index: llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
===================================================================
--- llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
+++ llvm/trunk/test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
@@ -32,7 +32,6 @@
name: fn1
alignment: 2
exposesReturnsTwice: false
-allVRegsAllocated: false
tracksRegLiveness: true
registers:
- { id: 0, class: g8rc }
Index: llvm/trunk/test/CodeGen/X86/eflags-copy-expansion.mir
===================================================================
--- llvm/trunk/test/CodeGen/X86/eflags-copy-expansion.mir
+++ llvm/trunk/test/CodeGen/X86/eflags-copy-expansion.mir
@@ -19,7 +19,6 @@
---
name: foo
-allVRegsAllocated: true
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
Index: llvm/trunk/test/CodeGen/X86/fixup-bw-copy.mir
===================================================================
--- llvm/trunk/test/CodeGen/X86/fixup-bw-copy.mir
+++ llvm/trunk/test/CodeGen/X86/fixup-bw-copy.mir
@@ -38,7 +38,6 @@
---
name: test_movb_killed
-allVRegsAllocated: true
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
@@ -54,7 +53,6 @@
---
name: test_movb_impuse
-allVRegsAllocated: true
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
@@ -70,7 +68,6 @@
---
name: test_movb_impdef_gr64
-allVRegsAllocated: true
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
@@ -86,7 +83,6 @@
---
name: test_movb_impdef_gr32
-allVRegsAllocated: true
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
@@ -102,7 +98,6 @@
---
name: test_movb_impdef_gr16
-allVRegsAllocated: true
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
@@ -118,7 +113,6 @@
---
name: test_movw_impdef_gr32
-allVRegsAllocated: true
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
@@ -134,7 +128,6 @@
---
name: test_movw_impdef_gr64
-allVRegsAllocated: true
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
Index: llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir
===================================================================
--- llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir
+++ llvm/trunk/test/CodeGen/X86/implicit-null-checks.mir
@@ -85,7 +85,6 @@
name: imp_null_check_with_bitwise_op_0
# CHECK-LABEL: name: imp_null_check_with_bitwise_op_0
alignment: 4
-allVRegsAllocated: true
tracksRegLiveness: true
liveins:
- { reg: '%rdi' }
@@ -128,7 +127,6 @@
---
name: imp_null_check_with_bitwise_op_1
alignment: 4
-allVRegsAllocated: true
tracksRegLiveness: true
liveins:
- { reg: '%rdi' }
@@ -176,7 +174,6 @@
name: imp_null_check_with_bitwise_op_2
# CHECK-LABEL: name: imp_null_check_with_bitwise_op_2
alignment: 4
-allVRegsAllocated: true
tracksRegLiveness: true
liveins:
- { reg: '%rdi' }
@@ -220,7 +217,6 @@
name: imp_null_check_with_bitwise_op_3
# CHECK-LABEL: name: imp_null_check_with_bitwise_op_3
alignment: 4
-allVRegsAllocated: true
tracksRegLiveness: true
liveins:
- { reg: '%rdi' }
Index: llvm/trunk/test/CodeGen/X86/machine-copy-prop.mir
===================================================================
--- llvm/trunk/test/CodeGen/X86/machine-copy-prop.mir
+++ llvm/trunk/test/CodeGen/X86/machine-copy-prop.mir
@@ -25,7 +25,6 @@
# CHECK-NOT: COPY
# CHECK-NEXT: NOOP implicit %rax, implicit %rdi
name: copyprop_remove_kill0
-allVRegsAllocated: true
body: |
bb.0:
%rax = COPY %rdi
@@ -43,7 +42,6 @@
# CHECK-NOT: COPY
# CHECK-NEXT: NOOP implicit %rax, implicit %rdi
name: copyprop_remove_kill1
-allVRegsAllocated: true
body: |
bb.0:
%rax = COPY %rdi
@@ -61,7 +59,6 @@
# CHECK-NOT: COPY
# CHECK-NEXT: NOOP implicit %rax, implicit %rdi
name: copyprop_remove_kill2
-allVRegsAllocated: true
body: |
bb.0:
%ax = COPY %di
@@ -79,7 +76,6 @@
# CHECK-NOT: COPY
# CHECK-NEXT: NOOP implicit %rax, implicit %rdi
name: copyprop0
-allVRegsAllocated: true
body: |
bb.0:
%rax = COPY %rdi
@@ -96,7 +92,6 @@
# CHECK-NEXT: NOOP implicit %rax
# CHECK-NEXT: NOOP implicit %rax, implicit %rdi
name: copyprop1
-allVRegsAllocated: true
body: |
bb.0:
%rax = COPY %rdi
@@ -113,7 +108,6 @@
# CHECK-NOT: %rax = COPY %rdi
# CHECK-NEXT: NOOP implicit %rax, implicit %rdi
name: copyprop2
-allVRegsAllocated: true
body: |
bb.0:
%rax = COPY %rdi
@@ -132,7 +126,6 @@
# CHECK-NEXT: %rbp = COPY %rax
# CHECK-NEXT: NOOP implicit %rax, implicit %rbp
name: nocopyprop0
-allVRegsAllocated: true
body: |
bb.0:
%rax = COPY %rbp
@@ -150,7 +143,6 @@
# CHECK-NEXT: %rax = COPY %rbp
# CHECK-NEXT: NOOP implicit %rax, implicit %rbp
name: nocopyprop1
-allVRegsAllocated: true
body: |
bb.0:
%rbp = COPY %rax
@@ -168,7 +160,6 @@
# CHECK-NEXT: %rax = COPY %rbp
# CHECK-NEXT: NOOP implicit %rax, implicit %rbp
name: nocopyprop2
-allVRegsAllocated: true
body: |
bb.0:
%rax = COPY %rbp
@@ -186,7 +177,6 @@
# CHECK-NEXT: %rbp = COPY %rax
# CHECK-NEXT: NOOP implicit %rax, implicit %rbp
name: nocopyprop3
-allVRegsAllocated: true
body: |
bb.0:
%rbp = COPY %rax
@@ -203,7 +193,6 @@
# CHECK-NEXT: %rax = COPY %rip
# CHECK-NEXT: NOOP implicit %rax
name: nocopyprop4
-allVRegsAllocated: true
body: |
bb.0:
%rax = COPY %rip
@@ -219,7 +208,6 @@
# CHECK-NEXT: %rip = COPY %rax
# CHECK-NEXT: %rip = COPY %rax
name: nocopyprop5
-allVRegsAllocated: true
body: |
bb.0:
%rip = COPY %rax
Index: llvm/trunk/test/CodeGen/X86/pr27681.mir
===================================================================
--- llvm/trunk/test/CodeGen/X86/pr27681.mir
+++ llvm/trunk/test/CodeGen/X86/pr27681.mir
@@ -11,7 +11,6 @@
---
# CHECK-LABEL: main
name: main
-allVRegsAllocated: true
tracksRegLiveness: true
frameInfo:
stackSize: 52
Index: llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir
===================================================================
--- llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir
+++ llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values-3preds.mir
@@ -157,7 +157,6 @@
name: add
alignment: 4
exposesReturnsTwice: false
-allVRegsAllocated: true
tracksRegLiveness: true
liveins:
- { reg: '%edi' }
Index: llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir
===================================================================
--- llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir
+++ llvm/trunk/test/DebugInfo/MIR/X86/live-debug-values.mir
@@ -159,7 +159,6 @@
name: main
alignment: 4
exposesReturnsTwice: false
-allVRegsAllocated: true
tracksRegLiveness: true
liveins:
- { reg: '%edi' }