Index: include/llvm/CodeGen/MIRYamlMapping.h =================================================================== --- include/llvm/CodeGen/MIRYamlMapping.h +++ include/llvm/CodeGen/MIRYamlMapping.h @@ -382,8 +382,6 @@ unsigned Alignment = 0; bool ExposesReturnsTwice = false; bool HasInlineAsm = false; - // MachineFunctionProperties - bool AllVRegsAllocated = false; // GISel MachineFunctionProperties. bool Legalized = false; bool RegBankSelected = false; @@ -410,7 +408,6 @@ YamlIO.mapOptional("alignment", MF.Alignment); YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice); YamlIO.mapOptional("hasInlineAsm", MF.HasInlineAsm); - YamlIO.mapOptional("allVRegsAllocated", MF.AllVRegsAllocated); YamlIO.mapOptional("legalized", MF.Legalized); YamlIO.mapOptional("regBankSelected", MF.RegBankSelected); YamlIO.mapOptional("selected", MF.Selected); Index: include/llvm/CodeGen/MachineFunction.h =================================================================== --- include/llvm/CodeGen/MachineFunction.h +++ include/llvm/CodeGen/MachineFunction.h @@ -79,7 +79,6 @@ /// Each of these has checking code in the MachineVerifier, and passes can /// require that a property be set. class MachineFunctionProperties { - // TODO: Add MachineVerifier checks for AllVRegsAllocated // Possible TODO: Allow targets to extend this (perhaps by allowing the // constructor to specify the size of the bit vector) // Possible TODO: Allow requiring the negative (e.g. VRegsAllocated could be @@ -100,8 +99,7 @@ // that affect the values in registers, for example by the register // scavenger. // When this property is clear, liveness is no longer reliable. - // AllVRegsAllocated: All virtual registers have been allocated; i.e. all - // register operands are physical registers. + // NoVRegs: The machine function does not use any virtual registers. // Legalized: In GlobalISel: the MachineLegalizer ran and all pre-isel generic // instructions have been legalized; i.e., all instructions are now one of: // - generic and always legal (e.g., COPY) @@ -120,7 +118,7 @@ IsSSA, NoPHIs, TracksLiveness, - AllVRegsAllocated, + NoVRegs, Legalized, RegBankSelected, Selected, Index: lib/CodeGen/ExecutionDepsFix.cpp =================================================================== --- lib/CodeGen/ExecutionDepsFix.cpp +++ lib/CodeGen/ExecutionDepsFix.cpp @@ -172,7 +172,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { Index: lib/CodeGen/FuncletLayout.cpp =================================================================== --- lib/CodeGen/FuncletLayout.cpp +++ lib/CodeGen/FuncletLayout.cpp @@ -30,7 +30,7 @@ bool runOnMachineFunction(MachineFunction &F) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } }; } Index: lib/CodeGen/IfConversion.cpp =================================================================== --- lib/CodeGen/IfConversion.cpp +++ lib/CodeGen/IfConversion.cpp @@ -192,7 +192,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: Index: lib/CodeGen/ImplicitNullChecks.cpp =================================================================== --- lib/CodeGen/ImplicitNullChecks.cpp +++ lib/CodeGen/ImplicitNullChecks.cpp @@ -129,7 +129,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } }; Index: lib/CodeGen/LiveDebugValues.cpp =================================================================== --- lib/CodeGen/LiveDebugValues.cpp +++ lib/CodeGen/LiveDebugValues.cpp @@ -217,7 +217,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } /// Print to ostream with a message. Index: lib/CodeGen/MIRParser/MIRParser.cpp =================================================================== --- lib/CodeGen/MIRParser/MIRParser.cpp +++ lib/CodeGen/MIRParser/MIRParser.cpp @@ -308,6 +308,10 @@ Properties.set(MachineFunctionProperties::Property::IsSSA); else Properties.clear(MachineFunctionProperties::Property::IsSSA); + + const MachineRegisterInfo &MRI = MF.getRegInfo(); + if (MRI.getNumVirtRegs() == 0) + Properties.set(MachineFunctionProperties::Property::NoVRegs); } bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) { @@ -321,8 +325,6 @@ MF.setAlignment(YamlMF.Alignment); MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice); MF.setHasInlineAsm(YamlMF.HasInlineAsm); - if (YamlMF.AllVRegsAllocated) - MF.getProperties().set(MachineFunctionProperties::Property::AllVRegsAllocated); if (YamlMF.Legalized) MF.getProperties().set(MachineFunctionProperties::Property::Legalized); Index: lib/CodeGen/MIRPrinter.cpp =================================================================== --- lib/CodeGen/MIRPrinter.cpp +++ lib/CodeGen/MIRPrinter.cpp @@ -175,8 +175,6 @@ YamlMF.Alignment = MF.getAlignment(); YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice(); YamlMF.HasInlineAsm = MF.hasInlineAsm(); - YamlMF.AllVRegsAllocated = MF.getProperties().hasProperty( - MachineFunctionProperties::Property::AllVRegsAllocated); YamlMF.Legalized = MF.getProperties().hasProperty( MachineFunctionProperties::Property::Legalized); Index: lib/CodeGen/MachineCopyPropagation.cpp =================================================================== --- lib/CodeGen/MachineCopyPropagation.cpp +++ lib/CodeGen/MachineCopyPropagation.cpp @@ -56,7 +56,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: Index: lib/CodeGen/MachineFunction.cpp =================================================================== --- lib/CodeGen/MachineFunction.cpp +++ lib/CodeGen/MachineFunction.cpp @@ -57,10 +57,10 @@ static const char *getPropertyName(MachineFunctionProperties::Property Prop) { typedef MachineFunctionProperties::Property P; switch(Prop) { - case P::AllVRegsAllocated: return "AllVRegsAllocated"; case P::IsSSA: return "IsSSA"; case P::Legalized: return "Legalized"; case P::NoPHIs: return "NoPHIs"; + case P::NoVRegs: return "NoVRegs"; case P::RegBankSelected: return "RegBankSelected"; case P::Selected: return "Selected"; case P::TracksLiveness: return "TracksLiveness"; Index: lib/CodeGen/MachineVerifier.cpp =================================================================== --- lib/CodeGen/MachineVerifier.cpp +++ lib/CodeGen/MachineVerifier.cpp @@ -314,13 +314,13 @@ void MachineVerifier::verifyProperties(const MachineFunction &MF) { // If a pass has introduced virtual registers without clearing the - // AllVRegsAllocated property (or set it without allocating the vregs) + // NoVRegs property (or set it without allocating the vregs) // then report an error. if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::AllVRegsAllocated) && + MachineFunctionProperties::Property::NoVRegs) && MRI->getNumVirtRegs()) { report( - "Function has AllVRegsAllocated property but there are VReg operands", + "Function has NoVRegs property but there are VReg operands", &MF); } } Index: lib/CodeGen/PatchableFunction.cpp =================================================================== --- lib/CodeGen/PatchableFunction.cpp +++ lib/CodeGen/PatchableFunction.cpp @@ -32,7 +32,7 @@ bool runOnMachineFunction(MachineFunction &F) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } }; } Index: lib/CodeGen/PostRASchedulerList.cpp =================================================================== --- lib/CodeGen/PostRASchedulerList.cpp +++ lib/CodeGen/PostRASchedulerList.cpp @@ -98,7 +98,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } bool runOnMachineFunction(MachineFunction &Fn) override; Index: lib/CodeGen/PrologEpilogInserter.cpp =================================================================== --- lib/CodeGen/PrologEpilogInserter.cpp +++ lib/CodeGen/PrologEpilogInserter.cpp @@ -80,7 +80,7 @@ MachineFunctionProperties getRequiredProperties() const override { MachineFunctionProperties MFP; if (UsesCalleeSaves) - MFP.set(MachineFunctionProperties::Property::AllVRegsAllocated); + MFP.set(MachineFunctionProperties::Property::NoVRegs); return MFP; } Index: lib/CodeGen/RegAllocFast.cpp =================================================================== --- lib/CodeGen/RegAllocFast.cpp +++ lib/CodeGen/RegAllocFast.cpp @@ -165,7 +165,7 @@ MachineFunctionProperties getSetProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: Index: lib/CodeGen/StackMapLivenessAnalysis.cpp =================================================================== --- lib/CodeGen/StackMapLivenessAnalysis.cpp +++ lib/CodeGen/StackMapLivenessAnalysis.cpp @@ -63,7 +63,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } /// \brief Calculate the liveness information for the given machine function. Index: lib/CodeGen/VirtRegMap.cpp =================================================================== --- lib/CodeGen/VirtRegMap.cpp +++ lib/CodeGen/VirtRegMap.cpp @@ -177,7 +177,7 @@ bool runOnMachineFunction(MachineFunction&) override; MachineFunctionProperties getSetProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } }; } // end anonymous namespace Index: lib/Target/AArch64/AArch64A53Fix835769.cpp =================================================================== --- lib/Target/AArch64/AArch64A53Fix835769.cpp +++ lib/Target/AArch64/AArch64A53Fix835769.cpp @@ -90,7 +90,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { Index: lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp =================================================================== --- lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp +++ lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp @@ -122,7 +122,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { Index: lib/Target/AArch64/AArch64CollectLOH.cpp =================================================================== --- lib/Target/AArch64/AArch64CollectLOH.cpp +++ lib/Target/AArch64/AArch64CollectLOH.cpp @@ -177,7 +177,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { Index: lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp =================================================================== --- lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp +++ lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp @@ -46,7 +46,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { return AARCH64_DEAD_REG_DEF_NAME; } Index: lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp =================================================================== --- lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp +++ lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp @@ -162,7 +162,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { Index: lib/Target/AArch64/AArch64RedundantCopyElimination.cpp =================================================================== --- lib/Target/AArch64/AArch64RedundantCopyElimination.cpp +++ lib/Target/AArch64/AArch64RedundantCopyElimination.cpp @@ -54,7 +54,7 @@ bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { return "AArch64 Redundant Copy Elimination"; Index: lib/Target/ARM/ARMConstantIslandPass.cpp =================================================================== --- lib/Target/ARM/ARMConstantIslandPass.cpp +++ lib/Target/ARM/ARMConstantIslandPass.cpp @@ -197,7 +197,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { Index: lib/Target/ARM/ARMExpandPseudoInsts.cpp =================================================================== --- lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -53,7 +53,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { Index: lib/Target/ARM/ARMLoadStoreOptimizer.cpp =================================================================== --- lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -95,7 +95,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { Index: lib/Target/ARM/ARMOptimizeBarriersPass.cpp =================================================================== --- lib/Target/ARM/ARMOptimizeBarriersPass.cpp +++ lib/Target/ARM/ARMOptimizeBarriersPass.cpp @@ -29,7 +29,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { Index: lib/Target/ARM/Thumb2ITBlockPass.cpp =================================================================== --- lib/Target/ARM/Thumb2ITBlockPass.cpp +++ lib/Target/ARM/Thumb2ITBlockPass.cpp @@ -38,7 +38,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { Index: lib/Target/ARM/Thumb2SizeReduction.cpp =================================================================== --- lib/Target/ARM/Thumb2SizeReduction.cpp +++ lib/Target/ARM/Thumb2SizeReduction.cpp @@ -148,7 +148,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { Index: lib/Target/Hexagon/HexagonCFGOptimizer.cpp =================================================================== --- lib/Target/Hexagon/HexagonCFGOptimizer.cpp +++ lib/Target/Hexagon/HexagonCFGOptimizer.cpp @@ -51,7 +51,7 @@ bool runOnMachineFunction(MachineFunction &Fn) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } }; Index: lib/Target/Hexagon/HexagonCopyToCombine.cpp =================================================================== --- lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -85,7 +85,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: Index: lib/Target/Hexagon/HexagonFixupHwLoops.cpp =================================================================== --- lib/Target/Hexagon/HexagonFixupHwLoops.cpp +++ lib/Target/Hexagon/HexagonFixupHwLoops.cpp @@ -47,7 +47,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { Index: lib/Target/Hexagon/HexagonFrameLowering.cpp =================================================================== --- lib/Target/Hexagon/HexagonFrameLowering.cpp +++ lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -182,7 +182,7 @@ bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } }; Index: lib/Target/Hexagon/HexagonGenMux.cpp =================================================================== --- lib/Target/Hexagon/HexagonGenMux.cpp +++ lib/Target/Hexagon/HexagonGenMux.cpp @@ -51,7 +51,7 @@ bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: Index: lib/Target/Hexagon/HexagonNewValueJump.cpp =================================================================== --- lib/Target/Hexagon/HexagonNewValueJump.cpp +++ lib/Target/Hexagon/HexagonNewValueJump.cpp @@ -85,7 +85,7 @@ bool runOnMachineFunction(MachineFunction &Fn) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: Index: lib/Target/Hexagon/HexagonRDFOpt.cpp =================================================================== --- lib/Target/Hexagon/HexagonRDFOpt.cpp +++ lib/Target/Hexagon/HexagonRDFOpt.cpp @@ -57,7 +57,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } static char ID; Index: lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp =================================================================== --- lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp +++ lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp @@ -49,7 +49,7 @@ bool runOnMachineFunction(MachineFunction &Fn) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } }; } Index: lib/Target/Hexagon/HexagonVLIWPacketizer.cpp =================================================================== --- lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -80,7 +80,7 @@ bool runOnMachineFunction(MachineFunction &Fn) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: Index: lib/Target/Lanai/LanaiDelaySlotFiller.cpp =================================================================== --- lib/Target/Lanai/LanaiDelaySlotFiller.cpp +++ lib/Target/Lanai/LanaiDelaySlotFiller.cpp @@ -60,7 +60,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } void insertDefsUses(MachineBasicBlock::instr_iterator MI, Index: lib/Target/Lanai/LanaiMemAluCombiner.cpp =================================================================== --- lib/Target/Lanai/LanaiMemAluCombiner.cpp +++ lib/Target/Lanai/LanaiMemAluCombiner.cpp @@ -69,7 +69,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: Index: lib/Target/MSP430/MSP430BranchSelector.cpp =================================================================== --- lib/Target/MSP430/MSP430BranchSelector.cpp +++ lib/Target/MSP430/MSP430BranchSelector.cpp @@ -41,7 +41,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { Index: lib/Target/Mips/MipsConstantIslandPass.cpp =================================================================== --- lib/Target/Mips/MipsConstantIslandPass.cpp +++ lib/Target/Mips/MipsConstantIslandPass.cpp @@ -364,7 +364,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } void doInitialPlacement(std::vector &CPEMIs); Index: lib/Target/Mips/MipsDelaySlotFiller.cpp =================================================================== --- lib/Target/Mips/MipsDelaySlotFiller.cpp +++ lib/Target/Mips/MipsDelaySlotFiller.cpp @@ -213,7 +213,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } void getAnalysisUsage(AnalysisUsage &AU) const override { Index: lib/Target/Mips/MipsHazardSchedule.cpp =================================================================== --- lib/Target/Mips/MipsHazardSchedule.cpp +++ lib/Target/Mips/MipsHazardSchedule.cpp @@ -76,7 +76,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: Index: lib/Target/Mips/MipsLongBranch.cpp =================================================================== --- lib/Target/Mips/MipsLongBranch.cpp +++ lib/Target/Mips/MipsLongBranch.cpp @@ -74,7 +74,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: Index: lib/Target/PowerPC/PPCBranchSelector.cpp =================================================================== --- lib/Target/PowerPC/PPCBranchSelector.cpp +++ lib/Target/PowerPC/PPCBranchSelector.cpp @@ -48,7 +48,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { Index: lib/Target/PowerPC/PPCEarlyReturn.cpp =================================================================== --- lib/Target/PowerPC/PPCEarlyReturn.cpp +++ lib/Target/PowerPC/PPCEarlyReturn.cpp @@ -196,7 +196,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } void getAnalysisUsage(AnalysisUsage &AU) const override { Index: lib/Target/Sparc/DelaySlotFiller.cpp =================================================================== --- lib/Target/Sparc/DelaySlotFiller.cpp +++ lib/Target/Sparc/DelaySlotFiller.cpp @@ -64,7 +64,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } void insertCallDefsUses(MachineBasicBlock::iterator MI, Index: lib/Target/SystemZ/SystemZElimCompare.cpp =================================================================== --- lib/Target/SystemZ/SystemZElimCompare.cpp +++ lib/Target/SystemZ/SystemZElimCompare.cpp @@ -66,7 +66,7 @@ bool runOnMachineFunction(MachineFunction &F) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: Index: lib/Target/SystemZ/SystemZLongBranch.cpp =================================================================== --- lib/Target/SystemZ/SystemZLongBranch.cpp +++ lib/Target/SystemZ/SystemZLongBranch.cpp @@ -140,7 +140,7 @@ bool runOnMachineFunction(MachineFunction &F) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: Index: lib/Target/SystemZ/SystemZShortenInst.cpp =================================================================== --- lib/Target/SystemZ/SystemZShortenInst.cpp +++ lib/Target/SystemZ/SystemZShortenInst.cpp @@ -37,7 +37,7 @@ bool runOnMachineFunction(MachineFunction &F) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: Index: lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp =================================================================== --- lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp +++ lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp @@ -196,7 +196,7 @@ // Has no asserts of its own, but was not written to handle virtual regs. disablePass(&ShrinkWrapID); - // These functions all require the AllVRegsAllocated property. + // These functions all require the NoVRegs property. disablePass(&MachineCopyPropagationID); disablePass(&PostRASchedulerID); disablePass(&FuncletLayoutID); Index: lib/Target/X86/X86ExpandPseudo.cpp =================================================================== --- lib/Target/X86/X86ExpandPseudo.cpp +++ lib/Target/X86/X86ExpandPseudo.cpp @@ -51,7 +51,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { Index: lib/Target/X86/X86FixupBWInsts.cpp =================================================================== --- lib/Target/X86/X86FixupBWInsts.cpp +++ lib/Target/X86/X86FixupBWInsts.cpp @@ -125,7 +125,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: Index: lib/Target/X86/X86FixupLEAs.cpp =================================================================== --- lib/Target/X86/X86FixupLEAs.cpp +++ lib/Target/X86/X86FixupLEAs.cpp @@ -95,7 +95,7 @@ // This pass runs after regalloc and doesn't support VReg operands. MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } private: Index: lib/Target/X86/X86FloatingPoint.cpp =================================================================== --- lib/Target/X86/X86FloatingPoint.cpp +++ lib/Target/X86/X86FloatingPoint.cpp @@ -78,7 +78,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { return "X86 FP Stackifier"; } Index: lib/Target/X86/X86PadShortFunction.cpp =================================================================== --- lib/Target/X86/X86PadShortFunction.cpp +++ lib/Target/X86/X86PadShortFunction.cpp @@ -57,7 +57,7 @@ MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { Index: lib/Target/X86/X86VZeroUpper.cpp =================================================================== --- lib/Target/X86/X86VZeroUpper.cpp +++ lib/Target/X86/X86VZeroUpper.cpp @@ -40,7 +40,7 @@ bool runOnMachineFunction(MachineFunction &MF) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override {return "X86 vzeroupper inserter";} Index: lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp =================================================================== --- lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp +++ lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp @@ -29,7 +29,7 @@ bool runOnMachineFunction(MachineFunction &Fn) override; MachineFunctionProperties getRequiredProperties() const override { return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); + MachineFunctionProperties::Property::NoVRegs); } const char *getPassName() const override { Index: test/CodeGen/AArch64/ldst-opt-dbg-limit.mir =================================================================== --- test/CodeGen/AArch64/ldst-opt-dbg-limit.mir +++ test/CodeGen/AArch64/ldst-opt-dbg-limit.mir @@ -29,7 +29,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: true tracksRegLiveness: false tracksSubRegLiveness: false liveins: @@ -86,7 +85,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: true tracksRegLiveness: false tracksSubRegLiveness: false liveins: Index: test/CodeGen/AArch64/movimm-wzr.mir =================================================================== --- test/CodeGen/AArch64/movimm-wzr.mir +++ test/CodeGen/AArch64/movimm-wzr.mir @@ -16,7 +16,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: true tracksRegLiveness: false tracksSubRegLiveness: false frameInfo: Index: test/CodeGen/ARM/ARMLoadStoreDBG.mir =================================================================== --- test/CodeGen/ARM/ARMLoadStoreDBG.mir +++ test/CodeGen/ARM/ARMLoadStoreDBG.mir @@ -80,7 +80,6 @@ alignment: 1 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: true tracksRegLiveness: true tracksSubRegLiveness: false liveins: Index: test/CodeGen/Hexagon/ifcvt-impuse-livein.mir =================================================================== --- test/CodeGen/Hexagon/ifcvt-impuse-livein.mir +++ test/CodeGen/Hexagon/ifcvt-impuse-livein.mir @@ -14,7 +14,6 @@ --- name: foo tracksRegLiveness: true -allVRegsAllocated: true body: | bb.0: successors: %bb.1, %bb.2 Index: test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir =================================================================== --- test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir +++ test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir @@ -34,7 +34,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: true tracksRegLiveness: false tracksSubRegLiveness: false liveins: Index: test/CodeGen/MIR/AArch64/machine-dead-copy.mir =================================================================== --- test/CodeGen/MIR/AArch64/machine-dead-copy.mir +++ test/CodeGen/MIR/AArch64/machine-dead-copy.mir @@ -13,9 +13,8 @@ # CHECK-LABEL: name: copyprop1 # CHECK: bb.0: # CHECK-NOT: %w20 = COPY -name: copyprop1 -allVRegsAllocated: true -body: | +name: copyprop1 +body: | bb.0: liveins: %w0, %w1 %w20 = COPY %w1 @@ -28,9 +27,8 @@ # CHECK-LABEL: name: copyprop2 # CHECK: bb.0: # CHECK: %w20 = COPY -name: copyprop2 -allVRegsAllocated: true -body: | +name: copyprop2 +body: | bb.0: liveins: %w0, %w1 %w20 = COPY %w1 @@ -43,9 +41,8 @@ # CHECK-LABEL: name: copyprop3 # CHECK: bb.0: # CHECK-NOT: COPY -name: copyprop3 -allVRegsAllocated: true -body: | +name: copyprop3 +body: | bb.0: liveins: %w0, %w1 %w20 = COPY %w1 @@ -58,9 +55,8 @@ # CHECK-LABEL: name: copyprop4 # CHECK: bb.0: # CHECK-NOT: COPY -name: copyprop4 -allVRegsAllocated: true -body: | +name: copyprop4 +body: | bb.0: liveins: %w0, %w1 %w20 = COPY %w0 Index: test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir =================================================================== --- test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir +++ test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir @@ -91,7 +91,6 @@ alignment: 1 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: true tracksRegLiveness: true tracksSubRegLiveness: false liveins: Index: test/CodeGen/MIR/Hexagon/anti-dep-partial.mir =================================================================== --- test/CodeGen/MIR/Hexagon/anti-dep-partial.mir +++ test/CodeGen/MIR/Hexagon/anti-dep-partial.mir @@ -10,7 +10,6 @@ --- name: foo tracksRegLiveness: true -allVRegsAllocated: true body: | bb.0: successors: Index: test/CodeGen/MIR/Lanai/peephole-compare.mir =================================================================== --- test/CodeGen/MIR/Lanai/peephole-compare.mir +++ test/CodeGen/MIR/Lanai/peephole-compare.mir @@ -176,7 +176,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: false tracksRegLiveness: true tracksSubRegLiveness: false registers: @@ -223,7 +222,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: false tracksRegLiveness: true tracksSubRegLiveness: false registers: @@ -268,7 +266,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: false tracksRegLiveness: true tracksSubRegLiveness: false registers: @@ -317,7 +314,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: false tracksRegLiveness: true tracksSubRegLiveness: false registers: @@ -366,7 +362,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: false tracksRegLiveness: true tracksSubRegLiveness: false registers: @@ -415,7 +410,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: false tracksRegLiveness: true tracksSubRegLiveness: false registers: @@ -464,7 +458,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: false tracksRegLiveness: true tracksSubRegLiveness: false registers: @@ -513,7 +506,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: false tracksRegLiveness: true tracksSubRegLiveness: false registers: @@ -626,7 +618,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: false tracksRegLiveness: true tracksSubRegLiveness: false registers: Index: test/CodeGen/PowerPC/aantidep-def-ec.mir =================================================================== --- test/CodeGen/PowerPC/aantidep-def-ec.mir +++ test/CodeGen/PowerPC/aantidep-def-ec.mir @@ -45,7 +45,6 @@ alignment: 4 exposesReturnsTwice: false hasInlineAsm: true -allVRegsAllocated: true tracksRegLiveness: true tracksSubRegLiveness: false liveins: Index: test/CodeGen/PowerPC/addisdtprelha-nonr3.mir =================================================================== --- test/CodeGen/PowerPC/addisdtprelha-nonr3.mir +++ test/CodeGen/PowerPC/addisdtprelha-nonr3.mir @@ -27,7 +27,6 @@ alignment: 4 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: true tracksRegLiveness: true tracksSubRegLiveness: false frameInfo: Index: test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir =================================================================== --- test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir +++ test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir @@ -33,7 +33,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: false tracksRegLiveness: true tracksSubRegLiveness: false registers: Index: test/CodeGen/X86/eflags-copy-expansion.mir =================================================================== --- test/CodeGen/X86/eflags-copy-expansion.mir +++ test/CodeGen/X86/eflags-copy-expansion.mir @@ -19,7 +19,6 @@ --- name: foo -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } Index: test/CodeGen/X86/fixup-bw-copy.mir =================================================================== --- test/CodeGen/X86/fixup-bw-copy.mir +++ test/CodeGen/X86/fixup-bw-copy.mir @@ -38,7 +38,6 @@ --- name: test_movb_killed -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } @@ -54,7 +53,6 @@ --- name: test_movb_impuse -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } @@ -70,7 +68,6 @@ --- name: test_movb_impdef_gr64 -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } @@ -86,7 +83,6 @@ --- name: test_movb_impdef_gr32 -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } @@ -102,7 +98,6 @@ --- name: test_movb_impdef_gr16 -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } @@ -118,7 +113,6 @@ --- name: test_movw_impdef_gr32 -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } @@ -134,7 +128,6 @@ --- name: test_movw_impdef_gr64 -allVRegsAllocated: true tracksRegLiveness: true liveins: - { reg: '%edi' } Index: test/CodeGen/X86/implicit-null-checks.mir =================================================================== --- test/CodeGen/X86/implicit-null-checks.mir +++ test/CodeGen/X86/implicit-null-checks.mir @@ -85,7 +85,6 @@ name: imp_null_check_with_bitwise_op_0 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_0 alignment: 4 -allVRegsAllocated: true tracksRegLiveness: true tracksSubRegLiveness: false liveins: @@ -129,7 +128,6 @@ --- name: imp_null_check_with_bitwise_op_1 alignment: 4 -allVRegsAllocated: true tracksRegLiveness: true tracksSubRegLiveness: false liveins: @@ -178,7 +176,6 @@ name: imp_null_check_with_bitwise_op_2 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_2 alignment: 4 -allVRegsAllocated: true tracksRegLiveness: true tracksSubRegLiveness: false liveins: @@ -223,7 +220,6 @@ name: imp_null_check_with_bitwise_op_3 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_3 alignment: 4 -allVRegsAllocated: true tracksRegLiveness: true tracksSubRegLiveness: false liveins: Index: test/CodeGen/X86/machine-copy-prop.mir =================================================================== --- test/CodeGen/X86/machine-copy-prop.mir +++ test/CodeGen/X86/machine-copy-prop.mir @@ -25,7 +25,6 @@ # CHECK-NOT: COPY # CHECK-NEXT: NOOP implicit %rax, implicit %rdi name: copyprop_remove_kill0 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rdi @@ -43,7 +42,6 @@ # CHECK-NOT: COPY # CHECK-NEXT: NOOP implicit %rax, implicit %rdi name: copyprop_remove_kill1 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rdi @@ -61,7 +59,6 @@ # CHECK-NOT: COPY # CHECK-NEXT: NOOP implicit %rax, implicit %rdi name: copyprop_remove_kill2 -allVRegsAllocated: true body: | bb.0: %ax = COPY %di @@ -79,7 +76,6 @@ # CHECK-NOT: COPY # CHECK-NEXT: NOOP implicit %rax, implicit %rdi name: copyprop0 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rdi @@ -96,7 +92,6 @@ # CHECK-NEXT: NOOP implicit %rax # CHECK-NEXT: NOOP implicit %rax, implicit %rdi name: copyprop1 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rdi @@ -113,7 +108,6 @@ # CHECK-NOT: %rax = COPY %rdi # CHECK-NEXT: NOOP implicit %rax, implicit %rdi name: copyprop2 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rdi @@ -132,7 +126,6 @@ # CHECK-NEXT: %rbp = COPY %rax # CHECK-NEXT: NOOP implicit %rax, implicit %rbp name: nocopyprop0 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rbp @@ -150,7 +143,6 @@ # CHECK-NEXT: %rax = COPY %rbp # CHECK-NEXT: NOOP implicit %rax, implicit %rbp name: nocopyprop1 -allVRegsAllocated: true body: | bb.0: %rbp = COPY %rax @@ -168,7 +160,6 @@ # CHECK-NEXT: %rax = COPY %rbp # CHECK-NEXT: NOOP implicit %rax, implicit %rbp name: nocopyprop2 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rbp @@ -186,7 +177,6 @@ # CHECK-NEXT: %rbp = COPY %rax # CHECK-NEXT: NOOP implicit %rax, implicit %rbp name: nocopyprop3 -allVRegsAllocated: true body: | bb.0: %rbp = COPY %rax @@ -203,7 +193,6 @@ # CHECK-NEXT: %rax = COPY %rip # CHECK-NEXT: NOOP implicit %rax name: nocopyprop4 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rip @@ -219,7 +208,6 @@ # CHECK-NEXT: %rip = COPY %rax # CHECK-NEXT: %rip = COPY %rax name: nocopyprop5 -allVRegsAllocated: true body: | bb.0: %rip = COPY %rax Index: test/CodeGen/X86/pr27681.mir =================================================================== --- test/CodeGen/X86/pr27681.mir +++ test/CodeGen/X86/pr27681.mir @@ -11,7 +11,6 @@ --- # CHECK-LABEL: main name: main -allVRegsAllocated: true tracksRegLiveness: true frameInfo: stackSize: 52 Index: test/DebugInfo/MIR/X86/live-debug-values-3preds.mir =================================================================== --- test/DebugInfo/MIR/X86/live-debug-values-3preds.mir +++ test/DebugInfo/MIR/X86/live-debug-values-3preds.mir @@ -158,7 +158,6 @@ alignment: 4 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: true tracksRegLiveness: true tracksSubRegLiveness: false liveins: Index: test/DebugInfo/MIR/X86/live-debug-values.mir =================================================================== --- test/DebugInfo/MIR/X86/live-debug-values.mir +++ test/DebugInfo/MIR/X86/live-debug-values.mir @@ -160,7 +160,6 @@ alignment: 4 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: true tracksRegLiveness: true tracksSubRegLiveness: false liveins: