Index: lib/Target/Mips/MipsFastISel.cpp
===================================================================
--- lib/Target/Mips/MipsFastISel.cpp
+++ lib/Target/Mips/MipsFastISel.cpp
@@ -976,9 +976,13 @@
 bool MipsFastISel::selectSelect(const Instruction *I) {
   assert(isa<SelectInst>(I) && "Expected a select instruction.");
 
+  DEBUG(dbgs() << "selectSelect\n");
+
   MVT VT;
-  if (!isTypeSupported(I->getType(), VT))
+  if (!isTypeSupported(I->getType(), VT) || UnsupportedFPMode) {
+    DEBUG(dbgs() << ".. .. gave up (!isTypeSupported || UnsupportedFPMode)\n");
     return false;
+  }
 
   unsigned CondMovOpc;
   const TargetRegisterClass *RC;
@@ -1376,6 +1380,10 @@
       break;
 
     case MVT::f64:
+      if (UnsupportedFPMode) {
+        DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode\n");
+        return false;
+      }
       if (NextAFGR64 == AFGR64ArgRegs.end()) {
         DEBUG(dbgs() << ".. .. gave up (ran out of AFGR64 arguments)\n");
         return false;
@@ -1617,6 +1625,8 @@
   const Function &F = *I->getParent()->getParent();
   const ReturnInst *Ret = cast<ReturnInst>(I);
 
+  DEBUG(dbgs() << "selectRet\n");
+
   if (!FuncInfo.CanLowerReturn)
     return false;
 
@@ -1677,6 +1687,12 @@
     if (RVVT == MVT::f128)
       return false;
 
+    // Do not handle FGR64 returns for now.
+    if (RVVT == MVT::f64 && UnsupportedFPMode) {
+      DEBUG(dbgs() << ".. .. gave up (UnsupportedFPMode\n");
+      return false;
+    }
+
     MVT DestVT = VA.getValVT();
     // Special handling for extended integers.
     if (RVVT != DestVT) {
Index: test/CodeGen/Mips/Fast-ISel/double-arg.ll
===================================================================
--- /dev/null
+++ test/CodeGen/Mips/Fast-ISel/double-arg.ll
@@ -0,0 +1,16 @@
+; RUN: llc -march=mipsel -mcpu=mips32r2 -fast-isel -relocation-model=pic < %s \
+; RUN:     -fast-isel-abort=3 | FileCheck %s
+; RUN: not llc -march=mipsel -mcpu=mips32r6 -fast-isel -relocation-model=pic < %s \
+; RUN:     -fast-isel-abort=3 2>&1
+
+; Check that FastISel aborts when we have 64bit FPU registers. FastISel currently
+; supports AFGR64 only, which has uses paired 32 bit registers.
+
+define zeroext i1 @f(double %value) {
+entry:
+; CHECK-LABEL: f:
+; CHECK: sdc1
+  %value.addr = alloca double, align 8
+  store double %value, double* %value.addr, align 8
+  ret i1 false
+}