Index: CMakeLists.txt =================================================================== --- CMakeLists.txt +++ CMakeLists.txt @@ -273,6 +273,7 @@ MSP430 NVPTX PowerPC + RISCV Sparc SystemZ X86 Index: docs/CompilerWriterInfo.rst =================================================================== --- docs/CompilerWriterInfo.rst +++ docs/CompilerWriterInfo.rst @@ -81,6 +81,10 @@ * `AMD GPU Programming Guide `_ * `AMD Compute Resources `_ +RISC-V +------ +* `RISC-V User-Level ISA Specification `_ + SPARC ----- Index: lib/Target/LLVMBuild.txt =================================================================== --- lib/Target/LLVMBuild.txt +++ lib/Target/LLVMBuild.txt @@ -30,6 +30,7 @@ NVPTX Mips PowerPC + RISCV Sparc SystemZ WebAssembly Index: lib/Target/RISCV/CMakeLists.txt =================================================================== --- /dev/null +++ lib/Target/RISCV/CMakeLists.txt @@ -0,0 +1,5 @@ +add_llvm_target(RISCVCodeGen + RISCVTargetMachine.cpp + ) + +add_subdirectory(TargetInfo) Index: lib/Target/RISCV/LLVMBuild.txt =================================================================== --- /dev/null +++ lib/Target/RISCV/LLVMBuild.txt @@ -0,0 +1,31 @@ +;===- ./lib/Target/RISCV/LLVMBuild.txt -------------------------*- Conf -*--===; +; +; The LLVM Compiler Infrastructure +; +; This file is distributed under the University of Illinois Open Source +; License. See LICENSE.TXT for details. +; +;===------------------------------------------------------------------------===; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;===------------------------------------------------------------------------===; + +[common] +subdirectories = TargetInfo + +[component_0] +type = TargetGroup +name = RISCV +parent = Target + +[component_1] +type = Library +name = RISCVCodeGen +parent = RISCV +required_libraries = Core CodeGen RISCVInfo Support Target +add_to_library_groups = RISCV Index: lib/Target/RISCV/RISCVTargetMachine.h =================================================================== --- /dev/null +++ lib/Target/RISCV/RISCVTargetMachine.h @@ -0,0 +1,40 @@ +//===-- RISCVTargetMachine.h - Define TargetMachine for RISCV ---*- C++ -*-===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file declares the RISCV specific subclass of TargetMachine. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_RISCV_RISCVTARGETMACHINE_H +#define LLVM_LIB_TARGET_RISCV_RISCVTARGETMACHINE_H + +#include "llvm/CodeGen/SelectionDAGTargetInfo.h" +#include "llvm/Target/TargetMachine.h" +#include "llvm/IR/DataLayout.h" + +namespace llvm { +class RISCVTargetMachine : public LLVMTargetMachine { + std::unique_ptr TLOF; + +public: + RISCVTargetMachine(const Target &T, const Triple &TT, StringRef CPU, + StringRef FS, const TargetOptions &Options, + Optional RM, CodeModel::Model CM, + CodeGenOpt::Level OL); + + TargetPassConfig *createPassConfig(PassManagerBase &PM) override; + + TargetLoweringObjectFile *getObjFileLowering() const override { + return TLOF.get(); + } +}; +extern Target TheRISCV32Target, TheRISCV64Target; +} + +#endif Index: lib/Target/RISCV/RISCVTargetMachine.cpp =================================================================== --- /dev/null +++ lib/Target/RISCV/RISCVTargetMachine.cpp @@ -0,0 +1,56 @@ +//===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// Implements the info about RISCV target spec. +// +//===----------------------------------------------------------------------===// + +#include "RISCVTargetMachine.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" +#include "llvm/CodeGen/TargetPassConfig.h" +#include "llvm/IR/LegacyPassManager.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/Support/FormattedStream.h" +#include "llvm/Support/TargetRegistry.h" +#include "llvm/Target/TargetOptions.h" +using namespace llvm; + +extern "C" void LLVMInitializeRISCVTarget() { + RegisterTargetMachine X(TheRISCV32Target); + RegisterTargetMachine Y(TheRISCV64Target); +} + +static std::string computeDataLayout(const Triple &TT) { + if (TT.isArch64Bit()) + return "e-m:e-i64:64-n32:64-S128"; + else + return "e-m:e-i64:64-n32-S128"; +} + +static Reloc::Model getEffectiveRelocModel(const Triple &TT, + Optional RM) { + if (!RM.hasValue()) + return Reloc::Static; + return *RM; +} + +RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT, + StringRef CPU, StringRef FS, + const TargetOptions &Options, + Optional RM, + CodeModel::Model CM, + CodeGenOpt::Level OL) + : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options, + getEffectiveRelocModel(TT, RM), CM, OL), + TLOF(make_unique()) {} + +TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) { + return new TargetPassConfig(this, PM); +} Index: lib/Target/RISCV/TargetInfo/CMakeLists.txt =================================================================== --- /dev/null +++ lib/Target/RISCV/TargetInfo/CMakeLists.txt @@ -0,0 +1,3 @@ +add_llvm_library(LLVMRISCVInfo + RISCVTargetInfo.cpp + ) Index: lib/Target/RISCV/TargetInfo/LLVMBuild.txt =================================================================== --- /dev/null +++ lib/Target/RISCV/TargetInfo/LLVMBuild.txt @@ -0,0 +1,23 @@ +;===- ./lib/Target/RISCV/TargetInfo/LLVMBuild.txt --------------*- Conf -*--===; +; +; The LLVM Compiler Infrastructure +; +; This file is distributed under the University of Illinois Open Source +; License. See LICENSE.TXT for details. +; +;===------------------------------------------------------------------------===; +; +; This is an LLVMBuild description file for the components in this subdirectory. +; +; For more information on the LLVMBuild system, please see: +; +; http://llvm.org/docs/LLVMBuild.html +; +;===------------------------------------------------------------------------===; + +[component_0] +type = Library +name = RISCVInfo +parent = RISCV +required_libraries = Support +add_to_library_groups = RISCV Index: lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp =================================================================== --- /dev/null +++ lib/Target/RISCV/TargetInfo/RISCVTargetInfo.cpp @@ -0,0 +1,28 @@ +//===-- RISCVTargetInfo.cpp - RISCV Target Implementation -----------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// + +#include "llvm/Support/TargetRegistry.h" +using namespace llvm; + +namespace llvm { +Target TheRISCV32Target; +Target TheRISCV64Target; +} + +extern "C" void LLVMInitializeRISCVTargetInfo() { + RegisterTarget X(TheRISCV32Target, "riscv32", + "32-bit RISC-V"); + RegisterTarget Y(TheRISCV64Target, "riscv64", + "64-bit RISC-V"); +} + +// FIXME: Temporary stub - this function must be defined for linking +// to succeed and will be called unconditionally by llc, so must be a no-op. +// Remove once this function is properly implemented. +extern "C" void LLVMInitializeRISCVTargetMC() {}