Index: include/llvm/Object/ELFObjectFile.h =================================================================== --- include/llvm/Object/ELFObjectFile.h +++ include/llvm/Object/ELFObjectFile.h @@ -854,6 +854,8 @@ return "ELF32-mips"; case ELF::EM_PPC: return "ELF32-ppc"; + case ELF::EM_RISCV: + return "ELF32-riscv"; case ELF::EM_SPARC: case ELF::EM_SPARC32PLUS: return "ELF32-sparc"; @@ -874,6 +876,8 @@ return (IsLittleEndian ? "ELF64-aarch64-little" : "ELF64-aarch64-big"); case ELF::EM_PPC64: return "ELF64-ppc64"; + case ELF::EM_RISCV: + return "ELF64-riscv"; case ELF::EM_S390: return "ELF64-s390"; case ELF::EM_SPARCV9: @@ -929,6 +933,15 @@ return Triple::ppc; case ELF::EM_PPC64: return IsLittleEndian ? Triple::ppc64le : Triple::ppc64; + case ELF::EM_RISCV: + switch (EF.getHeader()->e_ident[ELF::EI_CLASS]) { + case ELF::ELFCLASS32: + return Triple::riscv32; + case ELF::ELFCLASS64: + return Triple::riscv64; + default: + report_fatal_error("Invalid ELFCLASS!"); + } case ELF::EM_S390: return Triple::systemz; Index: include/llvm/Support/ELF.h =================================================================== --- include/llvm/Support/ELF.h +++ include/llvm/Support/ELF.h @@ -310,6 +310,7 @@ EM_NORC = 218, // Nanoradio Optimized RISC EM_CSR_KALIMBA = 219, // CSR Kalimba architecture family EM_AMDGPU = 224, // AMD GPU architecture + EM_RISCV = 243, // RISC-V EM_LANAI = 244, // Lanai 32-bit processor EM_BPF = 247, // Linux kernel bpf virtual machine @@ -597,6 +598,11 @@ #include "ELFRelocs/Lanai.def" }; +// ELF Relocation types for RISC-V +enum { +#include "ELFRelocs/RISCV.def" +}; + // ELF Relocation types for S390/zSeries enum { #include "ELFRelocs/SystemZ.def" Index: include/llvm/Support/ELFRelocs/RISCV.def =================================================================== --- /dev/null +++ include/llvm/Support/ELFRelocs/RISCV.def @@ -0,0 +1,50 @@ + +#ifndef ELF_RELOC +#error "ELF_RELOC must be defined" +#endif + +ELF_RELOC(R_RISCV_NONE, 0) +ELF_RELOC(R_RISCV_32, 1) +ELF_RELOC(R_RISCV_64, 2) +ELF_RELOC(R_RISCV_RELATIVE, 3) +ELF_RELOC(R_RISCV_COPY, 4) +ELF_RELOC(R_RISCV_JUMP_SLOT, 5) +ELF_RELOC(R_RISCV_TLS_DTPMOD32, 6) +ELF_RELOC(R_RISCV_TLS_DTPMOD64, 7) +ELF_RELOC(R_RISCV_TLS_DTPREL32, 8) +ELF_RELOC(R_RISCV_TLS_DTPREL64, 9) +ELF_RELOC(R_RISCV_TLS_TPREL32, 10) +ELF_RELOC(R_RISCV_TLS_TPREL64, 11) +ELF_RELOC(R_RISCV_BRANCH, 16) +ELF_RELOC(R_RISCV_JAL, 17) +ELF_RELOC(R_RISCV_CALL, 18) +ELF_RELOC(R_RISCV_CALL_PLT, 19) +ELF_RELOC(R_RISCV_GOT_HI20, 20) +ELF_RELOC(R_RISCV_TLS_GOT_HI20, 21) +ELF_RELOC(R_RISCV_TLS_GD_HI20, 22) +ELF_RELOC(R_RISCV_PCREL_HI20, 23) +ELF_RELOC(R_RISCV_PCREL_LO12_I, 24) +ELF_RELOC(R_RISCV_PCREL_LO12_S, 25) +ELF_RELOC(R_RISCV_HI20, 26) +ELF_RELOC(R_RISCV_LO12_I, 27) +ELF_RELOC(R_RISCV_LO12_S, 28) +ELF_RELOC(R_RISCV_TPREL_HI20, 29) +ELF_RELOC(R_RISCV_TPREL_LO12_I, 30) +ELF_RELOC(R_RISCV_TPREL_LO12_S, 31) +ELF_RELOC(R_RISCV_TPREL_ADD, 32) +ELF_RELOC(R_RISCV_ADD8, 33) +ELF_RELOC(R_RISCV_ADD16, 34) +ELF_RELOC(R_RISCV_ADD32, 35) +ELF_RELOC(R_RISCV_ADD64, 36) +ELF_RELOC(R_RISCV_SUB8, 37) +ELF_RELOC(R_RISCV_SUB16, 38) +ELF_RELOC(R_RISCV_SUB32, 39) +ELF_RELOC(R_RISCV_SUB64, 40) +ELF_RELOC(R_RISCV_GNU_VTINHERIT, 41) +ELF_RELOC(R_RISCV_GNU_VTENTRY, 42) +ELF_RELOC(R_RISCV_ALIGN, 43) +ELF_RELOC(R_RISCV_RVC_BRANCH, 44) +ELF_RELOC(R_RISCV_RVC_JUMP, 45) +ELF_RELOC(R_RISCV_RVC_LUI, 46) +ELF_RELOC(R_RISCV_GPREL_I, 47) +ELF_RELOC(R_RISCV_GPREL_S, 48) Index: lib/Object/ELF.cpp =================================================================== --- lib/Object/ELF.cpp +++ lib/Object/ELF.cpp @@ -82,6 +82,13 @@ break; } break; + case ELF::EM_RISCV: + switch (Type) { +#include "llvm/Support/ELFRelocs/RISCV.def" + default: + break; + } + break; case ELF::EM_S390: switch (Type) { #include "llvm/Support/ELFRelocs/SystemZ.def" Index: lib/ObjectYAML/ELFYAML.cpp =================================================================== --- lib/ObjectYAML/ELFYAML.cpp +++ lib/ObjectYAML/ELFYAML.cpp @@ -194,6 +194,7 @@ ECase(EM_78KOR) ECase(EM_56800EX) ECase(EM_AMDGPU) + ECase(EM_RISCV) ECase(EM_LANAI) ECase(EM_BPF) #undef ECase @@ -529,6 +530,9 @@ case ELF::EM_ARM: #include "llvm/Support/ELFRelocs/ARM.def" break; + case ELF::EM_RISCV: +#include "llvm/Support/ELFRelocs/RISCV.def" + break; case ELF::EM_LANAI: #include "llvm/Support/ELFRelocs/Lanai.def" break; Index: tools/llvm-objdump/llvm-objdump.cpp =================================================================== --- tools/llvm-objdump/llvm-objdump.cpp +++ tools/llvm-objdump/llvm-objdump.cpp @@ -683,6 +683,7 @@ case ELF::EM_HEXAGON: case ELF::EM_MIPS: case ELF::EM_BPF: + case ELF::EM_RISCV: res = Target; break; case ELF::EM_WEBASSEMBLY: Index: tools/llvm-readobj/ELFDumper.cpp =================================================================== --- tools/llvm-readobj/ELFDumper.cpp +++ tools/llvm-readobj/ELFDumper.cpp @@ -954,6 +954,7 @@ ENUM_ENT(EM_78KOR, "EM_78KOR"), ENUM_ENT(EM_56800EX, "EM_56800EX"), ENUM_ENT(EM_AMDGPU, "EM_AMDGPU"), + ENUM_ENT(EM_RISCV, "RISC-V"), ENUM_ENT(EM_WEBASSEMBLY, "EM_WEBASSEMBLY"), ENUM_ENT(EM_LANAI, "EM_LANAI"), ENUM_ENT(EM_BPF, "EM_BPF"),