Index: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td =================================================================== --- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td +++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -789,7 +789,7 @@ class MTC2_MMR6_DESC : MTC2_MMR6_DESC_BASE<"mtc2", COP2Opnd, GPR32Opnd, II_MTC2>; class MTHC0_MMR6_DESC : MTC0_MMR6_DESC_BASE<"mthc0", COP0Opnd, GPR32Opnd, - II_MTC0>; + II_MTHC0>; class MTHC1_D32_MMR6_DESC : MTC1_64_MMR6_DESC_BASE<"mthc1", AFGR64Opnd, GPR32Opnd, II_MTC1>, HARDFLOAT, FGR_32; @@ -838,7 +838,7 @@ class MFC2_MMR6_DESC : MFC2_MMR6_DESC_BASE<"mfc2", GPR32Opnd, COP2Opnd, II_MFC2>; class MFHC0_MMR6_DESC : MFC0_MMR6_DESC_BASE<"mfhc0", GPR32Opnd, COP0Opnd, - II_MFC0>; + II_MFHC0>; class MFHC1_D32_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, AFGR64Opnd, II_MFHC1>, HARDFLOAT, FGR_32; class MFHC1_D64_MMR6_DESC : MFC1_MMR6_DESC_BASE<"mfhc1", GPR32Opnd, FGR64Opnd, Index: llvm/trunk/lib/Target/Mips/Mips.td =================================================================== --- llvm/trunk/lib/Target/Mips/Mips.td +++ llvm/trunk/lib/Target/Mips/Mips.td @@ -59,6 +59,7 @@ // Avoid forward declaration issues. include "MipsScheduleP5600.td" +include "MipsScheduleGeneric.td" def MipsInstrInfo : InstrInfo; @@ -191,7 +192,7 @@ "The P5600 Processor", [FeatureMips32r5]>; class Proc Features> - : Processor; + : ProcessorModel; def : Proc<"mips1", [FeatureMips1]>; def : Proc<"mips2", [FeatureMips2]>; Index: llvm/trunk/lib/Target/Mips/MipsSchedule.td =================================================================== --- llvm/trunk/lib/Target/Mips/MipsSchedule.td +++ llvm/trunk/lib/Target/Mips/MipsSchedule.td @@ -216,6 +216,7 @@ def II_MINA_D : InstrItinClass; def II_MINA_S : InstrItinClass; def II_MFC0 : InstrItinClass; +def II_MFHC0 : InstrItinClass; def II_MFC1 : InstrItinClass; def II_MFHC1 : InstrItinClass; def II_MFC2 : InstrItinClass; @@ -244,6 +245,7 @@ def II_MSUBF_D : InstrItinClass; def II_MSUBF_S : InstrItinClass; def II_MTC0 : InstrItinClass; +def II_MTHC0 : InstrItinClass; def II_MTC1 : InstrItinClass; def II_MTHC1 : InstrItinClass; def II_MTC2 : InstrItinClass; @@ -640,9 +642,11 @@ InstrItinData]>, InstrItinData]>, InstrItinData]>, + InstrItinData]>, InstrItinData]>, InstrItinData]>, InstrItinData]>, + InstrItinData]>, InstrItinData]>, InstrItinData]>, InstrItinData]>, Index: llvm/trunk/test/CodeGen/Mips/biggot.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/biggot.ll +++ llvm/trunk/test/CodeGen/Mips/biggot.ll @@ -15,12 +15,12 @@ ; O32: lw ${{[0-9]+}}, %call_lo(foo0)($[[R3]]) ; N64-LABEL: foo1: -; N64: lui $[[R0:[0-9]+]], %got_hi(v0) -; N64: daddu $[[R1:[0-9]+]], $[[R0]], ${{[a-z0-9]+}} -; N64: lui $[[R2:[0-9]+]], %call_hi(foo0) -; N64: daddu $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}} -; N64: ld ${{[0-9]+}}, %got_lo(v0)($[[R1]]) -; N64: ld ${{[0-9]+}}, %call_lo(foo0)($[[R3]]) +; N64-DAG: lui $[[R0:[0-9]+]], %got_hi(v0) +; N64-DAG: daddu $[[R1:[0-9]+]], $[[R0]], ${{[a-z0-9]+}} +; N64-DAG: lui $[[R2:[0-9]+]], %call_hi(foo0) +; N64-DAG: daddu $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}} +; N64-DAG: ld ${{[0-9]+}}, %got_lo(v0)($[[R1]]) +; N64-DAG: ld ${{[0-9]+}}, %call_lo(foo0)($[[R3]]) %0 = load i32, i32* @v0, align 4 tail call void @foo0(i32 %0) nounwind Index: llvm/trunk/test/CodeGen/Mips/divrem.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/divrem.ll +++ llvm/trunk/test/CodeGen/Mips/divrem.ll @@ -152,20 +152,20 @@ ; ACC64: mfhi $[[R0:[0-9]+]] ; ACC64: sw $[[R0]], 0(${{[0-9]+}}) -; GPR32-DAG: div $2, $4, $5 -; GPR32-TRAP: teq $5, $zero, 7 -; NOCHECK-NOT: teq ; GPR32-DAG: mod $[[R0:[0-9]+]], $4, $5 ; GPR32-TRAP: teq $5, $zero, 7 +; NOCHECK-NOT: teq ; GPR32: sw $[[R0]], 0(${{[0-9]+}}) +; GPR32-DAG: div $2, $4, $5 +; GPR32-TRAP: teq $5, $zero, 7 -; GPR64-DAG: div $2, $4, $5 -; GPR64-TRAP: teq $5, $zero, 7 -; NOCHECK-NOT: teq ; GPR64-DAG: mod $[[R0:[0-9]+]], $4, $5 ; GPR64-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq ; GPR64: sw $[[R0]], 0(${{[0-9]+}}) +; GPR64-DAG: div $2, $4, $5 +; GPR64-TRAP: teq $5, $zero, 7 +; NOCHECK-NOT: teq ; ALL: .end sdivrem1 @@ -193,21 +193,21 @@ ; ACC64: mfhi $[[R0:[0-9]+]] ; ACC64: sw $[[R0]], 0(${{[0-9]+}}) -; GPR32-DAG: divu $2, $4, $5 +; GPR32-DAG: modu $[[R0:[0-9]+]], $4, $5 ; GPR32-TRAP: teq $5, $zero, 7 +; GPR32: sw $[[R0]], 0(${{[0-9]+}}) ; NOCHECK-NOT: teq -; GPR32-DAG: modu $[[R0:[0-9]+]], $4, $5 +; GPR32-DAG: divu $2, $4, $5 ; GPR32-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq -; GPR32: sw $[[R0]], 0(${{[0-9]+}}) -; GPR64-DAG: divu $2, $4, $5 -; GPR64-TRAP: teq $5, $zero, 7 -; NOCHECK-NOT: teq ; GPR64-DAG: modu $[[R0:[0-9]+]], $4, $5 ; GPR64-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq ; GPR64: sw $[[R0]], 0(${{[0-9]+}}) +; GPR64-DAG: divu $2, $4, $5 +; GPR64-TRAP: teq $5, $zero, 7 +; NOCHECK-NOT: teq ; ALL: .end udivrem1 @@ -335,14 +335,14 @@ ; ACC64: mfhi $[[R0:[0-9]+]] ; ACC64: sd $[[R0]], 0(${{[0-9]+}}) -; GPR64-DAG: ddiv $2, $4, $5 +; GPR64-DAG: dmod $[[R0:[0-9]+]], $4, $5 ; GPR64-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq +; GPR64: sd $[[R0]], 0(${{[0-9]+}}) -; GPR64-DAG: dmod $[[R0:[0-9]+]], $4, $5 +; GPR64-DAG: ddiv $2, $4, $5 ; GPR64-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq -; GPR64: sd $[[R0]], 0(${{[0-9]+}}) ; ALL: .end sdivrem2 @@ -370,14 +370,14 @@ ; ACC64: mfhi $[[R0:[0-9]+]] ; ACC64: sd $[[R0]], 0(${{[0-9]+}}) -; GPR64-DAG: ddivu $2, $4, $5 +; GPR64: dmodu $[[R0:[0-9]+]], $4, $5 ; GPR64-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq +; GPR64: sd $[[R0]], 0(${{[0-9]+}}) -; GPR64: dmodu $[[R0:[0-9]+]], $4, $5 +; GPR64-DAG: ddivu $2, $4, $5 ; GPR64-TRAP: teq $5, $zero, 7 ; NOCHECK-NOT: teq -; GPR64: sd $[[R0]], 0(${{[0-9]+}}) ; ALL: .end udivrem2 Index: llvm/trunk/test/CodeGen/Mips/fcopysign-f32-f64.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/fcopysign-f32-f64.ll +++ llvm/trunk/test/CodeGen/Mips/fcopysign-f32-f64.ll @@ -36,14 +36,14 @@ entry: ; ALL-LABEL: func3: -; 64-DAG: mfc1 $[[MFC:[0-9]+]], $f13 -; 64-DAG: srl $[[SRL:[0-9]+]], $[[MFC:[0-9]+]], 31 -; 64: dsll $[[DSLL:[0-9]+]], $[[SRL]], 63 -; 64-DAG: daddiu $[[R1:[0-9]+]], $zero, 1 -; 64-DAG: dsll $[[R2:[0-9]+]], $[[R1]], 63 -; 64-DAG: daddiu $[[R3:[0-9]+]], $[[R2]], -1 -; 64-DAG: dmfc1 $[[R0:[0-9]+]], ${{.*}} +; 64: dmfc1 $[[R0:[0-9]+]], ${{.*}} +; 64: daddiu $[[R1:[0-9]+]], $zero, 1 +; 64: dsll $[[R2:[0-9]+]], $[[R1]], 63 +; 64: daddiu $[[R3:[0-9]+]], $[[R2]], -1 ; 64: and $[[AND0:[0-9]+]], $[[R0]], $[[R3]] +; 64: mfc1 $[[MFC:[0-9]+]], $f13 +; 64: srl $[[SRL:[0-9]+]], $[[MFC:[0-9]+]], 31 +; 64: dsll $[[DSLL:[0-9]+]], $[[SRL]], 63 ; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]] ; 64: dmtc1 $[[OR]], $f0 Index: llvm/trunk/test/CodeGen/Mips/llvm-ir/add.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/llvm-ir/add.ll +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/add.ll @@ -132,13 +132,13 @@ ; GP32: lw $[[T3:[0-9]+]], 24($sp) ; GP32: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]] ; GP32: addu $[[T5:[0-9]+]], $6, $[[T4]] - ; GP32: lw $[[T6:[0-9]+]], 16($sp) + ; GP32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]] ; GP32: lw $[[T7:[0-9]+]], 20($sp) - ; GP32: sltu $[[T8:[0-9]+]], $[[T5]], $[[T3]] - ; GP32: addu $[[T9:[0-9]+]], $[[T8]], $[[T7]] + ; GP32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]] + ; GP32: lw $[[T9:[0-9]+]], 16($sp) ; GP32: addu $3, $5, $[[T8]] ; GP32: sltu $[[T10:[0-9]+]], $3, $[[T7]] - ; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T6]] + ; GP32: addu $[[T11:[0-9]+]], $[[T10]], $[[T9]] ; GP32: addu $2, $4, $[[T11]] ; GP32: move $4, $[[T5]] ; GP32: move $5, $[[T1]] @@ -154,13 +154,13 @@ ; MM32: lw $[[T3:[0-9]+]], 24($sp) ; MM32: addu $[[T4:[0-9]+]], $[[T2]], $[[T3]] ; MM32: addu $[[T5:[0-9]+]], $6, $[[T4]] - ; MM32: lw $[[T6:[0-9]+]], 16($sp) + ; MM32: sltu $[[T6:[0-9]+]], $[[T5]], $[[T3]] ; MM32: lw $[[T7:[0-9]+]], 20($sp) - ; MM32: sltu $[[T8:[0-9]+]], $[[T5]], $[[T3]] - ; MM32: addu $[[T9:[0-9]+]], $[[T8]], $[[T7]] - ; MM32: addu $[[T10:[0-9]+]], $5, $[[T9]] - ; MM32: sltu $[[T11:[0-6]+]], $[[T9]], $[[T7]] - ; MM32: addu $[[T12:[0-6]+]], $[[T11]], $[[T6]] + ; MM32: addu $[[T8:[0-9]+]], $[[T6]], $[[T7]] + ; MM32: lw $[[T9:[0-9]+]], 16($sp) + ; MM32: addu $[[T10:[0-9]+]], $5, $[[T8]] + ; MM32: sltu $[[T11:[0-9]+]], $[[T10]], $[[T7]] + ; MM32: addu $[[T12:[0-9]+]], $[[T11]], $[[T9]] ; MM32: addu $[[T13:[0-9]+]], $4, $[[T12]] ; MM32: move $4, $[[T5]] ; MM32: move $5, $[[T1]] Index: llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/and.ll @@ -119,25 +119,25 @@ entry: ; ALL-LABEL: and_i128: - ; GP32: lw $[[T0:[0-9]+]], 24($sp) - ; GP32: lw $[[T1:[0-9]+]], 20($sp) - ; GP32: lw $[[T2:[0-9]+]], 16($sp) - ; GP32: and $2, $4, $[[T2]] - ; GP32: and $3, $5, $[[T1]] - ; GP32: and $4, $6, $[[T0]] + ; GP32: lw $[[T0:[0-9]+]], 20($sp) + ; GP32: lw $[[T1:[0-9]+]], 16($sp) + ; GP32: and $2, $4, $[[T1]] + ; GP32: and $3, $5, $[[T0]] + ; GP32: lw $[[T2:[0-9]+]], 24($sp) + ; GP32: and $4, $6, $[[T2]] ; GP32: lw $[[T3:[0-9]+]], 28($sp) ; GP32: and $5, $7, $[[T3]] ; GP64: and $2, $4, $6 ; GP64: and $3, $5, $7 - ; MM32: lw $[[T0:[0-9]+]], 32($sp) - ; MM32: lw $[[T1:[0-9]+]], 28($sp) + ; MM32: lw $[[T0:[0-9]+]], 20($sp) + ; MM32: lw $[[T1:[0-9]+]], 16($sp) + ; MM32: and16 $[[T1]], $4 + ; MM32: and16 $[[T0]], $5 ; MM32: lw $[[T2:[0-9]+]], 24($sp) - ; MM32: and16 $[[T2]], $4 - ; MM32: and16 $[[T1]], $5 - ; MM32: and16 $[[T0]], $6 - ; MM32: lw $[[T3:[0-9]+]], 36($sp) + ; MM32: and16 $[[T2]], $6 + ; MM32: lw $[[T3:[0-9]+]], 28($sp) ; MM32: and16 $[[T3]], $7 ; MM64: and $2, $4, $6 Index: llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll @@ -185,17 +185,17 @@ ; 32R1-R5: multu $5, $7 ; 32R1-R5: mflo $3 ; 32R1-R5: mfhi $[[T0:[0-9]+]] - ; 32R1-R5: mul $[[T1:[0-9]+]], $4, $7 - ; 32R1-R5: mul $[[T2:[0-9]+]], $5, $6 - ; 32R1-R5: addu $[[T0]], $[[T0]], $[[T2:[0-9]+]] - ; 32R1-R5: addu $2, $[[T0]], $[[T1]] - + ; 32R1-R5: mul $[[T1:[0-9]+]], $5, $6 + ; 32R1-R5: addu $[[T0]], $[[T0]], $[[T1:[0-9]+]] + ; 32R1-R5: mul $[[T2:[0-9]+]], $4, $7 + ; 32R1-R5: addu $2, $[[T0]], $[[T2]] + + ; 32R6-DAG: mul $[[T0:[0-9]+]], $5, $6 + ; 32R6: muhu $[[T1:[0-9]+]], $5, $7 + ; 32R6: addu $[[T0]], $[[T1]], $[[T0]] + ; 32R6-DAG: mul $[[T2:[0-9]+]], $4, $7 + ; 32R6: addu $2, $[[T0]], $[[T2]] ; 32R6-DAG: mul $3, $5, $7 - ; 32R6-DAG: mul $[[T0:[0-9]+]], $4, $7 - ; 32R6-DAG: mul $[[T1:[0-9]+]], $5, $6 - ; 32R6: muhu $[[T2:[0-9]+]], $5, $7 - ; 32R6: addu $[[T1]], $[[T2]], $[[T1]] - ; 32R6: addu $2, $[[T1]], $[[T0]] ; M4: dmult $4, $5 ; M4: mflo $2 @@ -208,17 +208,17 @@ ; MM32R3: multu $[[T0:[0-9]+]], $7 ; MM32R3: mflo $[[T1:[0-9]+]] ; MM32R3: mfhi $[[T2:[0-9]+]] - ; MM32R3: mul $[[T3:[0-9]+]], $4, $7 ; MM32R3: mul $[[T0]], $[[T0]], $6 - ; MM32R3: addu16 $[[T2]], $[[T2]], $[[T0]] - ; MM32R3: addu16 $2, $[[T2]], $[[T3]] + ; MM32R3: addu16 $2, $[[T2]], $[[T0]] + ; MM32R3: mul $[[T3:[0-9]+]], $4, $7 + ; MM32R3: addu16 $[[T2]], $[[T2]], $[[T3]] - ; MM32R6: mul $[[T0:[0-9]+]], $5, $7 - ; MM32R6: mul $[[T1:[0-9]+]], $4, $7 - ; MM32R6: mul $[[T2:[0-9]+]], $5, $6 - ; MM32R6: muhu $[[T3:[0-9]+]], $5, $7 - ; MM32R6: addu16 $[[T2]], $[[T3]], $[[T2]] - ; MM32R6: addu16 $2, $[[T2]], $[[T1]] + ; MM32R6: mul $[[T0:[0-9]+]], $5, $6 + ; MM32R6: muhu $[[T1:[0-9]+]], $5, $7 + ; MM32R6: addu16 $[[T2:[0-9]+]], $[[T1]], $[[T0]] + ; MM32R6: mul $[[T3:[0-9]+]], $4, $7 + ; MM32R6: addu16 $2, $[[T2]], $[[T3]] + ; MM32R6: mul $[[T1]], $5, $7 %r = mul i64 %a, %b ret i64 %r @@ -240,12 +240,12 @@ ; GP64-NOT-R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]] ; GP64-NOT-R6: daddu $2, $[[T3:[0-9]+]], $[[T0]] - ; 64R6-DAG: dmul $3, $5, $7 - ; 64R6-DAG: dmul $[[T0:[0-9]+]], $4, $7 ; 64R6-DAG: dmul $[[T1:[0-9]+]], $5, $6 ; 64R6: dmuhu $[[T2:[0-9]+]], $5, $7 ; 64R6: daddu $[[T3:[0-9]+]], $[[T2]], $[[T1]] + ; 64R6-DAG: dmul $[[T0:[0-9]+]], $4, $7 ; 64R6: daddu $2, $[[T1]], $[[T0]] + ; 64R6-DAG: dmul $3, $5, $7 ; MM32: lw $25, %call16(__multi3)($16) Index: llvm/trunk/test/CodeGen/Mips/llvm-ir/not.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/llvm-ir/not.ll +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/not.ll @@ -209,11 +209,11 @@ entry: ; ALL-LABEL: nor_i128: - ; GP32: lw $[[T0:[0-9]+]], 24($sp) ; GP32: lw $[[T1:[0-9]+]], 20($sp) ; GP32: lw $[[T2:[0-9]+]], 16($sp) ; GP32: nor $2, $[[T2]], $4 ; GP32: nor $3, $[[T1]], $5 + ; GP32: lw $[[T0:[0-9]+]], 24($sp) ; GP32: nor $4, $[[T0]], $6 ; GP32: lw $[[T3:[0-9]+]], 28($sp) ; GP32: nor $5, $[[T3]], $7 @@ -221,11 +221,11 @@ ; GP64: nor $2, $6, $4 ; GP64: nor $3, $7, $5 - ; MM32: lw $[[T0:[0-9]+]], 24($sp) ; MM32: lw $[[T1:[0-9]+]], 20($sp) ; MM32: lw $[[T2:[0-9]+]], 16($sp) ; MM32: nor $2, $[[T2]], $4 ; MM32: nor $3, $[[T1]], $5 + ; MM32: lw $[[T0:[0-9]+]], 24($sp) ; MM32: nor $4, $[[T0]], $6 ; MM32: lw $[[T3:[0-9]+]], 28($sp) ; MM32: nor $5, $[[T3]], $7 Index: llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/or.ll @@ -107,11 +107,11 @@ entry: ; ALL-LABEL: or_i128: - ; GP32: lw $[[T0:[0-9]+]], 24($sp) ; GP32: lw $[[T1:[0-9]+]], 20($sp) ; GP32: lw $[[T2:[0-9]+]], 16($sp) ; GP32: or $2, $4, $[[T2]] ; GP32: or $3, $5, $[[T1]] + ; GP32: lw $[[T0:[0-9]+]], 24($sp) ; GP32: or $4, $6, $[[T0]] ; GP32: lw $[[T3:[0-9]+]], 28($sp) ; GP32: or $5, $7, $[[T3]] @@ -119,13 +119,13 @@ ; GP64: or $2, $4, $6 ; GP64: or $3, $5, $7 - ; MM32: lw $[[T0:[0-9]+]], 32($sp) - ; MM32: lw $[[T1:[0-9]+]], 28($sp) - ; MM32: lw $[[T2:[0-9]+]], 24($sp) + ; MM32: lw $[[T1:[0-9]+]], 20($sp) + ; MM32: lw $[[T2:[0-9]+]], 16($sp) ; MM32: or16 $[[T2]], $4 ; MM32: or16 $[[T1]], $5 + ; MM32: lw $[[T0:[0-9]+]], 24($sp) ; MM32: or16 $[[T0]], $6 - ; MM32: lw $[[T3:[0-9]+]], 36($sp) + ; MM32: lw $[[T3:[0-9]+]], 28($sp) ; MM32: or16 $[[T3]], $7 ; MM64: or $2, $4, $6 Index: llvm/trunk/test/CodeGen/Mips/llvm-ir/select-flt.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/llvm-ir/select-flt.ll +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/select-flt.ll @@ -46,8 +46,8 @@ ; M3: mov.s $f0, $f13 ; CMOV-32: mtc1 $6, $f0 - ; CMOV-32: mtc1 $5, $f1 ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1 + ; CMOV-32: mtc1 $5, $f1 ; CMOV-32: movn.s $f0, $f1, $[[T0]] ; SEL-32: mtc1 $5, $[[F0:f[0-9]+]] @@ -63,8 +63,8 @@ ; SEL-64: sel.s $f0, $f14, $f13 ; MM32R3: mtc1 $6, $[[F0:f[0-9]+]] - ; MM32R3: mtc1 $5, $[[F1:f[0-9]+]] ; MM32R3: andi16 $[[T0:[0-9]+]], $4, 1 + ; MM32R3: mtc1 $5, $[[F1:f[0-9]+]] ; MM32R3: movn.s $f0, $[[F1]], $[[T0]] %r = select i1 %s, float %x, float %y Index: llvm/trunk/test/CodeGen/Mips/llvm-ir/select-int.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/llvm-ir/select-int.ll +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/select-int.ll @@ -163,14 +163,14 @@ ; CMOV-32: movn $3, $7, $[[T0]] ; SEL-32: andi $[[T0:[0-9]+]], $4, 1 - ; SEL-32: selnez $[[T1:[0-9]+]], $6, $[[T0]] - ; SEL-32: lw $[[T2:[0-9]+]], 16($sp) - ; SEL-32: seleqz $[[T3:[0-9]+]], $[[T2]], $[[T0]] - ; SEL-32: or $2, $[[T1]], $[[T3]] - ; SEL-32: selnez $[[T4:[0-9]+]], $7, $[[T0]] - ; SEL-32: lw $[[T5:[0-9]+]], 20($sp) - ; SEL-32: seleqz $[[T6:[0-9]+]], $[[T5]], $[[T0]] - ; SEL-32: or $3, $[[T4]], $[[T6]] + ; SEL-32: lw $[[T1:[0-9]+]], 16($sp) + ; SEL-32: seleqz $[[T2:[0-9]+]], $[[T1]], $[[T0]] + ; SEL-32: selnez $[[T3:[0-9]+]], $6, $[[T0]] + ; SEL-32: or $2, $[[T3]], $[[T2]] + ; SEL-32: lw $[[T4:[0-9]+]], 20($sp) + ; SEL-32: seleqz $[[T5:[0-9]+]], $[[T4]], $[[T0]] + ; SEL-32: selnez $[[T6:[0-9]+]], $7, $[[T0]] + ; SEL-32: or $3, $[[T6]], $[[T5]] ; M3: andi $[[T0:[0-9]+]], $4, 1 ; M3: bnez $[[T0]], [[BB0:\.LBB[0-9_]+]] @@ -198,13 +198,13 @@ ; MM32R3: movn $3, $7, $[[T0]] ; MM32R6: andi16 $[[T0:[0-9]+]], $4, 1 - ; MM32R6: selnez $[[T1:[0-9]+]], $6, $[[T0]] ; MM32R6: lw $[[T2:[0-9]+]], 16($sp) ; MM32R6: seleqz $[[T3:[0-9]+]], $[[T2]], $[[T0]] + ; MM32R6: selnez $[[T1:[0-9]+]], $6, $[[T0]] ; MM32R6: or $2, $[[T1]], $[[T3]] - ; MM32R6: selnez $[[T6:[0-9]+]], $7, $[[T0]] ; MM32R6: lw $[[T4:[0-9]+]], 20($sp) ; MM32R6: seleqz $[[T5:[0-9]+]], $[[T4]], $[[T0]] + ; MM32R6: selnez $[[T6:[0-9]+]], $7, $[[T0]] ; MM32R6: or $3, $[[T6]], $[[T5]] %r = select i1 %s, i64 %x, i64 %y Index: llvm/trunk/test/CodeGen/Mips/llvm-ir/sub.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/llvm-ir/sub.ll +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/sub.ll @@ -134,16 +134,16 @@ ; GP32-MM: sltu $[[T1:[0-9]+]], $[[T2:[0-9]+]], $[[T0]] ; GP32-MM: lw $[[T3:[0-9]+]], 16($sp) ; GP32-MM: addu $[[T3]], $[[T1]], $[[T3]] - ; GP32-MM: lw $[[T5:[0-9]+]], 24($sp) - ; GP32-MM: lw $[[T4:[0-9]+]], 28($sp) - ; GP32-MM: subu $[[T1]], $7, $[[T4]] - ; GP32-MM: subu $[[T3]], $4, $[[T3]] - ; GP32-MM: sltu $[[T6:[0-9]+]], $6, $[[T5]] + ; GP32-MM: lw $[[T4:[0-9]+]], 24($sp) + ; GP32-MM: lw $[[T5:[0-9]+]], 28($sp) + ; GP32-MM: subu $[[T1]], $7, $[[T5]] + ; GP32-MM: subu $[[T3]], $[[T6:[0-9]+]], $[[T3]] + ; GP32-MM: sltu $[[T6]], $6, $[[T4]] ; GP32-MM: addu $[[T0]], $[[T6]], $[[T0]] ; GP32-MM: subu $[[T0]], $5, $[[T0]] - ; GP32-MM: sltu $[[T7:[0-9]+]], $7, $[[T4]] - ; GP32-MM: addu $[[T8:[0-8]+]], $[[T7]], $[[T5]] - ; GP32-MM: subu $[[T9:[0-9]+]], $6, $[[T8]] + ; GP32-MM: sltu $[[T6]], $7, $[[T5]] + ; GP32-MM: addu $[[T6]], $[[T6]], $[[T4]] + ; GP32-MM: subu $[[T6]], $6, $[[T6]] ; GP32-MM: move $[[T2]], $[[T1]] ; GP64: dsubu $3, $5, $7 Index: llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll +++ llvm/trunk/test/CodeGen/Mips/llvm-ir/xor.ll @@ -117,11 +117,11 @@ entry: ; ALL-LABEL: xor_i128: - ; GP32: lw $[[T0:[0-9]+]], 24($sp) ; GP32: lw $[[T1:[0-9]+]], 20($sp) ; GP32: lw $[[T2:[0-9]+]], 16($sp) ; GP32: xor $2, $4, $[[T2]] ; GP32: xor $3, $5, $[[T1]] + ; GP32: lw $[[T0:[0-9]+]], 24($sp) ; GP32: xor $4, $6, $[[T0]] ; GP32: lw $[[T3:[0-9]+]], 28($sp) ; GP32: xor $5, $7, $[[T3]] @@ -129,13 +129,13 @@ ; GP64: xor $2, $4, $6 ; GP64: xor $3, $5, $7 - ; MM32: lw $[[T0:[0-9]+]], 32($sp) - ; MM32: lw $[[T1:[0-9]+]], 28($sp) - ; MM32: lw $[[T2:[0-9]+]], 24($sp) + ; MM32: lw $[[T1:[0-9]+]], 20($sp) + ; MM32: lw $[[T2:[0-9]+]], 16($sp) ; MM32: xor16 $[[T2]], $4 ; MM32: xor16 $[[T1]], $5 + ; MM32: lw $[[T0:[0-9]+]], 24($sp) ; MM32: xor16 $[[T0]], $6 - ; MM32: lw $[[T3:[0-9]+]], 36($sp) + ; MM32: lw $[[T3:[0-9]+]], 28($sp) ; MM32: xor16 $[[T3]], $7 ; MM64: xor $2, $4, $6 Index: llvm/trunk/test/CodeGen/Mips/longbranch.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/longbranch.ll +++ llvm/trunk/test/CodeGen/Mips/longbranch.ll @@ -102,8 +102,8 @@ ; N64: [[BB0]]: ; N64: daddiu $[[GP:[0-9]+]], $[[R1]], %lo(%neg(%gp_rel(test1))) -; N64: ld $[[R2:[0-9]+]], %got_disp(x)($[[GP]]) ; N64: addiu $[[R3:[0-9]+]], $zero, 1 +; N64: ld $[[R2:[0-9]+]], %got_disp(x)($[[GP]]) ; N64: sw $[[R3]], 0($[[R2]]) ; N64: [[BB2]]: ; N64: jr $ra Index: llvm/trunk/test/CodeGen/Mips/no-odd-spreg.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/no-odd-spreg.ll +++ llvm/trunk/test/CodeGen/Mips/no-odd-spreg.ll @@ -19,6 +19,9 @@ ; ; On the other hand, if odd single precision registers are not permitted, it ; will be forced to spill/reload either %a or %0. + ; + ; This is affected by scheduling as the new machine scheduler schedules the + ; two adds together, avoiding the spill+reload. %0 = fadd float %a, 1.0 call void asm "# Clobber", "~{$f0},~{$f1},~{$f2},~{$f3},~{$f4},~{$f5},~{$f6},~{$f7},~{$f8},~{$f9},~{$f10},~{$f11},~{$f14},~{$f15},~{$f16},~{$f17},~{$f18},~{$f19},~{$f20},~{$f21},~{$f22},~{$f23},~{$f24},~{$f25},~{$f26},~{$f27},~{$f28},~{$f29},~{$f30},~{$f31}"() @@ -27,15 +30,15 @@ } ; ALL-LABEL: two_floats: -; ODDSPREG: add.s $f13, $f12, ${{f[0-9]+}} +; ODDSPREG: add.s $f[[RES:[0-9]]], $f12, ${{f[0-9]+}} +; ODDSPREG: add.s ${{f[0-9]+}}, $f12, $f[[RES]] ; ODDSPREG-NOT: swc1 ; ODDSPREG-NOT: lwc1 -; ODDSPREG: add.s $f0, $f12, $f13 ; NOODDSPREG: add.s $[[T0:f[0-9]*[02468]]], $f12, ${{f[0-9]+}} -; NOODDSPREG: swc1 $[[T0]], -; NOODDSPREG: lwc1 $[[T1:f[0-9]*[02468]]], -; NOODDSPREG: add.s $f0, $f12, $[[T1]] +; NOODDSPREG-NOT: swc1 $[[T0]], +; NOODDSPREG-NOT: lwc1 $[[T1:f[0-9]*[02468]]], +; NOODDSPREG: add.s ${{f[0-9]+}}, $f12, $[[T0]] define double @two_doubles(double %a) { entry: @@ -51,8 +54,8 @@ } ; ALL-LABEL: two_doubles: -; ALL: add.d $[[T0:f[0-9]+]], $f12, ${{f[0-9]+}} -; ALL: add.d $f0, $f12, $[[T0]] +; ALL-DAG: add.d $[[T0:f[0-9]+]], $f12, ${{f[0-9]+}} +; ALL-DAG: add.d $f0, $f12, $[[T0]] ; INVALID: -mattr=+nooddspreg is not currently permitted for a 32-bit FPU register file (FR=0 mode). Index: llvm/trunk/test/CodeGen/Mips/prevent-hoisting.ll =================================================================== --- llvm/trunk/test/CodeGen/Mips/prevent-hoisting.ll +++ llvm/trunk/test/CodeGen/Mips/prevent-hoisting.ll @@ -13,17 +13,17 @@ ; The check for first "addiu" instruction is added so that we can match the correct "b" instruction. ; CHECK: andi ; CHECK: b $[[BB0:BB[0-9_]+]] -; CHECK-NEXT: sll +; CHECK: sll ; Check that at the start of a fallthrough block there is a instruction that writes to $1. -; CHECK-NEXT: {{BB[0-9_#]+}}: -; CHECK-NEXT: lw $[[R1:[0-9]+]], %got(assignSE2partition)($[[R2:[0-9]+]]) -; CHECK-NEXT: sll $1, $[[R0:[0-9]+]], 4 +; CHECK: {{BB[0-9_#]+}}: +; CHECK: sll $1, $[[R0:[0-9]+]], 4 +; CHECK: lw $[[R1:[0-9]+]], %got(assignSE2partition)($[[R2:[0-9]+]]) ; Check that identical instructions are at the start of a target block. ; CHECK: [[BB0]]: -; CHECK-NEXT: lw $[[R1]], %got(assignSE2partition)($[[R2]]) -; CHECK-NEXT: sll $1, $[[R0]], 4 +; CHECK: sll $1, $[[R0]], 4 +; CHECK: lw $[[R1]], %got(assignSE2partition)($[[R2]]) %struct.img_par = type { i32, i32, i32, i32, i32*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [16 x [16 x i16]], [6 x [32 x i32]], [16 x [16 x i32]], [4 x [12 x [4 x [4 x i32]]]], [16 x i32], i8**, i32*, i32***, i32**, i32, i32, i32, i32, %struct.Slice*, %struct.macroblock*, i32, i32, i32, i32, i32, i32, %struct.DecRefPicMarking_s*, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x i32], i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32***, i32***, i32****, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, [3 x [2 x i32]], [3 x [2 x i32]], i32, i32, i32, i32, %struct.timeb, %struct.timeb, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } Index: llvm/trunk/test/DebugInfo/Mips/dsr-fixed-objects.ll =================================================================== --- llvm/trunk/test/DebugInfo/Mips/dsr-fixed-objects.ll +++ llvm/trunk/test/DebugInfo/Mips/dsr-fixed-objects.ll @@ -29,7 +29,7 @@ ; ; x -> DW_OP_reg1(51) ; F0: [[LOC]]: Beginning address offset: 0x0000000000000028 -; F0: Ending address offset: 0x0000000000000030 +; F0: Ending address offset: 0x000000000000002c ; F0: Location description: 51 define i32 @f0(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d, i32 signext %e) !dbg !4 { @@ -65,7 +65,7 @@ ; x -> DW_OP_reg1(51) ; F1: [[LOC]]: Beginning address offset: 0x0000000000000080 -; F1: Ending address offset: 0x0000000000000088 +; F1: Ending address offset: 0x0000000000000084 ; F1: Location description: 51 define i32 @f1(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d, i32 signext %e) !dbg !15 {