Index: llvm/trunk/include/llvm/MC/MCParser/MCTargetAsmParser.h =================================================================== --- llvm/trunk/include/llvm/MC/MCParser/MCTargetAsmParser.h +++ llvm/trunk/include/llvm/MC/MCParser/MCTargetAsmParser.h @@ -82,6 +82,12 @@ : AsmRewrites(rewrites) {} }; +enum OperandMatchResultTy { + MatchOperand_Success, // operand matched successfully + MatchOperand_NoMatch, // operand did not match + MatchOperand_ParseFail // operand matched but had errors +}; + /// MCTargetAsmParser - Generic interface to target specific assembly parsers. class MCTargetAsmParser : public MCAsmParserExtension { public: Index: llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp =================================================================== --- llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp +++ llvm/trunk/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp @@ -2026,7 +2026,7 @@ } /// tryParseSysCROperand - Try to parse a system instruction CR operand name. -AArch64AsmParser::OperandMatchResultTy +OperandMatchResultTy AArch64AsmParser::tryParseSysCROperand(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = getLoc(); @@ -2056,7 +2056,7 @@ } /// tryParsePrefetch - Try to parse a prefetch operand. -AArch64AsmParser::OperandMatchResultTy +OperandMatchResultTy AArch64AsmParser::tryParsePrefetch(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = getLoc(); @@ -2105,7 +2105,7 @@ } /// tryParsePSBHint - Try to parse a PSB operand, mapped to Hint command -AArch64AsmParser::OperandMatchResultTy +OperandMatchResultTy AArch64AsmParser::tryParsePSBHint(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = getLoc(); @@ -2129,7 +2129,7 @@ /// tryParseAdrpLabel - Parse and validate a source label for the ADRP /// instruction. -AArch64AsmParser::OperandMatchResultTy +OperandMatchResultTy AArch64AsmParser::tryParseAdrpLabel(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = getLoc(); @@ -2180,7 +2180,7 @@ /// tryParseAdrLabel - Parse and validate a source label for the ADR /// instruction. -AArch64AsmParser::OperandMatchResultTy +OperandMatchResultTy AArch64AsmParser::tryParseAdrLabel(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = getLoc(); @@ -2200,7 +2200,7 @@ } /// tryParseFPImm - A floating point immediate expression operand. -AArch64AsmParser::OperandMatchResultTy +OperandMatchResultTy AArch64AsmParser::tryParseFPImm(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = getLoc(); @@ -2264,7 +2264,7 @@ } /// tryParseAddSubImm - Parse ADD/SUB shifted immediate operand -AArch64AsmParser::OperandMatchResultTy +OperandMatchResultTy AArch64AsmParser::tryParseAddSubImm(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = getLoc(); @@ -2382,7 +2382,7 @@ /// tryParseOptionalShift - Some operands take an optional shift argument. Parse /// them if present. -AArch64AsmParser::OperandMatchResultTy +OperandMatchResultTy AArch64AsmParser::tryParseOptionalShiftExtend(OperandVector &Operands) { MCAsmParser &Parser = getParser(); const AsmToken &Tok = Parser.getTok(); @@ -2722,7 +2722,7 @@ return false; } -AArch64AsmParser::OperandMatchResultTy +OperandMatchResultTy AArch64AsmParser::tryParseBarrierOperand(OperandVector &Operands) { MCAsmParser &Parser = getParser(); const AsmToken &Tok = Parser.getTok(); @@ -2776,7 +2776,7 @@ return MatchOperand_Success; } -AArch64AsmParser::OperandMatchResultTy +OperandMatchResultTy AArch64AsmParser::tryParseSysReg(OperandVector &Operands) { MCAsmParser &Parser = getParser(); const AsmToken &Tok = Parser.getTok(); @@ -3075,7 +3075,7 @@ return false; } -AArch64AsmParser::OperandMatchResultTy +OperandMatchResultTy AArch64AsmParser::tryParseGPR64sp0Operand(OperandVector &Operands) { MCAsmParser &Parser = getParser(); const AsmToken &Tok = Parser.getTok(); @@ -4635,7 +4635,7 @@ } -AArch64AsmParser::OperandMatchResultTy +OperandMatchResultTy AArch64AsmParser::tryParseGPRSeqPair(OperandVector &Operands) { SMLoc S = getLoc(); Index: llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ llvm/trunk/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -1199,7 +1199,7 @@ return AMDGPUOperand::CreateReg(this, Reg, StartLoc, EndLoc, false); } -AMDGPUAsmParser::OperandMatchResultTy +OperandMatchResultTy AMDGPUAsmParser::parseImm(OperandVector &Operands) { // TODO: add syntactic sugar for 1/(2*PI) bool Minus = false; @@ -1237,7 +1237,7 @@ } } -AMDGPUAsmParser::OperandMatchResultTy +OperandMatchResultTy AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands) { auto res = parseImm(Operands); if (res != MatchOperand_NoMatch) { @@ -1253,7 +1253,7 @@ return MatchOperand_ParseFail; } -AMDGPUAsmParser::OperandMatchResultTy +OperandMatchResultTy AMDGPUAsmParser::parseRegOrImmWithFPInputMods(OperandVector &Operands) { // XXX: During parsing we can't determine if minus sign means // negate-modifier or negative immediate value. @@ -1317,7 +1317,7 @@ return MatchOperand_Success; } -AMDGPUAsmParser::OperandMatchResultTy +OperandMatchResultTy AMDGPUAsmParser::parseRegOrImmWithIntInputMods(OperandVector &Operands) { bool Sext = false; @@ -1713,7 +1713,7 @@ return true; } -AMDGPUAsmParser::OperandMatchResultTy +OperandMatchResultTy AMDGPUAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { // Try to parse with a custom parser @@ -1785,7 +1785,7 @@ Operands.push_back(AMDGPUOperand::CreateToken(this, Name, NameLoc)); while (!getLexer().is(AsmToken::EndOfStatement)) { - AMDGPUAsmParser::OperandMatchResultTy Res = parseOperand(Operands, Name); + OperandMatchResultTy Res = parseOperand(Operands, Name); // Eat the comma or space if there is one. if (getLexer().is(AsmToken::Comma)) @@ -1815,7 +1815,7 @@ // Utility functions //===----------------------------------------------------------------------===// -AMDGPUAsmParser::OperandMatchResultTy +OperandMatchResultTy AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, int64_t &Int) { switch(getLexer().getKind()) { default: return MatchOperand_NoMatch; @@ -1841,7 +1841,7 @@ return MatchOperand_Success; } -AMDGPUAsmParser::OperandMatchResultTy +OperandMatchResultTy AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, OperandVector &Operands, enum AMDGPUOperand::ImmTy ImmTy, bool (*ConvertResult)(int64_t&)) { @@ -1849,7 +1849,7 @@ SMLoc S = Parser.getTok().getLoc(); int64_t Value = 0; - AMDGPUAsmParser::OperandMatchResultTy Res = parseIntWithPrefix(Prefix, Value); + OperandMatchResultTy Res = parseIntWithPrefix(Prefix, Value); if (Res != MatchOperand_Success) return Res; @@ -1861,7 +1861,7 @@ return MatchOperand_Success; } -AMDGPUAsmParser::OperandMatchResultTy +OperandMatchResultTy AMDGPUAsmParser::parseNamedBit(const char *Name, OperandVector &Operands, enum AMDGPUOperand::ImmTy ImmTy) { int64_t Bit = 0; @@ -1907,7 +1907,7 @@ } } -AMDGPUAsmParser::OperandMatchResultTy +OperandMatchResultTy AMDGPUAsmParser::parseStringWithPrefix(StringRef Prefix, StringRef &Value) { if (getLexer().isNot(AsmToken::Identifier)) { return MatchOperand_NoMatch; @@ -2032,7 +2032,7 @@ return false; } -AMDGPUAsmParser::OperandMatchResultTy +OperandMatchResultTy AMDGPUAsmParser::parseSWaitCntOps(OperandVector &Operands) { IsaVersion IV = getIsaVersion(getSTI().getFeatureBits()); int64_t Waitcnt = getWaitcntBitMask(IV); @@ -2118,7 +2118,7 @@ return false; } -AMDGPUAsmParser::OperandMatchResultTy +OperandMatchResultTy AMDGPUAsmParser::parseHwreg(OperandVector &Operands) { using namespace llvm::AMDGPU::Hwreg; @@ -2266,7 +2266,7 @@ return false; } -AMDGPUAsmParser::OperandMatchResultTy +OperandMatchResultTy AMDGPUAsmParser::parseSendMsgOp(OperandVector &Operands) { using namespace llvm::AMDGPU::SendMsg; @@ -2353,7 +2353,7 @@ // sopp branch targets //===----------------------------------------------------------------------===// -AMDGPUAsmParser::OperandMatchResultTy +OperandMatchResultTy AMDGPUAsmParser::parseSOppBrTarget(OperandVector &Operands) { SMLoc S = Parser.getTok().getLoc(); @@ -2626,7 +2626,7 @@ {"dst_unused", AMDGPUOperand::ImmTySdwaDstUnused, false, nullptr}, }; -AMDGPUAsmParser::OperandMatchResultTy AMDGPUAsmParser::parseOptionalOperand(OperandVector &Operands) { +OperandMatchResultTy AMDGPUAsmParser::parseOptionalOperand(OperandVector &Operands) { OperandMatchResultTy res; for (const OptionalOperand &Op : AMDGPUOptionalOperandTable) { // try to parse any optional operand here @@ -2650,7 +2650,7 @@ return MatchOperand_NoMatch; } -AMDGPUAsmParser::OperandMatchResultTy AMDGPUAsmParser::parseOModOperand(OperandVector &Operands) +OperandMatchResultTy AMDGPUAsmParser::parseOModOperand(OperandVector &Operands) { StringRef Name = Parser.getTok().getString(); if (Name == "mul") { @@ -2756,7 +2756,7 @@ return isImm() && isUInt<4>(getImm()); } -AMDGPUAsmParser::OperandMatchResultTy +OperandMatchResultTy AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) { SMLoc S = Parser.getTok().getLoc(); StringRef Prefix; @@ -2909,14 +2909,14 @@ // sdwa //===----------------------------------------------------------------------===// -AMDGPUAsmParser::OperandMatchResultTy +OperandMatchResultTy AMDGPUAsmParser::parseSDWASel(OperandVector &Operands, StringRef Prefix, AMDGPUOperand::ImmTy Type) { using namespace llvm::AMDGPU::SDWA; SMLoc S = Parser.getTok().getLoc(); StringRef Value; - AMDGPUAsmParser::OperandMatchResultTy res; + OperandMatchResultTy res; res = parseStringWithPrefix(Prefix, Value); if (res != MatchOperand_Success) { @@ -2943,13 +2943,13 @@ return MatchOperand_Success; } -AMDGPUAsmParser::OperandMatchResultTy +OperandMatchResultTy AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) { using namespace llvm::AMDGPU::SDWA; SMLoc S = Parser.getTok().getLoc(); StringRef Value; - AMDGPUAsmParser::OperandMatchResultTy res; + OperandMatchResultTy res; res = parseStringWithPrefix("dst_unused", Value); if (res != MatchOperand_Success) { Index: llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp =================================================================== --- llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp +++ llvm/trunk/lib/Target/ARM/AsmParser/ARMAsmParser.cpp @@ -3449,7 +3449,7 @@ } /// parseITCondCode - Try to parse a condition code for an IT instruction. -ARMAsmParser::OperandMatchResultTy +OperandMatchResultTy ARMAsmParser::parseITCondCode(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = Parser.getTok().getLoc(); @@ -3487,7 +3487,7 @@ /// parseCoprocNumOperand - Try to parse an coprocessor number operand. The /// token must be an Identifier when called, and if it is a coprocessor /// number, the token is eaten and the operand is added to the operand list. -ARMAsmParser::OperandMatchResultTy +OperandMatchResultTy ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = Parser.getTok().getLoc(); @@ -3510,7 +3510,7 @@ /// parseCoprocRegOperand - Try to parse an coprocessor register operand. The /// token must be an Identifier when called, and if it is a coprocessor /// number, the token is eaten and the operand is added to the operand list. -ARMAsmParser::OperandMatchResultTy +OperandMatchResultTy ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = Parser.getTok().getLoc(); @@ -3529,7 +3529,7 @@ /// parseCoprocOptionOperand - Try to parse an coprocessor option operand. /// coproc_option : '{' imm0_255 '}' -ARMAsmParser::OperandMatchResultTy +OperandMatchResultTy ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = Parser.getTok().getLoc(); @@ -3739,7 +3739,7 @@ } // Helper function to parse the lane index for vector lists. -ARMAsmParser::OperandMatchResultTy ARMAsmParser:: +OperandMatchResultTy ARMAsmParser:: parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) { MCAsmParser &Parser = getParser(); Index = 0; // Always return a defined index value. @@ -3791,7 +3791,7 @@ } // parse a vector register list -ARMAsmParser::OperandMatchResultTy +OperandMatchResultTy ARMAsmParser::parseVectorList(OperandVector &Operands) { MCAsmParser &Parser = getParser(); VectorLaneTy LaneKind; @@ -4043,7 +4043,7 @@ } /// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options. -ARMAsmParser::OperandMatchResultTy +OperandMatchResultTy ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = Parser.getTok().getLoc(); @@ -4115,7 +4115,7 @@ } /// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options. -ARMAsmParser::OperandMatchResultTy +OperandMatchResultTy ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = Parser.getTok().getLoc(); @@ -4167,7 +4167,7 @@ /// parseProcIFlagsOperand - Try to parse iflags from CPS instruction. -ARMAsmParser::OperandMatchResultTy +OperandMatchResultTy ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = Parser.getTok().getLoc(); @@ -4202,7 +4202,7 @@ } /// parseMSRMaskOperand - Try to parse mask flags from MSR instruction. -ARMAsmParser::OperandMatchResultTy +OperandMatchResultTy ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = Parser.getTok().getLoc(); @@ -4355,7 +4355,7 @@ /// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for /// use in the MRS/MSR instructions added to support virtualization. -ARMAsmParser::OperandMatchResultTy +OperandMatchResultTy ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = Parser.getTok().getLoc(); @@ -4410,7 +4410,7 @@ return MatchOperand_Success; } -ARMAsmParser::OperandMatchResultTy +OperandMatchResultTy ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low, int High) { MCAsmParser &Parser = getParser(); @@ -4459,7 +4459,7 @@ return MatchOperand_Success; } -ARMAsmParser::OperandMatchResultTy +OperandMatchResultTy ARMAsmParser::parseSetEndImm(OperandVector &Operands) { MCAsmParser &Parser = getParser(); const AsmToken &Tok = Parser.getTok(); @@ -4489,7 +4489,7 @@ /// lsl #n 'n' in [0,31] /// asr #n 'n' in [1,32] /// n == 32 encoded as n == 0. -ARMAsmParser::OperandMatchResultTy +OperandMatchResultTy ARMAsmParser::parseShifterImm(OperandVector &Operands) { MCAsmParser &Parser = getParser(); const AsmToken &Tok = Parser.getTok(); @@ -4560,7 +4560,7 @@ /// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family /// of instructions. Legal values are: /// ror #n 'n' in {0, 8, 16, 24} -ARMAsmParser::OperandMatchResultTy +OperandMatchResultTy ARMAsmParser::parseRotImm(OperandVector &Operands) { MCAsmParser &Parser = getParser(); const AsmToken &Tok = Parser.getTok(); @@ -4607,7 +4607,7 @@ return MatchOperand_Success; } -ARMAsmParser::OperandMatchResultTy +OperandMatchResultTy ARMAsmParser::parseModImm(OperandVector &Operands) { MCAsmParser &Parser = getParser(); MCAsmLexer &Lexer = getLexer(); @@ -4724,7 +4724,7 @@ } } -ARMAsmParser::OperandMatchResultTy +OperandMatchResultTy ARMAsmParser::parseBitfield(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SMLoc S = Parser.getTok().getLoc(); @@ -4793,7 +4793,7 @@ return MatchOperand_Success; } -ARMAsmParser::OperandMatchResultTy +OperandMatchResultTy ARMAsmParser::parsePostIdxReg(OperandVector &Operands) { // Check for a post-index addressing register operand. Specifically: // postidx_reg := '+' register {, shift} @@ -4843,7 +4843,7 @@ return MatchOperand_Success; } -ARMAsmParser::OperandMatchResultTy +OperandMatchResultTy ARMAsmParser::parseAM3Offset(OperandVector &Operands) { // Check for a post-index addressing register operand. Specifically: // am3offset := '+' register @@ -5245,7 +5245,7 @@ } /// parseFPImm - A floating point immediate expression operand. -ARMAsmParser::OperandMatchResultTy +OperandMatchResultTy ARMAsmParser::parseFPImm(OperandVector &Operands) { MCAsmParser &Parser = getParser(); // Anything that can accept a floating point constant as an operand Index: llvm/trunk/lib/Target/AVR/AsmParser/AVRAsmParser.cpp =================================================================== --- llvm/trunk/lib/Target/AVR/AsmParser/AVRAsmParser.cpp +++ llvm/trunk/lib/Target/AVR/AsmParser/AVRAsmParser.cpp @@ -496,7 +496,7 @@ return true; } -AVRAsmParser::OperandMatchResultTy +OperandMatchResultTy AVRAsmParser::parseMemriOperand(OperandVector &Operands) { DEBUG(dbgs() << "parseMemriOperand()\n"); Index: llvm/trunk/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp =================================================================== --- llvm/trunk/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp +++ llvm/trunk/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp @@ -844,7 +844,7 @@ } // Matches memory operand. Returns true if error encountered. -LanaiAsmParser::OperandMatchResultTy +OperandMatchResultTy LanaiAsmParser::parseMemoryOperand(OperandVector &Operands) { // Try to match a memory operand. // The memory operands are of the form: @@ -978,7 +978,7 @@ // Looks at a token type and creates the relevant operand from this // information, adding to operands. // If operand was parsed, returns false, else true. -LanaiAsmParser::OperandMatchResultTy +OperandMatchResultTy LanaiAsmParser::parseOperand(OperandVector *Operands, StringRef Mnemonic) { // Check if the current operand has a custom associated parser, if so, try to // custom parse the operand, or fallback to the general approach. Index: llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ llvm/trunk/lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -4512,14 +4512,14 @@ return getParser().parseExpression(Res); } -MipsAsmParser::OperandMatchResultTy +OperandMatchResultTy MipsAsmParser::parseMemOperand(OperandVector &Operands) { MCAsmParser &Parser = getParser(); DEBUG(dbgs() << "parseMemOperand\n"); const MCExpr *IdVal = nullptr; SMLoc S; bool isParenExpr = false; - MipsAsmParser::OperandMatchResultTy Res = MatchOperand_NoMatch; + OperandMatchResultTy Res = MatchOperand_NoMatch; // First operand is the offset. S = Parser.getTok().getLoc(); @@ -4676,7 +4676,7 @@ return false; } -MipsAsmParser::OperandMatchResultTy +OperandMatchResultTy MipsAsmParser::matchAnyRegisterNameWithoutDollar(OperandVector &Operands, StringRef Identifier, SMLoc S) { @@ -4739,7 +4739,7 @@ return MatchOperand_NoMatch; } -MipsAsmParser::OperandMatchResultTy +OperandMatchResultTy MipsAsmParser::matchAnyRegisterWithoutDollar(OperandVector &Operands, SMLoc S) { MCAsmParser &Parser = getParser(); auto Token = Parser.getLexer().peekTok(false); @@ -4763,7 +4763,7 @@ return MatchOperand_NoMatch; } -MipsAsmParser::OperandMatchResultTy +OperandMatchResultTy MipsAsmParser::parseAnyRegister(OperandVector &Operands) { MCAsmParser &Parser = getParser(); DEBUG(dbgs() << "parseAnyRegister\n"); @@ -4791,7 +4791,7 @@ return ResTy; } -MipsAsmParser::OperandMatchResultTy +OperandMatchResultTy MipsAsmParser::parseJumpTarget(OperandVector &Operands) { MCAsmParser &Parser = getParser(); DEBUG(dbgs() << "parseJumpTarget\n"); @@ -4814,7 +4814,7 @@ return MatchOperand_Success; } -MipsAsmParser::OperandMatchResultTy +OperandMatchResultTy MipsAsmParser::parseInvNum(OperandVector &Operands) { MCAsmParser &Parser = getParser(); const MCExpr *IdVal; @@ -4833,7 +4833,7 @@ return MatchOperand_Success; } -MipsAsmParser::OperandMatchResultTy +OperandMatchResultTy MipsAsmParser::parseRegisterList(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SmallVector Regs; @@ -4919,7 +4919,7 @@ return MatchOperand_Success; } -MipsAsmParser::OperandMatchResultTy +OperandMatchResultTy MipsAsmParser::parseRegisterPair(OperandVector &Operands) { MCAsmParser &Parser = getParser(); @@ -4935,7 +4935,7 @@ return MatchOperand_Success; } -MipsAsmParser::OperandMatchResultTy +OperandMatchResultTy MipsAsmParser::parseMovePRegPair(OperandVector &Operands) { MCAsmParser &Parser = getParser(); SmallVector, 8> TmpOperands; Index: llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp =================================================================== --- llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp +++ llvm/trunk/lib/Target/Sparc/AsmParser/SparcAsmParser.cpp @@ -715,7 +715,7 @@ return false; } -SparcAsmParser::OperandMatchResultTy +OperandMatchResultTy SparcAsmParser::parseMEMOperand(OperandVector &Operands) { SMLoc S, E; @@ -753,7 +753,7 @@ return MatchOperand_Success; } -SparcAsmParser::OperandMatchResultTy +OperandMatchResultTy SparcAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) { OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); @@ -821,7 +821,7 @@ return MatchOperand_Success; } -SparcAsmParser::OperandMatchResultTy +OperandMatchResultTy SparcAsmParser::parseSparcAsmOperand(std::unique_ptr &Op, bool isCall) { @@ -908,7 +908,7 @@ return (Op) ? MatchOperand_Success : MatchOperand_ParseFail; } -SparcAsmParser::OperandMatchResultTy +OperandMatchResultTy SparcAsmParser::parseBranchModifiers(OperandVector &Operands) { // parse (,a|,pn|,pt)+ Index: llvm/trunk/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp =================================================================== --- llvm/trunk/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp +++ llvm/trunk/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp @@ -662,7 +662,7 @@ } // Parse a register and add it to Operands. The other arguments are as above. -SystemZAsmParser::OperandMatchResultTy +OperandMatchResultTy SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group, const unsigned *Regs, RegisterKind Kind) { if (Parser.getTok().isNot(AsmToken::Percent)) @@ -679,7 +679,7 @@ } // Parse any type of register (including integers) and add it to Operands. -SystemZAsmParser::OperandMatchResultTy +OperandMatchResultTy SystemZAsmParser::parseAnyRegister(OperandVector &Operands) { // Handle integer values. if (Parser.getTok().is(AsmToken::Integer)) { @@ -792,7 +792,7 @@ // Parse a memory operand and add it to Operands. The other arguments // are as above. -SystemZAsmParser::OperandMatchResultTy +OperandMatchResultTy SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind, const unsigned *Regs, RegisterKind RegKind) { SMLoc StartLoc = Parser.getTok().getLoc(); @@ -1183,7 +1183,7 @@ llvm_unreachable("Unexpected match type"); } -SystemZAsmParser::OperandMatchResultTy +OperandMatchResultTy SystemZAsmParser::parseAccessReg(OperandVector &Operands) { if (Parser.getTok().isNot(AsmToken::Percent)) return MatchOperand_NoMatch; @@ -1198,7 +1198,7 @@ return MatchOperand_Success; } -SystemZAsmParser::OperandMatchResultTy +OperandMatchResultTy SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal, int64_t MaxVal, bool AllowTLS) { MCContext &Ctx = getContext(); Index: llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp =================================================================== --- llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp +++ llvm/trunk/utils/TableGen/AsmMatcherEmitter.cpp @@ -2728,8 +2728,7 @@ // Emit the operand class switch to call the correct custom parser for // the found operand class. - OS << Target.getName() << ClassName << "::OperandMatchResultTy " - << Target.getName() << ClassName << "::\n" + OS << "OperandMatchResultTy " << Target.getName() << ClassName << "::\n" << "tryCustomParseOperand(OperandVector" << " &Operands,\n unsigned MCK) {\n\n" << " switch(MCK) {\n"; @@ -2750,8 +2749,7 @@ // Emit the static custom operand parser. This code is very similar with // the other matcher. Also use MatchResultTy here just in case we go for // a better error handling. - OS << Target.getName() << ClassName << "::OperandMatchResultTy " - << Target.getName() << ClassName << "::\n" + OS << "OperandMatchResultTy " << Target.getName() << ClassName << "::\n" << "MatchOperandParserImpl(OperandVector" << " &Operands,\n StringRef Mnemonic) {\n"; @@ -2905,11 +2903,6 @@ << " unsigned VariantID = 0);\n"; if (!Info.OperandMatchInfo.empty()) { - OS << "\n enum OperandMatchResultTy {\n"; - OS << " MatchOperand_Success, // operand matched successfully\n"; - OS << " MatchOperand_NoMatch, // operand did not match\n"; - OS << " MatchOperand_ParseFail // operand matched but had errors\n"; - OS << " };\n"; OS << " OperandMatchResultTy MatchOperandParserImpl(\n"; OS << " OperandVector &Operands,\n"; OS << " StringRef Mnemonic);\n";