Index: lib/Target/Sparc/LeonFeatures.td =================================================================== --- lib/Target/Sparc/LeonFeatures.td +++ lib/Target/Sparc/LeonFeatures.td @@ -10,57 +10,76 @@ // //===----------------------------------------------------------------------===// - //===----------------------------------------------------------------------===// -// UMAC and SMAC support for LEON3 and LEON4 processors. +// CASA Support differs between LEON3-FT GR712RC and LEON3-FT UT699 +// We need to have the option to switch this on and off. //===----------------------------------------------------------------------===// -//support to casa instruction; for leon3 subtarget only -def UMACSMACSupport : SubtargetFeature< - "hasumacsmac", - "HasUmacSmac", - "true", - "Enable UMAC and SMAC for LEON3 and LEON4 processors" ->; - +// support to casa instruction; for leon3 subtarget only +def LeonCASA : SubtargetFeature< + "hasleoncasa", "HasLeonCasa", "true", + "Enable CASA instruction for LEON3 and LEON4 processors">; //===----------------------------------------------------------------------===// -// CASA Support differs between LEON3-FT GR712RC and LEON3-FT UT699 -// We need to have the option to switch this on and off. +// UMAC and SMAC support for LEON3 and LEON4 processors. //===----------------------------------------------------------------------===// -//support to casa instruction; for leon3 subtarget only -def LeonCASA : SubtargetFeature< - "hasleoncasa", - "HasLeonCasa", - "true", - "Enable CASA instruction for LEON3 and LEON4 processors" ->; - -def InsertNOPLoad: SubtargetFeature< - "insertnopload", - "InsertNOPLoad", - "true", - "LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction" ->; - -def FixFSMULD : SubtargetFeature< - "fixfsmuld", - "FixFSMULD", - "true", - "LEON erratum fix: Do not use FSMULD" ->; - -def ReplaceFMULS : SubtargetFeature< - "replacefmuls", - "ReplaceFMULS", - "true", - "LEON erratum fix: Replace FMULS instruction with FMULD and relevant conversion instructions" ->; - -def FixAllFDIVSQRT : SubtargetFeature< - "fixallfdivsqrt", - "FixAllFDIVSQRT", - "true", - "LEON erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD instructions with NOPs and floating-point store" ->; +// support to casa instruction; for leon3 subtarget only +def UMACSMACSupport + : SubtargetFeature<"hasumacsmac", "HasUmacSmac", "true", + "Enable UMAC and SMAC for LEON3 and LEON4 processors">; + +//===----------------------------------------------------------------------===// +// LEON Erratum fixes +//===----------------------------------------------------------------------===// + +def ReplaceSDIV + : SubtargetFeature< + "replacesdiv", "PerformSDIVReplace", "true", + "AT697E erratum fix: Do not emit SDIV, emit SDIVCC instead">; + +def FixCALL + : SubtargetFeature<"fixcall", "FixCallImmediates", "true", + "AT697E erratum fix: Restrict the size of the immediate " + "operand of the CALL instruction to 20 bits">; + +def IgnoreZeroFlag + : SubtargetFeature<"ignrzeroflag", "IgnoreZeroFlag", "true", + "AT697E erratum fix: Do not rely on the zero bit flag " + "on a divide overflow for SDIVCC and UDIVCC">; + +def InsertNOPDoublePrecision + : SubtargetFeature<"insrtnopdblprcsn", "InsertNOPDoublePrecision", "true", + "LEON2 erratum fix: Insert a NOP before the double " + "precision floating point instruction">; + +def FixFSMULD : SubtargetFeature<"fixfsmuld", "FixFSMULD", "true", + "LEON3 erratum fix: Do not select FSMULD">; + +def ReplaceFMULS + : SubtargetFeature<"replacefmuls", "ReplaceFMULS", "true", + "LEON3 erratum fix: Replace FMULS instruction with a " + "routine using conversions/double precision operations " + "to replace FMULS">; + +def PreventRoundChange + : SubtargetFeature<"prvntroundchange", "PreventRoundChange", "true", + "LEON3 erratum fix: Prevent any rounding mode change " + "request: use only the round-to-nearest rounding mode">; + +def FixAllFDIVSQRT + : SubtargetFeature<"fixallfdivsqrt", "FixAllFDIVSQRT", "true", + "LEON3 erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD " + "instructions with NOPs and floating-point store">; + +def InsertNOPLoad + : SubtargetFeature<"insertnopload", "InsertNOPLoad", "true", + "LEON3 erratum fix: Insert a NOP instruction after " + "every single-cycle load instruction when the next " + "instruction is another load/store instruction">; + +def InsertNOPsLoadStore + : SubtargetFeature<"insertnopsloadstore", "InsertNOPsLoadStore", "true", + "LEON3 erratum fix: Insert NOPs between " + "single-precision loads and the store, so the number of " + "instructions between is 4">; Index: lib/Target/Sparc/LeonPasses.h =================================================================== --- lib/Target/Sparc/LeonPasses.h +++ lib/Target/Sparc/LeonPasses.h @@ -42,19 +42,60 @@ UsedRegisters.push_back(registerIndex); } int getUnusedFPRegister(MachineRegisterInfo &MRI); + int getUnusedIntRegister(MachineRegisterInfo &MRI); }; -class LLVM_LIBRARY_VISIBILITY InsertNOPLoad : public LEONMachineFunctionPass { +class LLVM_LIBRARY_VISIBILITY ReplaceSDIV : public LEONMachineFunctionPass { public: static char ID; - InsertNOPLoad(TargetMachine &tm); + ReplaceSDIV(); + ReplaceSDIV(TargetMachine &tm); bool runOnMachineFunction(MachineFunction &MF) override; const char *getPassName() const override { - return "InsertNOPLoad: Erratum Fix LBR35: insert a NOP instruction after " - "every single-cycle load instruction when the next instruction is " - "another load/store instruction"; + return "ReplaceSDIV: Leon erratum fix: do not emit SDIV, but emit SDIVCC " + "instead"; + } +}; + +class LLVM_LIBRARY_VISIBILITY FixCALL : public LEONMachineFunctionPass { +public: + static char ID; + + FixCALL(TargetMachine &tm); + bool runOnMachineFunction(MachineFunction &MF) override; + + const char *getPassName() const override { + return "FixCALL: Leon erratum fix: restrict the size of the immediate " + "operand of the CALL instruction to 20 bits"; + } +}; + +class LLVM_LIBRARY_VISIBILITY IgnoreZeroFlag : public LEONMachineFunctionPass { +public: + static char ID; + + IgnoreZeroFlag(TargetMachine &tm); + bool runOnMachineFunction(MachineFunction &MF) override; + + const char *getPassName() const override { + return "IgnoreZeroFlag: Leon erratum fix: do not rely on the zero bit " + "flag on a divide overflow for SDIVCC and UDIVCC"; + } +}; + +class LLVM_LIBRARY_VISIBILITY InsertNOPDoublePrecision + : public LEONMachineFunctionPass { +public: + static char ID; + + InsertNOPDoublePrecision(TargetMachine &tm); + bool runOnMachineFunction(MachineFunction &MF) override; + + const char *getPassName() const override { + return "InsertNOPDoublePrecision: Leon erratum fix: insert a NOP before " + "the double precision floating point instruction"; } }; @@ -66,7 +107,7 @@ bool runOnMachineFunction(MachineFunction &MF) override; const char *getPassName() const override { - return "FixFSMULD: Erratum Fix LBR31: do not select FSMULD"; + return "FixFSMULD: Leon erratum fix: do not utilize FSMULD"; } }; @@ -78,12 +119,26 @@ bool runOnMachineFunction(MachineFunction &MF) override; const char *getPassName() const override { - return "ReplaceFMULS: Erratum Fix LBR32: replace FMULS instruction with a " + return "ReplaceFMULS: Leon erratum fix: Replace FMULS instruction with a " "routine using conversions/double precision operations to replace " "FMULS"; } }; +class LLVM_LIBRARY_VISIBILITY PreventRoundChange + : public LEONMachineFunctionPass { +public: + static char ID; + + PreventRoundChange(TargetMachine &tm); + bool runOnMachineFunction(MachineFunction &MF) override; + + const char *getPassName() const override { + return "PreventRoundChange: Leon erratum fix: prevent any rounding mode " + "change request: use only the round-to-nearest rounding mode"; + } +}; + class LLVM_LIBRARY_VISIBILITY FixAllFDIVSQRT : public LEONMachineFunctionPass { public: static char ID; @@ -92,10 +147,39 @@ bool runOnMachineFunction(MachineFunction &MF) override; const char *getPassName() const override { - return "FixAllFDIVSQRT: Erratum Fix LBR34: fix FDIVS/FDIVD/FSQRTS/FSQRTD " + return "FixAllFDIVSQRT: Leon erratum fix: Fix FDIVS/FDIVD/FSQRTS/FSQRTD " "instructions with NOPs and floating-point store"; } }; -} // namespace llvm + +class LLVM_LIBRARY_VISIBILITY InsertNOPLoad : public LEONMachineFunctionPass { +public: + static char ID; + + InsertNOPLoad(TargetMachine &tm); + bool runOnMachineFunction(MachineFunction &MF) override; + + const char *getPassName() const override { + return "InsertNOPLoad: Leon erratum fix: Insert a NOP instruction after " + "every single-cycle load instruction when the next instruction is " + "another load/store instruction"; + } +}; + +class LLVM_LIBRARY_VISIBILITY InsertNOPsLoadStore + : public LEONMachineFunctionPass { +public: + static char ID; + + InsertNOPsLoadStore(TargetMachine &tm); + bool runOnMachineFunction(MachineFunction &MF) override; + + const char *getPassName() const override { + return "InsertNOPsLoadStore: Leon Erratum Fix: Insert NOPs between " + "single-precision loads and the store, so the number of " + "instructions between is 4"; + } +}; +} // namespace lllvm #endif // LLVM_LIB_TARGET_SPARC_LEON_PASSES_H Index: lib/Target/Sparc/LeonPasses.cpp =================================================================== --- lib/Target/Sparc/LeonPasses.cpp +++ lib/Target/Sparc/LeonPasses.cpp @@ -16,6 +16,7 @@ #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/IR/DiagnosticInfo.h" #include "llvm/IR/LLVMContext.h" #include "llvm/Support/raw_ostream.h" using namespace llvm; @@ -59,6 +60,29 @@ return -1; } +// finds a new free integer register +// checks also the AllocatedRegisters vector +int LEONMachineFunctionPass::getUnusedIntRegister(MachineRegisterInfo &MRI) { + // checks the local registers first + for (int RegisterIndex = SP::L0; RegisterIndex <= SP::L7; ++RegisterIndex) { + if (!MRI.isPhysRegUsed(RegisterIndex) && + !is_contained(UsedRegisters, RegisterIndex)) { + return RegisterIndex; + } + } + + // then checks the global registers, but G0 + for (int RegisterIndex = SP::G1; RegisterIndex <= SP::G7; ++RegisterIndex) { + if (!MRI.isPhysRegUsed(RegisterIndex) && + !is_contained(UsedRegisters, RegisterIndex)) { + return RegisterIndex; + } + } + + return -1; +} + + //***************************************************************************** //**** InsertNOPLoad pass //***************************************************************************** @@ -89,15 +113,6 @@ MachineBasicBlock::iterator NMBBI = std::next(MBBI); BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP)); Modified = true; - } else if (MI.isInlineAsm()) { - // Look for an inline ld or ldf instruction. - StringRef AsmString = - MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName(); - if (AsmString.startswith_lower("ld")) { - MachineBasicBlock::iterator NMBBI = std::next(MBBI); - BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP)); - Modified = true; - } } } } @@ -147,32 +162,6 @@ Reg1Index = MI.getOperand(0).getReg(); Reg2Index = MI.getOperand(1).getReg(); Reg3Index = MI.getOperand(2).getReg(); - } else if (MI.isInlineAsm()) { - std::string AsmString( - MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName()); - std::string FMULSOpCoode("fsmuld"); - std::transform(AsmString.begin(), AsmString.end(), AsmString.begin(), - ::tolower); - if (AsmString.find(FMULSOpCoode) == - 0) { // this is an inline FSMULD instruction - - unsigned StartOp = InlineAsm::MIOp_FirstOperand; - - // extracts the registers from the inline assembly instruction - for (unsigned i = StartOp, e = MI.getNumOperands(); i != e; ++i) { - const MachineOperand &MO = MI.getOperand(i); - if (MO.isReg()) { - if (Reg1Index == UNASSIGNED_INDEX) - Reg1Index = MO.getReg(); - else if (Reg2Index == UNASSIGNED_INDEX) - Reg2Index = MO.getReg(); - else if (Reg3Index == UNASSIGNED_INDEX) - Reg3Index = MO.getReg(); - } - if (Reg3Index != UNASSIGNED_INDEX) - break; - } - } } if (Reg1Index != UNASSIGNED_INDEX && Reg2Index != UNASSIGNED_INDEX && @@ -262,31 +251,6 @@ Reg1Index = MI.getOperand(0).getReg(); Reg2Index = MI.getOperand(1).getReg(); Reg3Index = MI.getOperand(2).getReg(); - } else if (MI.isInlineAsm()) { - std::string AsmString( - MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName()); - std::string FMULSOpCoode("fmuls"); - std::transform(AsmString.begin(), AsmString.end(), AsmString.begin(), - ::tolower); - if (AsmString.find(FMULSOpCoode) == - 0) { // this is an inline FMULS instruction - unsigned StartOp = InlineAsm::MIOp_FirstOperand; - - // extracts the registers from the inline assembly instruction - for (unsigned i = StartOp, e = MI.getNumOperands(); i != e; ++i) { - const MachineOperand &MO = MI.getOperand(i); - if (MO.isReg()) { - if (Reg1Index == UNASSIGNED_INDEX) - Reg1Index = MO.getReg(); - else if (Reg2Index == UNASSIGNED_INDEX) - Reg2Index = MO.getReg(); - else if (Reg3Index == UNASSIGNED_INDEX) - Reg3Index = MO.getReg(); - } - if (Reg3Index != UNASSIGNED_INDEX) - break; - } - } } if (Reg1Index != UNASSIGNED_INDEX && Reg2Index != UNASSIGNED_INDEX && @@ -369,17 +333,13 @@ unsigned Opcode = MI.getOpcode(); if (MI.isInlineAsm()) { - std::string AsmString( - MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName()); - std::string FSQRTDOpCode("fsqrtd"); - std::string FDIVDOpCode("fdivd"); - std::transform(AsmString.begin(), AsmString.end(), AsmString.begin(), - ::tolower); - if (AsmString.find(FSQRTDOpCode) == - 0) { // this is an inline fsqrts instruction + StringRef AsmString = + MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName(); + if (AsmString.startswith_lower("fsqrtd")) { + // this is an inline fsqrts instruction Opcode = SP::FSQRTD; - } else if (AsmString.find(FDIVDOpCode) == - 0) { // this is an inline fsqrts instruction + } else if (AsmString.startswith_lower("fdivd")) { + // this is an inline fsqrts instruction Opcode = SP::FDIVD; } } @@ -389,14 +349,526 @@ // already have been converted to FSQRTD or FDIVD earlier in the // pipeline. if (Opcode == SP::FSQRTD || Opcode == SP::FDIVD) { - for (int InsertedCount = 0; InsertedCount < 5; InsertedCount++) + + //******************************************************************* + //optimization->begin: "Delay Slot after Unused Modified Register" + //******************************************************************* + // The FixAllFDIVSQRT pass shall be oprimized when the source register(s) of FSQRTD or FDIVD is(are) not + // destination resgisters in the previos instruction. If so, reduce the number of inserted NOPs to 2. + //******************************************************************* + bool ShallOptimize = false; + const int UNASSIGNED_INDEX = -1; + int RegSourceIndex1 = UNASSIGNED_INDEX; + int RegSourceIndex2 = UNASSIGNED_INDEX; + if (Opcode == SP::FSQRTD) + //get the source register if the instruction is "fsqrtd fregrs2, fregrd" + RegSourceIndex1 = MI.getOperand(0).getReg(); + else { + //get the source registers if the instruction is "fdivd fregrs1, fregrs2, fregrd" + RegSourceIndex1 = MI.getOperand(0).getReg(); + RegSourceIndex2 = MI.getOperand(1).getReg(); + } + + MachineBasicBlock::iterator PMBBI = std::prev(MBBI); + MachineInstr &PMI = *PMBBI; + int RegFound = 0; + // extract the registers of the prev instruction and check if they + // overlap with the source register(s) of the current instruction + for (MachineInstr::mop_iterator MOp = PMI.operands_begin(), MOE = PMI.operands_end(); MOp != MOE; ++MOp) { + if (MOp->isReg()) { + if ((RegSourceIndex1 == MOp->getReg()) || (RegSourceIndex2 == MOp->getReg())) + RegFound++; + } + } + if (RegFound == 0) // there is no register overlaping, then we shall optimize the pass + ShallOptimize = true; + //******************************************************************* + //optimization->end: "Delay Slot after Unused Modified Register" + //******************************************************************* + + int NumbNOPs = 5; + if (ShallOptimize) // optimization shall be applied + NumbNOPs = 2; + + // Insert 5 NOPs before FSQRTD,FDIVD. + for (int InsertedCount = 0; InsertedCount < NumbNOPs; InsertedCount++) BuildMI(MBB, MBBI, DL, TII.get(SP::NOP)); MachineBasicBlock::iterator NMBBI = std::next(MBBI); - for (int InsertedCount = 0; InsertedCount < 28; InsertedCount++) + + //******************************************************************* + //optimization: "Delay Slot after Unused Modified Register" + //******************************************************************* + // The FixAllFDIVSQRT pass shall be oprimized when the destination register of FSQRTD or FDIVD is not + // used by the next instruction. If so, reduce the number of inserted NOPs by half. + //******************************************************************* + ShallOptimize = false; + MachineInstr &NMI = *NMBBI; + int RegDesIndex = UNASSIGNED_INDEX; + if (Opcode == SP::FSQRTD) + //get dest register if the instruction is "fsqrtd fregrs2, fregrd" + RegDesIndex = MI.getOperand(1).getReg(); + else + //get dest register if the instruction is "fdivd fregrs1, fregrs2, fregrd" + RegDesIndex = MI.getOperand(2).getReg(); + + RegFound = 0; + // extract the registers of the next instruction and check if they + // overlap with the destination register of the current instruction + for (MachineInstr::mop_iterator MOp = NMI.operands_begin(), MOE = NMI.operands_end(); MOp != MOE; ++MOp) { + if (MOp->isReg()) { + if (RegDesIndex == MOp->getReg()) + RegFound++; + } + } + if (RegFound == 0) // there is no register overlaping, then we shall optimize the pass + ShallOptimize = true; + //******************************************************************* + //optimization->end: "Delay Slot after Unused Modified Register" + //******************************************************************* + + NumbNOPs = 28; + if (ShallOptimize) // optimization shall be applied + NumbNOPs = NumbNOPs/2; + + // ... and inserting 28 NOPs after FSQRTD,FDIVD. + for (int InsertedCount = 0; InsertedCount < NumbNOPs; InsertedCount++) BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP)); Modified = true; + } + } + } + + return Modified; +} +//***************************************************************************** +//**** ReplaceSDIV pass +//***************************************************************************** +// This pass fixes the incorrectly working SDIV instruction that +// exist for some earlier versions of the LEON processor line. The instruction +// is replaced with an SDIVcc instruction instead, which is working. +// +char ReplaceSDIV::ID = 0; + +ReplaceSDIV::ReplaceSDIV() : LEONMachineFunctionPass(ID) {} + +ReplaceSDIV::ReplaceSDIV(TargetMachine &tm) : LEONMachineFunctionPass(tm, ID) {} + +bool ReplaceSDIV::runOnMachineFunction(MachineFunction &MF) { + Subtarget = &MF.getSubtarget(); + const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); + + bool Modified = false; + for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) { + MachineBasicBlock &MBB = *MFI; + for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) { + MachineInstr &MI = *MBBI; + unsigned Opcode = MI.getOpcode(); + if (Opcode == SP::SDIVrr) { + MI.setDesc(TII.get(SP::SDIVCCrr)); + Modified = true; + } else if (Opcode == SP::SDIVri) { + MI.setDesc(TII.get(SP::SDIVCCri)); + Modified = true; + } + } + } + + return Modified; +} + +static RegisterPass X("replace-sdiv", "Replase SDIV Pass", false, + false); + +//***************************************************************************** +//**** FixCALL pass +//***************************************************************************** +// This pass restricts the size of the immediate operand of the CALL +// instruction, which can cause problems on some earlier versions of the LEON +// processor, which can interpret some of the call address bits incorrectly. +// +char FixCALL::ID = 0; + +FixCALL::FixCALL(TargetMachine &tm) : LEONMachineFunctionPass(tm, ID) {} + +bool FixCALL::runOnMachineFunction(MachineFunction &MF) { + bool Modified = false; + + for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) { + MachineBasicBlock &MBB = *MFI; + for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) { + MachineInstr &MI = *MBBI; + MI.print(errs()); + errs() << "\n"; + + unsigned Opcode = MI.getOpcode(); + if (Opcode == SP::CALL) { + unsigned NumOperands = MI.getNumOperands(); + for (unsigned OperandIndex = 0; OperandIndex < NumOperands; + OperandIndex++) { + MachineOperand &MO = MI.getOperand(OperandIndex); + if (MO.isImm()) { + const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); + DebugLoc DL = DebugLoc(); + MachineBasicBlock::iterator NMBBI = std::next(MBBI); + + const int ScratchReg1Index = getUnusedIntRegister(MF.getRegInfo()); + markRegisterUsed(ScratchReg1Index); + + // create sethi + BuildMI(MBB, MBBI, DL, TII.get(SP::SETHIi)) + .addReg(ScratchReg1Index) + .addImm(MO.getImm()); + + // create CALLri + BuildMI(MBB, MBBI, DL, TII.get(SP::CALLri)) + .addReg(ScratchReg1Index); + + MI.eraseFromParent(); + MBBI = NMBBI; + + break; + } + } + } + } + } + + return Modified; +} + + +//***************************************************************************** +//**** IgnoreZeroFlag pass +//***************************************************************************** +// This erratum fix fixes the overflow behavior of SDIVCC and UDIVCC +// instructions that exists on some earlier LEON processors. Where these +// instructions are detected, they are replaced by a sequence that will +// explicitly write the overflow bit flag if this is required. +// +char IgnoreZeroFlag::ID = 0; + +IgnoreZeroFlag::IgnoreZeroFlag(TargetMachine &tm) + : LEONMachineFunctionPass(tm, ID) {} + +bool IgnoreZeroFlag::runOnMachineFunction(MachineFunction &MF) { + Subtarget = &MF.getSubtarget(); + const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); + DebugLoc DL = DebugLoc(); + + bool Modified = false; + for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) { + MachineBasicBlock &MBB = *MFI; + for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) { + MachineInstr &MI = *MBBI; + unsigned Opcode = MI.getOpcode(); + if (Opcode == SP::SDIVCCrr || Opcode == SP::SDIVCCri || + Opcode == SP::UDIVCCrr || Opcode == SP::UDIVCCri) { + + // split the current machine basic block - just after the sdivcc/udivcc + // instruction + // create a label that help us skip the zero flag update (of PSR - + // Processor Status Register) + // if conditions are not met + const BasicBlock *LLVM_BB = MBB.getBasicBlock(); + MachineFunction::iterator It = + std::next(MachineFunction::iterator(MBB)); + + MachineBasicBlock *dneBB = MF.CreateMachineBasicBlock(LLVM_BB); + MF.insert(It, dneBB); + + // Transfer the remainder of MBB and its successor edges to dneBB. + dneBB->splice(dneBB->begin(), &MBB, + std::next(MachineBasicBlock::iterator(MI)), MBB.end()); + dneBB->transferSuccessorsAndUpdatePHIs(&MBB); + + MBB.addSuccessor(dneBB); + + MachineBasicBlock::iterator NextMBBI = std::next(MBBI); + + // bvc - branch if overflow flag not set + BuildMI(MBB, NextMBBI, DL, TII.get(SP::BCOND)) + .addMBB(dneBB) + .addImm(SPCC::ICC_VS); + + // bnz - branch if not zero + BuildMI(MBB, NextMBBI, DL, TII.get(SP::BCOND)) + .addMBB(dneBB) + .addImm(SPCC::ICC_NE); + + // use the WRPSR (Write Processor State Register) instruction to set the + // zeo flag to 1 + // create wr %g0, 1, %psr + BuildMI(MBB, NextMBBI, DL, TII.get(SP::WRPSRri)) + .addReg(SP::G0) + .addImm(1); + + BuildMI(MBB, NextMBBI, DL, TII.get(SP::NOP)); + + Modified = true; + } + } + } + + return Modified; +} + +//***************************************************************************** +//**** InsertNOPDoublePrecision pass +//***************************************************************************** +// This erratum fix for some earlier LEON processors fixes a problem where a +// double precision load will not yield the correct result if used in FMUL, +// FDIV, FADD, FSUB or FSQRT instructions later. If this sequence is detected, +// inserting a NOP between the two instructions will fix the erratum. +// 1.scans the code after register allocation; +// 2.checks for the problem conditions as described in the AT697E erratum +// “Odd-Numbered FPU Register Dependency not Properly Checked in some +// Double-Precision FPU Operations”; +// 3.inserts NOPs if the problem exists. +// +char InsertNOPDoublePrecision::ID = 0; + +InsertNOPDoublePrecision::InsertNOPDoublePrecision(TargetMachine &tm) + : LEONMachineFunctionPass(tm, ID) {} + +bool InsertNOPDoublePrecision::runOnMachineFunction(MachineFunction &MF) { + Subtarget = &MF.getSubtarget(); + const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); + DebugLoc DL = DebugLoc(); + + bool Modified = false; + for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) { + MachineBasicBlock &MBB = *MFI; + for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) { + MachineInstr &MI = *MBBI; + unsigned Opcode = MI.getOpcode(); + if (Opcode == SP::LDDFri || Opcode == SP::LDDFrr) { + MachineBasicBlock::iterator NMBBI = std::next(MBBI); + MachineInstr &NMI = *NMBBI; + + unsigned NextOpcode = NMI.getOpcode(); + if (NextOpcode == SP::FADDD || NextOpcode == SP::FSUBD || + NextOpcode == SP::FMULD || NextOpcode == SP::FDIVD) { + int RegAIndex = GetRegIndexForOperand(MI, 0); + int RegBIndex = GetRegIndexForOperand(NMI, 0); + int RegCIndex = + GetRegIndexForOperand(NMI, 2); // Second source operand is index 2 + int RegDIndex = + GetRegIndexForOperand(NMI, 1); // Destination operand is index 1 + + if ((RegAIndex == RegBIndex + 1 && RegBIndex == RegDIndex) || + (RegAIndex == RegCIndex + 1 && RegCIndex == RegDIndex) || + (RegAIndex == RegBIndex + 1 && RegCIndex == RegDIndex) || + (RegAIndex == RegCIndex + 1 && RegBIndex == RegDIndex)) { + // Insert NOP between the two instructions. + BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP)); + Modified = true; + } + + // Check the errata patterns that only happen for FADDD and FMULD + if (Modified == false && + (NextOpcode == SP::FADDD || NextOpcode == SP::FMULD)) { + RegAIndex = GetRegIndexForOperand(MI, 1); + if (RegAIndex == RegBIndex + 1 && RegBIndex == RegCIndex && + RegBIndex == RegDIndex) { + // Insert NOP between the two instructions. + BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP)); + Modified = true; + } + } + } else if (NextOpcode == SP::FSQRTD) { + int RegAIndex = GetRegIndexForOperand(MI, 1); + int RegBIndex = GetRegIndexForOperand(NMI, 0); + int RegCIndex = GetRegIndexForOperand(NMI, 1); + + if (RegAIndex == RegBIndex + 1 && RegBIndex == RegCIndex) { + // Insert NOP between the two instructions. + BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP)); + Modified = true; + } + } + } + } + } + + return Modified; +} + +//***************************************************************************** +//**** PreventRoundChange pass +//***************************************************************************** +// To prevent any explicit change of the default rounding mode, this pass +// detects any call of the fesetround function and removes this call from the +// list of generated operations. +// +char PreventRoundChange::ID = 0; + +PreventRoundChange::PreventRoundChange(TargetMachine &tm) + : LEONMachineFunctionPass(tm, ID) {} + +bool PreventRoundChange::runOnMachineFunction(MachineFunction &MF) { + Subtarget = &MF.getSubtarget(); + + bool Modified = false; + for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) { + MachineBasicBlock &MBB = *MFI; + for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) { + MachineInstr &MI = *MBBI; + unsigned Opcode = MI.getOpcode(); + if (Opcode == SP::CALL && MI.getNumOperands() > 0) { + MachineOperand &MO = MI.getOperand(0); + + if (MO.isGlobal()) { + StringRef FuncName = MO.getGlobal()->getName(); + if (FuncName.compare_lower("fesetround") == 0) { + MachineBasicBlock::iterator NMBBI = std::next(MBBI); + emitOptimizationRemark( + MF.getFunction()->getContext(), getPassName(), *MF.getFunction(), + MI.getDebugLoc(), "Warning: You are using the prvntroundchange " + "option to prevent rounding changes caused " + "by LEON errata. A call to fesetround to be " + "removed from the output."); + MI.eraseFromParent(); + MBBI = NMBBI; + Modified = true; + } + } + } + } + } + + return Modified; +} +//***************************************************************************** +//**** InsertNOPsLoadStore pass +//***************************************************************************** +// This pass shall insert NOPs between floating point loads and stores when the +// following circumstances are present [5]: +// Pattern 1: +// 1. single-precision load or single-precision FPOP to register %fX, where X is +// the same register as the store being checked; +// 2. single-precision load or single-precision FPOP to register %fY , where Y +// is the opposite register in the same double-precision pair; +// 3. 0-3 instructions of any kind, except stores from %fX or %fY or operations +// with %fX as destination; +// 4. the store (from register %fX) being considered. +// Pattern 2: +// 1. double-precision FPOP; +// 2. any number of operations on any kind, except no double-precision FPOP and +// at most one (less than two) single-precision or single-to-double FPOPs; +// 3. the store (from register %fX) being considered. +// +char InsertNOPsLoadStore::ID = 0; + +InsertNOPsLoadStore::InsertNOPsLoadStore(TargetMachine &tm) + : LEONMachineFunctionPass(tm, ID) {} + +bool InsertNOPsLoadStore::runOnMachineFunction(MachineFunction &MF) { + Subtarget = &MF.getSubtarget(); + const TargetInstrInfo &TII = *Subtarget->getInstrInfo(); + DebugLoc DL = DebugLoc(); + + MachineInstr *Pattern1FirstInstruction = NULL; + MachineInstr *Pattern2FirstInstruction = NULL; + unsigned int StoreInstructionsToCheck = 0; + int FxRegIndex, FyRegIndex; + + bool Modified = false; + for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) { + MachineBasicBlock &MBB = *MFI; + for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++MBBI) { + MachineInstr &MI = *MBBI; + + if (StoreInstructionsToCheck > 0) { + if (((MI.getOpcode() == SP::STFrr || MI.getOpcode() == SP::STFri) && + (GetRegIndexForOperand(MI, LAST_OPERAND) == FxRegIndex || + GetRegIndexForOperand(MI, LAST_OPERAND) == FyRegIndex)) || + GetRegIndexForOperand(MI, 0) == FxRegIndex) { + // Insert four NOPs + for (unsigned InsertedCount = 0; InsertedCount < 4; InsertedCount++) { + BuildMI(MBB, MBBI, DL, TII.get(SP::NOP)); + } + Modified = true; + } + StoreInstructionsToCheck--; + } + + switch (MI.getOpcode()) { + // Watch for Pattern 1 FPop instructions + case SP::LDrr: + case SP::LDri: + case SP::LDFrr: + case SP::LDFri: + case SP::FADDS: + case SP::FSUBS: + case SP::FMULS: + case SP::FDIVS: + case SP::FSQRTS: + case SP::FCMPS: + case SP::FMOVS: + case SP::FNEGS: + case SP::FABSS: + case SP::FITOS: + case SP::FSTOI: + case SP::FITOD: + case SP::FDTOI: + case SP::FDTOS: + if (Pattern1FirstInstruction != NULL) { + FxRegIndex = GetRegIndexForOperand(*Pattern1FirstInstruction, 0); + FyRegIndex = GetRegIndexForOperand(MI, 0); + + // Check to see if these registers are part of the same double + // precision + // register pair. + int DoublePrecRegIndexForX = (FxRegIndex - SP::F0) / 2; + int DoublePrecRegIndexForY = (FyRegIndex - SP::F0) / 2; + + if (DoublePrecRegIndexForX == DoublePrecRegIndexForY) + StoreInstructionsToCheck = 4; + } + + Pattern1FirstInstruction = &MI; + break; + // End of Pattern 1 + + // Search for Pattern 2 + case SP::FADDD: + case SP::FSUBD: + case SP::FMULD: + case SP::FDIVD: + case SP::FSQRTD: + case SP::FCMPD: + Pattern2FirstInstruction = &MI; + Pattern1FirstInstruction = NULL; + break; + + case SP::STFrr: + case SP::STFri: + case SP::STDFrr: + case SP::STDFri: + if (Pattern2FirstInstruction != NULL) { + if (GetRegIndexForOperand(MI, LAST_OPERAND) == + GetRegIndexForOperand(*Pattern2FirstInstruction, 0)) { + // Insert four NOPs + for (unsigned InsertedCount = 0; InsertedCount < 4; + InsertedCount++) { + BuildMI(MBB, MBBI, DL, TII.get(SP::NOP)); + } + + Pattern2FirstInstruction = NULL; + } + } + Pattern1FirstInstruction = NULL; + break; + // End of Pattern 2 + + default: + // Ensure we don't count debug-only values while we're testing for the + // patterns. + if (!MI.isDebugValue()) + Pattern1FirstInstruction = NULL; + break; } } } Index: lib/Target/Sparc/Sparc.td =================================================================== --- lib/Target/Sparc/Sparc.td +++ lib/Target/Sparc/Sparc.td @@ -108,38 +108,43 @@ [FeatureLeon]>; // LEON 2 FT (AT697E) -// TO DO: Place-holder: Processor specific features will be added *very* soon here. -def : Processor<"at697e", LEON2Itineraries, - [FeatureLeon, InsertNOPLoad]>; +// AT697E: Provides full coverage of AT697E - covers all the erratum fixes for +// LEON2 AT697E +def : Processor<"at697e", LEON2Itineraries, [ + FeatureLeon, ReplaceSDIV, FixCALL, IgnoreZeroFlag, InsertNOPDoublePrecision +]>; // LEON 2 FT (AT697F) -// TO DO: Place-holder: Processor specific features will be added *very* soon here. +// AT697F: Provides full coverage of AT697F - covers all the erratum fixes for +// LEON2 AT697F def : Processor<"at697f", LEON2Itineraries, - [FeatureLeon, InsertNOPLoad]>; - + [ FeatureLeon, InsertNOPDoublePrecision ]>; // LEON 3 FT generic def : Processor<"leon3", LEON3Itineraries, [FeatureLeon, UMACSMACSupport]>; // LEON 3 FT (UT699). Provides features for the UT699 processor -// - covers all the erratum fixes for LEON3, but does not support the CASA instruction. -def : Processor<"ut699", LEON3Itineraries, - [FeatureLeon, InsertNOPLoad, FixFSMULD, ReplaceFMULS, FixAllFDIVSQRT]>; +// - covers all the erratum fixes for LEON3, but does not support the CASA +// instruction. +def : Processor<"ut699", LEON3Itineraries, [ + FeatureLeon, FixFSMULD, ReplaceFMULS, PreventRoundChange, + FixAllFDIVSQRT, InsertNOPLoad, InsertNOPsLoadStore, UMACSMACSupport +]>; // LEON3 FT (GR712RC). Provides features for the GR712RC processor. // - covers all the erratum fixed for LEON3 and support for the CASA instruction. def : Processor<"gr712rc", LEON3Itineraries, - [FeatureLeon, LeonCASA]>; + [ FeatureLeon, LeonCASA, UMACSMACSupport ]>; // LEON 4 FT generic def : Processor<"leon4", LEON4Itineraries, - [FeatureLeon, UMACSMACSupport, LeonCASA]>; + [ FeatureLeon, LeonCASA, UMACSMACSupport ]>; -// LEON 4 FT (GR740) -// TO DO: Place-holder: Processor specific features will be added *very* soon here. -def : Processor<"gr740", LEON4Itineraries, - [FeatureLeon, UMACSMACSupport, LeonCASA]>; +// GR740: Provides full coverage of GR740 - covers all the erratum fixes for +// LEON3 + support to CASA + LEON 4 instruction timings +def : Processor<"gr740", LEON4Itineraries, + [ FeatureLeon, LeonCASA, UMACSMACSupport ]> {} //===----------------------------------------------------------------------===// // Declare the target which we are implementing Index: lib/Target/Sparc/SparcISelLowering.cpp =================================================================== --- lib/Target/Sparc/SparcISelLowering.cpp +++ lib/Target/Sparc/SparcISelLowering.cpp @@ -1620,7 +1620,7 @@ if (Subtarget->isV9()) setMaxAtomicSizeInBitsSupported(64); else if (Subtarget->hasLeonCasa()) - setMaxAtomicSizeInBitsSupported(64); + setMaxAtomicSizeInBitsSupported(32); else setMaxAtomicSizeInBitsSupported(0); Index: lib/Target/Sparc/SparcSubtarget.h =================================================================== --- lib/Target/Sparc/SparcSubtarget.h +++ lib/Target/Sparc/SparcSubtarget.h @@ -48,6 +48,13 @@ bool FixFSMULD; bool ReplaceFMULS; bool FixAllFDIVSQRT; + bool UseSoftFpu; + bool PerformSDIVReplace; + bool FixCallImmediates; + bool IgnoreZeroFlag; + bool InsertNOPDoublePrecision; + bool PreventRoundChange; + bool InsertNOPsLoadStore; SparcInstrInfo InstrInfo; SparcTargetLowering TLInfo; @@ -85,12 +92,19 @@ bool useSoftFloat() const { return UseSoftFloat; } // Leon options - bool hasUmacSmac() const { return HasUmacSmac; } + bool useSoftFpu() const { return UseSoftFpu; } bool hasLeonCasa() const { return HasLeonCasa; } - bool insertNOPLoad() const { return InsertNOPLoad; } + bool hasUmacSmac() const { return HasUmacSmac; } + bool performSDIVReplace() const { return PerformSDIVReplace; } + bool fixCallImmediates() const { return FixCallImmediates; } + bool ignoreZeroFlag() const { return IgnoreZeroFlag; } + bool insertNOPDoublePrecision() const { return InsertNOPDoublePrecision; } bool fixFSMULD() const { return FixFSMULD; } bool replaceFMULS() const { return ReplaceFMULS; } + bool preventRoundChange() const { return PreventRoundChange; } bool fixAllFDIVSQRT() const { return FixAllFDIVSQRT; } + bool insertNOPsLoadStore() const { return InsertNOPsLoadStore; } + bool insertNOPLoad() const { return InsertNOPLoad; } /// ParseSubtargetFeatures - Parses features string setting specified /// subtarget options. Definition of function is auto generated by tblgen. Index: lib/Target/Sparc/SparcSubtarget.cpp =================================================================== --- lib/Target/Sparc/SparcSubtarget.cpp +++ lib/Target/Sparc/SparcSubtarget.cpp @@ -39,10 +39,16 @@ // Leon features HasLeonCasa = false; HasUmacSmac = false; - InsertNOPLoad = false; + PerformSDIVReplace = false; + FixCallImmediates = false; + IgnoreZeroFlag = false; + InsertNOPDoublePrecision = false; FixFSMULD = false; ReplaceFMULS = false; + PreventRoundChange = false; FixAllFDIVSQRT = false; + InsertNOPLoad = false; + InsertNOPsLoadStore = false; // Determine default and user specified characteristics std::string CPUName = CPU; Index: lib/Target/Sparc/SparcTargetMachine.cpp =================================================================== --- lib/Target/Sparc/SparcTargetMachine.cpp +++ lib/Target/Sparc/SparcTargetMachine.cpp @@ -76,7 +76,7 @@ SparcTargetMachine::~SparcTargetMachine() {} -const SparcSubtarget * +const SparcSubtarget * SparcTargetMachine::getSubtargetImpl(const Function &F) const { Attribute CPUAttr = F.getFnAttribute("target-cpu"); Attribute FSAttr = F.getFnAttribute("target-features"); @@ -95,7 +95,7 @@ F.hasFnAttribute("use-soft-float") && F.getFnAttribute("use-soft-float").getValueAsString() == "true"; - if (softFloat) + if (softFloat) FS += FS.empty() ? "+soft-float" : ",+soft-float"; auto &I = SubtargetMap[CPU + FS]; @@ -115,7 +115,7 @@ class SparcPassConfig : public TargetPassConfig { public: SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM) - : TargetPassConfig(TM, PM) {} + : TargetPassConfig(TM, PM) {} SparcTargetMachine &getSparcTargetMachine() const { return getTM(); @@ -142,28 +142,43 @@ return false; } -void SparcPassConfig::addPreEmitPass(){ +void SparcPassConfig::addPreEmitPass() { addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine())); - - if (this->getSparcTargetMachine().getSubtargetImpl()->insertNOPLoad()) - { - addPass(new InsertNOPLoad(getSparcTargetMachine())); + if (this->getSparcTargetMachine().getSubtargetImpl()->ignoreZeroFlag()) { + addPass(new IgnoreZeroFlag(getSparcTargetMachine())); + } + if (this->getSparcTargetMachine().getSubtargetImpl()->performSDIVReplace()) { + addPass(new ReplaceSDIV(getSparcTargetMachine())); } - if (this->getSparcTargetMachine().getSubtargetImpl()->fixFSMULD()) - { + if (this->getSparcTargetMachine().getSubtargetImpl()->fixCallImmediates()) { + addPass(new FixCALL(getSparcTargetMachine())); + } + if (this->getSparcTargetMachine().getSubtargetImpl()->fixFSMULD()) { addPass(new FixFSMULD(getSparcTargetMachine())); } - if (this->getSparcTargetMachine().getSubtargetImpl()->replaceFMULS()) - { + if (this->getSparcTargetMachine().getSubtargetImpl()->replaceFMULS()) { addPass(new ReplaceFMULS(getSparcTargetMachine())); } - if (this->getSparcTargetMachine().getSubtargetImpl()->fixAllFDIVSQRT()) - { + if (this->getSparcTargetMachine().getSubtargetImpl()->preventRoundChange()) { + addPass(new PreventRoundChange(getSparcTargetMachine())); + } + if (this->getSparcTargetMachine().getSubtargetImpl()->fixAllFDIVSQRT()) { addPass(new FixAllFDIVSQRT(getSparcTargetMachine())); } + if (this->getSparcTargetMachine().getSubtargetImpl()->insertNOPsLoadStore()) { + addPass(new InsertNOPsLoadStore(getSparcTargetMachine())); + } + if (this->getSparcTargetMachine().getSubtargetImpl()->insertNOPLoad()) { + addPass(new InsertNOPLoad(getSparcTargetMachine())); + } + if (this->getSparcTargetMachine() + .getSubtargetImpl() + ->insertNOPDoublePrecision()) { + addPass(new InsertNOPDoublePrecision(getSparcTargetMachine())); + } } -void SparcV8TargetMachine::anchor() { } +void SparcV8TargetMachine::anchor() {} SparcV8TargetMachine::SparcV8TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, @@ -173,7 +188,7 @@ CodeGenOpt::Level OL) : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} -void SparcV9TargetMachine::anchor() { } +void SparcV9TargetMachine::anchor() {} SparcV9TargetMachine::SparcV9TargetMachine(const Target &T, const Triple &TT, StringRef CPU, StringRef FS, Index: test/CodeGen/SPARC/LeonFixFSMULDPassUT.ll =================================================================== --- test/CodeGen/SPARC/LeonFixFSMULDPassUT.ll +++ test/CodeGen/SPARC/LeonFixFSMULDPassUT.ll @@ -1,31 +1,17 @@ -; RUN: llc %s -O0 -march=sparc -mcpu=ut699 -o - | FileCheck %s +; RUN: llc %s -O0 -march=sparc -mattr=fixfsmuld -o - | FileCheck %s +; RUN: llc %s -O0 -march=sparc -o - | FileCheck %s --check-prefix=NOFIX ; CHECK-LABEL: test_fix_fsmuld_1 -; CHECK: fstod %f20, %f2 -; CHECK: fstod %f21, %f3 -; CHECK: fmuld %f2, %f3, %f8 -; CHECK: fstod %f20, %f0 -define double @test_fix_fsmuld_1() { +; CHECK: fstod %f1, %f2 +; CHECK: fstod %f0, %f4 +; CHECK: fmuld %f2, %f4, %f0 +; NOFIX-LABEL: test_fix_fsmuld_1 +; NOFIX: fsmuld %f1, %f0, %f0 +define double @test_fix_fsmuld_1(float %a, float %b) { entry: - %a = alloca float, align 4 - %b = alloca float, align 4 - store float 0x402ECCCCC0000000, float* %a, align 4 - store float 0x4022333340000000, float* %b, align 4 - %0 = load float, float* %b, align 4 - %1 = load float, float* %a, align 4 - %mul = tail call double asm sideeffect "fsmuld $0, $1, $2", "={f20},{f21},{f8}"(float* %a, float* %b) - - ret double %mul -} - -; CHECK-LABEL: test_fix_fsmuld_2 -; CHECK: fstod %f20, %f2 -; CHECK: fstod %f21, %f3 -; CHECK: fmuld %f2, %f3, %f8 -; CHECK: fstod %f20, %f0 -define double @test_fix_fsmuld_2(float* %a, float* %b) { -entry: - %mul = tail call double asm sideeffect "fsmuld $0, $1, $2", "={f20},{f21},{f8}"(float* %a, float* %b) + %0 = fpext float %a to double + %1 = fpext float %b to double + %mul = fmul double %0, %1 ret double %mul } Index: test/CodeGen/SPARC/LeonInsertNOPLoadPassUT.ll =================================================================== --- test/CodeGen/SPARC/LeonInsertNOPLoadPassUT.ll +++ test/CodeGen/SPARC/LeonInsertNOPLoadPassUT.ll @@ -19,25 +19,3 @@ %res = load i32, i32* %p ret i32 %res } - -; CHECK-LABEL: ld_inlineasm_test_1 -; CHECK: ld [%o0], %o0 -; CHECK-NEXT: !NO_APP -; CHECK-NEXT: nop -define float @ld_inlineasm_test_1(float* %a) { -entry: - %res = tail call float asm sideeffect "ld [$1], $0", "=r,r"(float* %a) - - ret float %res -} - -; CHECK-LABEL: ld_inlineasm_test_2 -; CHECK: ld [%o0], %o0 -; CHECK-NEXT: !NO_APP -; CHECK-NEXT: nop -define i32 @ld_inlineasm_test_2(i32* %a) { -entry: - %res = tail call i32 asm sideeffect "ld [$1], $0", "=r,r"(i32* %a) - - ret i32 %res -} \ No newline at end of file Index: test/CodeGen/SPARC/LeonReplaceFMULSPassUT.ll =================================================================== --- test/CodeGen/SPARC/LeonReplaceFMULSPassUT.ll +++ test/CodeGen/SPARC/LeonReplaceFMULSPassUT.ll @@ -1,19 +1,13 @@ -; RUN: llc %s -O0 -march=sparc -mcpu=ut699 -o - | FileCheck %s +; RUN: llc %s -O0 -march=sparc -mattr=replacefmuls -o - | FileCheck %s -; CHECK-LABEL: fmuls_fix_test -; CHECK: fstod %f20, %f2 -; CHECK: fstod %f21, %f3 -; CHECK: fmuld %f2, %f3, %f8 -; CHECK: fstod %f20, %f0 -define double @fmuls_fix_test() { +; CHECK-LABEL: test_replace_fmuls +; CHECK: fsmuld %f1, %f0, %f2 +; CHECK: fdtos %f2, %f0 +; NOFIX-LABEL: test_replace_fmuls +; NOFIX: fmuls %f1, %f0, %f0 +define float @test_replace_fmuls(float %a, float %b) { entry: - %a = alloca float, align 4 - %b = alloca float, align 4 - store float 0x402ECCCCC0000000, float* %a, align 4 - store float 0x4022333340000000, float* %b, align 4 - %0 = load float, float* %b, align 4 - %1 = load float, float* %a, align 4 - %mul = tail call double asm sideeffect "fmuls $0, $1, $2", "={f20},{f21},{f8}"(float* %a, float* %b) + %mul = fmul float %a, %b - ret double %mul + ret float %mul }