Index: llvm/trunk/lib/Target/AVR/AVRInstrInfo.h
===================================================================
--- llvm/trunk/lib/Target/AVR/AVRInstrInfo.h
+++ llvm/trunk/lib/Target/AVR/AVRInstrInfo.h
@@ -70,7 +70,7 @@
   const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const;
   AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const;
   AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const;
-  unsigned getInstSizeInBytes(const MachineInstr *MI) const override;
+  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
 
   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
                    const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
Index: llvm/trunk/lib/Target/AVR/AVRInstrInfo.cpp
===================================================================
--- llvm/trunk/lib/Target/AVR/AVRInstrInfo.cpp
+++ llvm/trunk/lib/Target/AVR/AVRInstrInfo.cpp
@@ -439,8 +439,8 @@
   return false;
 }
 
-unsigned AVRInstrInfo::getInstSizeInBytes(const MachineInstr *MI) const {
-  unsigned Opcode = MI->getOpcode();
+unsigned AVRInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
+  unsigned Opcode = MI.getOpcode();
 
   switch (Opcode) {
   // A regular instruction
@@ -454,10 +454,10 @@
   case TargetOpcode::DBG_VALUE:
     return 0;
   case TargetOpcode::INLINEASM: {
-    const MachineFunction *MF = MI->getParent()->getParent();
+    const MachineFunction *MF = MI.getParent()->getParent();
     const AVRTargetMachine &TM = static_cast<const AVRTargetMachine&>(MF->getTarget());
     const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
-    return TII.getInlineAsmLength(MI->getOperand(0).getSymbolName(),
+    return TII.getInlineAsmLength(MI.getOperand(0).getSymbolName(),
                                   *TM.getMCAsmInfo());
   }
   }