Index: lib/Target/AArch64/AArch64BranchRelaxation.cpp
===================================================================
--- lib/Target/AArch64/AArch64BranchRelaxation.cpp
+++ lib/Target/AArch64/AArch64BranchRelaxation.cpp
@@ -167,8 +167,11 @@
 /// This function updates BlockInfo directly.
 void AArch64BranchRelaxation::computeBlockSize(const MachineBasicBlock &MBB) {
   unsigned Size = 0;
-  for (const MachineInstr &MI : MBB)
-    Size += TII->getInstSizeInBytes(MI);
+  for (const MachineInstr &MI : MBB) {
+    unsigned InstSize = TII->getInstSizeInBytes(MI);
+    assert(InstSize != ~0U && "Failed to get instruction size");
+    Size += InstSize;
+  }
   BlockInfo[MBB.getNumber()].Size = Size;
 }
 
@@ -186,7 +189,9 @@
   // Sum instructions before MI in MBB.
   for (MachineBasicBlock::const_iterator I = MBB->begin(); &*I != &MI; ++I) {
     assert(I != MBB->end() && "Didn't find MI in its own basic block?");
-    Offset += TII->getInstSizeInBytes(*I);
+    unsigned InstSize = TII->getInstSizeInBytes(*I);
+    assert(InstSize != ~0U && "Failed to get instruction size");
+    Offset += InstSize;
   }
 
   return Offset;
@@ -343,7 +348,9 @@
 
   MIB.addMBB(&NewDestBB);
 
-  return TII->getInstSizeInBytes(*MIB);
+  unsigned InstSize = TII->getInstSizeInBytes(*MIB);
+  assert(InstSize != ~0U && "Failed to get instruction size");
+  return InstSize;
 }
 
 /// Insert an unconditional branch at the end of \p MBB to \p DestBB.
@@ -355,7 +362,9 @@
   MachineInstr *MI = BuildMI(&MBB, DL, TII->get(AArch64::B))
     .addMBB(&DestBB);
 
-  return TII->getInstSizeInBytes(*MI);
+  unsigned InstSize = TII->getInstSizeInBytes(*MI);
+  assert(InstSize != ~0U && "Failed to get instruction size");
+  return InstSize;
 }
 
 static void changeBranchDestBlock(MachineInstr &MI,
@@ -414,7 +423,8 @@
         int NewSize =
           insertInvertedConditionalBranch(*MBB, MI.getIterator(),
                                           MI.getDebugLoc(), MI, *NewDest);
-        int OldSize = TII->getInstSizeInBytes(MI);
+        unsigned OldSize = TII->getInstSizeInBytes(MI);
+        assert(OldSize != ~0U && "Failed to get instruction size");
         BlockInfo[MBB->getNumber()].Size += (NewSize - OldSize);
         MI.eraseFromParent();
         return true;
@@ -431,7 +441,8 @@
     MachineBasicBlock *NewBB = splitBlockBeforeInstr(MI);
     // No need for the branch to the next block. We're adding an unconditional
     // branch to the destination.
-    int delta = TII->getInstSizeInBytes(MBB->back());
+    unsigned delta = TII->getInstSizeInBytes(MBB->back());
+    assert(delta != ~0U && "Failed to get instruction size");
     BlockInfo[MBB->getNumber()].Size -= delta;
     MBB->back().eraseFromParent();
     // BlockInfo[SplitBB].Offset is wrong temporarily, fixed below
@@ -457,7 +468,9 @@
   MBBSize += insertUnconditionalBranch(*MBB, *DestBB, MI.getDebugLoc());
 
   // Remove the old conditional branch.  It may or may not still be in MBB.
-  MBBSize -= TII->getInstSizeInBytes(MI);
+  unsigned InstSize = TII->getInstSizeInBytes(MI);
+  assert(InstSize != ~0U && "Failed to get instruction size");
+  MBBSize -= InstSize;
   MI.eraseFromParent();
 
   // Finally, keep the block offsets up to date.
Index: lib/Target/AArch64/AArch64InstrInfo.cpp
===================================================================
--- lib/Target/AArch64/AArch64InstrInfo.cpp
+++ lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -72,8 +72,7 @@
     // This gets lowered to an instruction sequence which takes 16 bytes
     return 16;
   }
-
-  llvm_unreachable("getInstSizeInBytes()- Unable to determin insn size");
+  return ~0U;
 }
 
 static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,
Index: lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -335,7 +335,9 @@
       if (MI.isDebugValue())
         continue;
 
-      CodeSize += TII->getInstSizeInBytes(MI);
+      unsigned InstSize = TII->getInstSizeInBytes(MI);
+      assert(InstSize != ~0U && "Failed to get instruction size");
+      CodeSize += InstSize;
 
       unsigned numOperands = MI.getNumOperands();
       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
Index: lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.cpp
+++ lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -3186,7 +3186,7 @@
     return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
   }
   default:
-    llvm_unreachable("unable to find instruction size");
+    return ~0U;
   }
 }
 
Index: lib/Target/MSP430/MSP430BranchSelector.cpp
===================================================================
--- lib/Target/MSP430/MSP430BranchSelector.cpp
+++ lib/Target/MSP430/MSP430BranchSelector.cpp
@@ -69,8 +69,11 @@
   unsigned FuncSize = 0;
   for (MachineBasicBlock &MBB : Fn) {
     unsigned BlockSize = 0;
-    for (MachineInstr &MI : MBB)
-      BlockSize += TII->getInstSizeInBytes(MI);
+    for (MachineInstr &MI : MBB) {
+      unsigned InstSize = TII->getInstSizeInBytes(MI);
+      assert(InstSize != ~0U && "Failed to get instruction size");
+      BlockSize += InstSize;
+    }
 
     BlockSizes[MBB.getNumber()] = BlockSize;
     FuncSize += BlockSize;
@@ -107,7 +110,9 @@
            I != E; ++I) {
         if ((I->getOpcode() != MSP430::JCC || I->getOperand(0).isImm()) &&
             I->getOpcode() != MSP430::JMP) {
-          MBBStartOffset += TII->getInstSizeInBytes(*I);
+          unsigned InstSize = TII->getInstSizeInBytes(*I);
+          assert(InstSize != ~0U && "Failed to get instruction size");
+          MBBStartOffset += InstSize;
           continue;
         }
 
Index: lib/Target/MSP430/MSP430InstrInfo.cpp
===================================================================
--- lib/Target/MSP430/MSP430InstrInfo.cpp
+++ lib/Target/MSP430/MSP430InstrInfo.cpp
@@ -299,7 +299,7 @@
   switch (Desc.TSFlags & MSP430II::SizeMask) {
   default:
     switch (Desc.getOpcode()) {
-    default: llvm_unreachable("Unknown instruction size!");
+    default: return ~0U;
     case TargetOpcode::CFI_INSTRUCTION:
     case TargetOpcode::EH_LABEL:
     case TargetOpcode::IMPLICIT_DEF:
@@ -315,7 +315,7 @@
     }
   case MSP430II::SizeSpecial:
     switch (MI.getOpcode()) {
-    default: llvm_unreachable("Unknown instruction size!");
+    default: return ~0U;
     case MSP430::SAR8r1c:
     case MSP430::SAR16r1c:
       return 4;