Index: lib/Target/AArch64/AArch64BranchRelaxation.cpp
===================================================================
--- lib/Target/AArch64/AArch64BranchRelaxation.cpp
+++ lib/Target/AArch64/AArch64BranchRelaxation.cpp
@@ -167,8 +167,15 @@
 /// This function updates BlockInfo directly.
 void AArch64BranchRelaxation::computeBlockSize(const MachineBasicBlock &MBB) {
   unsigned Size = 0;
-  for (const MachineInstr &MI : MBB)
-    Size += TII->getInstSizeInBytes(MI);
+  for (const MachineInstr &MI : MBB) {
+    unsigned InstSize = TII->getInstSizeInBytes(MI);
+    // Do the error check here and not at the other invocations of
+    // getInstSizeInBytes because here all instructions are seen for the first
+    // time.
+    if (InstSize == ~0U)
+      llvm_unreachable("Failed to get instruction size");
+    Size += InstSize;
+  }
   BlockInfo[MBB.getNumber()].Size = Size;
 }
 
Index: lib/Target/AArch64/AArch64InstrInfo.cpp
===================================================================
--- lib/Target/AArch64/AArch64InstrInfo.cpp
+++ lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -72,8 +72,7 @@
     // This gets lowered to an instruction sequence which takes 16 bytes
     return 16;
   }
-
-  llvm_unreachable("getInstSizeInBytes()- Unable to determin insn size");
+  return ~0U;
 }
 
 static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,
Index: lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
===================================================================
--- lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -335,7 +335,10 @@
       if (MI.isDebugValue())
         continue;
 
-      CodeSize += TII->getInstSizeInBytes(MI);
+      unsigned InstSize = TII->getInstSizeInBytes(MI);
+      if (InstSize == ~0U)
+        llvm_unreachable("Failed to get instruction size");
+      CodeSize += InstSize;
 
       unsigned numOperands = MI.getNumOperands();
       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
Index: lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- lib/Target/AMDGPU/SIInstrInfo.cpp
+++ lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -3186,7 +3186,7 @@
     return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
   }
   default:
-    llvm_unreachable("unable to find instruction size");
+    return ~0U;
   }
 }
 
Index: lib/Target/MSP430/MSP430BranchSelector.cpp
===================================================================
--- lib/Target/MSP430/MSP430BranchSelector.cpp
+++ lib/Target/MSP430/MSP430BranchSelector.cpp
@@ -69,8 +69,12 @@
   unsigned FuncSize = 0;
   for (MachineBasicBlock &MBB : Fn) {
     unsigned BlockSize = 0;
-    for (MachineInstr &MI : MBB)
-      BlockSize += TII->getInstSizeInBytes(MI);
+    for (MachineInstr &MI : MBB) {
+      unsigned InstSize = TII->getInstSizeInBytes(MI);
+      if (InstSize == ~0U)
+        llvm_unreachable("Failed to get instruction size");
+      BlockSize += InstSize;
+    }
 
     BlockSizes[MBB.getNumber()] = BlockSize;
     FuncSize += BlockSize;
Index: lib/Target/MSP430/MSP430InstrInfo.cpp
===================================================================
--- lib/Target/MSP430/MSP430InstrInfo.cpp
+++ lib/Target/MSP430/MSP430InstrInfo.cpp
@@ -299,7 +299,7 @@
   switch (Desc.TSFlags & MSP430II::SizeMask) {
   default:
     switch (Desc.getOpcode()) {
-    default: llvm_unreachable("Unknown instruction size!");
+    default: return ~0U;
     case TargetOpcode::CFI_INSTRUCTION:
     case TargetOpcode::EH_LABEL:
     case TargetOpcode::IMPLICIT_DEF:
@@ -315,7 +315,7 @@
     }
   case MSP430II::SizeSpecial:
     switch (MI.getOpcode()) {
-    default: llvm_unreachable("Unknown instruction size!");
+    default: return ~0U;
     case MSP430::SAR8r1c:
     case MSP430::SAR16r1c:
       return 4;