Index: lib/CodeGen/SelectionDAG/TargetLowering.cpp =================================================================== --- lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -37,7 +37,7 @@ /// NOTE: The TargetMachine owns TLOF. TargetLowering::TargetLowering(const TargetMachine &tm) - : TargetLoweringBase(tm) {} + : TargetLoweringBase(tm) {} const char *TargetLowering::getTargetNodeName(unsigned Opcode) const { return nullptr; @@ -57,7 +57,8 @@ // the return. Ignore noalias because it doesn't affect the call sequence. AttributeSet CallerAttrs = F->getAttributes(); if (AttrBuilder(CallerAttrs, AttributeSet::ReturnIndex) - .removeAttribute(Attribute::NoAlias).hasAttributes()) + .removeAttribute(Attribute::NoAlias) + .hasAttributes()) return false; // It's not safe to eliminate the sign / zero extension of the return value. @@ -69,8 +70,8 @@ return isUsedByReturnOnly(Node, Chain); } -bool TargetLowering::parametersInCSRMatch(const MachineRegisterInfo &MRI, - const uint32_t *CallerPreservedMask, +bool TargetLowering::parametersInCSRMatch( + const MachineRegisterInfo &MRI, const uint32_t *CallerPreservedMask, const SmallVectorImpl &ArgLocs, const SmallVectorImpl &OutVals) const { for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) { @@ -98,17 +99,17 @@ /// and called function attributes. void TargetLowering::ArgListEntry::setAttributes(ImmutableCallSite *CS, unsigned AttrIdx) { - isSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt); - isZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt); - isInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg); - isSRet = CS->paramHasAttr(AttrIdx, Attribute::StructRet); - isNest = CS->paramHasAttr(AttrIdx, Attribute::Nest); - isByVal = CS->paramHasAttr(AttrIdx, Attribute::ByVal); + isSExt = CS->paramHasAttr(AttrIdx, Attribute::SExt); + isZExt = CS->paramHasAttr(AttrIdx, Attribute::ZExt); + isInReg = CS->paramHasAttr(AttrIdx, Attribute::InReg); + isSRet = CS->paramHasAttr(AttrIdx, Attribute::StructRet); + isNest = CS->paramHasAttr(AttrIdx, Attribute::Nest); + isByVal = CS->paramHasAttr(AttrIdx, Attribute::ByVal); isInAlloca = CS->paramHasAttr(AttrIdx, Attribute::InAlloca); isReturned = CS->paramHasAttr(AttrIdx, Attribute::Returned); isSwiftSelf = CS->paramHasAttr(AttrIdx, Attribute::SwiftSelf); isSwiftError = CS->paramHasAttr(AttrIdx, Attribute::SwiftError); - Alignment = CS->getParamAlignment(AttrIdx); + Alignment = CS->getParamAlignment(AttrIdx); } /// Generate a libcall taking the given operands as arguments and returning a @@ -138,10 +139,13 @@ Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); TargetLowering::CallLoweringInfo CLI(DAG); bool signExtend = shouldSignExtendTypeInLibCall(RetVT, isSigned); - CLI.setDebugLoc(dl).setChain(DAG.getEntryNode()) - .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args)) - .setNoReturn(doesNotReturn).setDiscardResult(!isReturnValueUsed) - .setSExtResult(signExtend).setZExtResult(!signExtend); + CLI.setDebugLoc(dl) + .setChain(DAG.getEntryNode()) + .setCallee(getLibcallCallingConv(LC), RetTy, Callee, std::move(Args)) + .setNoReturn(doesNotReturn) + .setDiscardResult(!isReturnValueUsed) + .setSExtResult(signExtend) + .setZExtResult(!signExtend); return LowerCallTo(CLI); } @@ -151,8 +155,9 @@ SDValue &NewLHS, SDValue &NewRHS, ISD::CondCode &CCCode, const SDLoc &dl) const { - assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || VT == MVT::ppcf128) - && "Unsupported setcc type!"); + assert((VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128 || + VT == MVT::ppcf128) && + "Unsupported setcc type!"); // Expand into one or more soft-fp libcall(s). RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL; @@ -160,100 +165,133 @@ switch (CCCode) { case ISD::SETEQ: case ISD::SETOEQ: - LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : - (VT == MVT::f64) ? RTLIB::OEQ_F64 : - (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128; + LC1 = (VT == MVT::f32) + ? RTLIB::OEQ_F32 + : (VT == MVT::f64) + ? RTLIB::OEQ_F64 + : (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128; break; case ISD::SETNE: case ISD::SETUNE: - LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : - (VT == MVT::f64) ? RTLIB::UNE_F64 : - (VT == MVT::f128) ? RTLIB::UNE_F128 : RTLIB::UNE_PPCF128; + LC1 = (VT == MVT::f32) + ? RTLIB::UNE_F32 + : (VT == MVT::f64) + ? RTLIB::UNE_F64 + : (VT == MVT::f128) ? RTLIB::UNE_F128 : RTLIB::UNE_PPCF128; break; case ISD::SETGE: case ISD::SETOGE: - LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : - (VT == MVT::f64) ? RTLIB::OGE_F64 : - (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128; + LC1 = (VT == MVT::f32) + ? RTLIB::OGE_F32 + : (VT == MVT::f64) + ? RTLIB::OGE_F64 + : (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128; break; case ISD::SETLT: case ISD::SETOLT: - LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : - (VT == MVT::f64) ? RTLIB::OLT_F64 : - (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128; + LC1 = (VT == MVT::f32) + ? RTLIB::OLT_F32 + : (VT == MVT::f64) + ? RTLIB::OLT_F64 + : (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128; break; case ISD::SETLE: case ISD::SETOLE: - LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : - (VT == MVT::f64) ? RTLIB::OLE_F64 : - (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128; + LC1 = (VT == MVT::f32) + ? RTLIB::OLE_F32 + : (VT == MVT::f64) + ? RTLIB::OLE_F64 + : (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128; break; case ISD::SETGT: case ISD::SETOGT: - LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : - (VT == MVT::f64) ? RTLIB::OGT_F64 : - (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128; + LC1 = (VT == MVT::f32) + ? RTLIB::OGT_F32 + : (VT == MVT::f64) + ? RTLIB::OGT_F64 + : (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128; break; case ISD::SETUO: - LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : - (VT == MVT::f64) ? RTLIB::UO_F64 : - (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128; + LC1 = (VT == MVT::f32) + ? RTLIB::UO_F32 + : (VT == MVT::f64) + ? RTLIB::UO_F64 + : (VT == MVT::f128) ? RTLIB::UO_F128 : RTLIB::UO_PPCF128; break; case ISD::SETO: - LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : - (VT == MVT::f64) ? RTLIB::O_F64 : - (VT == MVT::f128) ? RTLIB::O_F128 : RTLIB::O_PPCF128; + LC1 = (VT == MVT::f32) + ? RTLIB::O_F32 + : (VT == MVT::f64) + ? RTLIB::O_F64 + : (VT == MVT::f128) ? RTLIB::O_F128 : RTLIB::O_PPCF128; break; case ISD::SETONE: // SETONE = SETOLT | SETOGT - LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : - (VT == MVT::f64) ? RTLIB::OLT_F64 : - (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128; - LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : - (VT == MVT::f64) ? RTLIB::OGT_F64 : - (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128; + LC1 = (VT == MVT::f32) + ? RTLIB::OLT_F32 + : (VT == MVT::f64) + ? RTLIB::OLT_F64 + : (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128; + LC2 = (VT == MVT::f32) + ? RTLIB::OGT_F32 + : (VT == MVT::f64) + ? RTLIB::OGT_F64 + : (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128; break; case ISD::SETUEQ: - LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : - (VT == MVT::f64) ? RTLIB::UO_F64 : - (VT == MVT::f128) ? RTLIB::UO_F64 : RTLIB::UO_PPCF128; - LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : - (VT == MVT::f64) ? RTLIB::OEQ_F64 : - (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128; + LC1 = (VT == MVT::f32) + ? RTLIB::UO_F32 + : (VT == MVT::f64) + ? RTLIB::UO_F64 + : (VT == MVT::f128) ? RTLIB::UO_F64 : RTLIB::UO_PPCF128; + LC2 = (VT == MVT::f32) + ? RTLIB::OEQ_F32 + : (VT == MVT::f64) + ? RTLIB::OEQ_F64 + : (VT == MVT::f128) ? RTLIB::OEQ_F128 : RTLIB::OEQ_PPCF128; break; default: // Invert CC for unordered comparisons ShouldInvertCC = true; switch (CCCode) { case ISD::SETULT: - LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : - (VT == MVT::f64) ? RTLIB::OGE_F64 : - (VT == MVT::f128) ? RTLIB::OGE_F128 : RTLIB::OGE_PPCF128; + LC1 = (VT == MVT::f32) + ? RTLIB::OGE_F32 + : (VT == MVT::f64) ? RTLIB::OGE_F64 + : (VT == MVT::f128) ? RTLIB::OGE_F128 + : RTLIB::OGE_PPCF128; break; case ISD::SETULE: - LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : - (VT == MVT::f64) ? RTLIB::OGT_F64 : - (VT == MVT::f128) ? RTLIB::OGT_F128 : RTLIB::OGT_PPCF128; + LC1 = (VT == MVT::f32) + ? RTLIB::OGT_F32 + : (VT == MVT::f64) ? RTLIB::OGT_F64 + : (VT == MVT::f128) ? RTLIB::OGT_F128 + : RTLIB::OGT_PPCF128; break; case ISD::SETUGT: - LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : - (VT == MVT::f64) ? RTLIB::OLE_F64 : - (VT == MVT::f128) ? RTLIB::OLE_F128 : RTLIB::OLE_PPCF128; + LC1 = (VT == MVT::f32) + ? RTLIB::OLE_F32 + : (VT == MVT::f64) ? RTLIB::OLE_F64 + : (VT == MVT::f128) ? RTLIB::OLE_F128 + : RTLIB::OLE_PPCF128; break; case ISD::SETUGE: - LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : - (VT == MVT::f64) ? RTLIB::OLT_F64 : - (VT == MVT::f128) ? RTLIB::OLT_F128 : RTLIB::OLT_PPCF128; + LC1 = (VT == MVT::f32) + ? RTLIB::OLT_F32 + : (VT == MVT::f64) ? RTLIB::OLT_F64 + : (VT == MVT::f128) ? RTLIB::OLT_F128 + : RTLIB::OLT_PPCF128; break; - default: llvm_unreachable("Do not know how to soften this setcc!"); + default: + llvm_unreachable("Do not know how to soften this setcc!"); } } // Use the target specific return value for comparions lib calls. EVT RetVT = getCmpLibcallReturnType(); SDValue Ops[2] = {NewLHS, NewRHS}; - NewLHS = makeLibCall(DAG, LC1, RetVT, Ops, false /*sign irrelevant*/, - dl).first; + NewLHS = + makeLibCall(DAG, LC1, RetVT, Ops, false /*sign irrelevant*/, dl).first; NewRHS = DAG.getConstant(0, dl, RetVT); CCCode = getCmpLibcallCC(LC1); @@ -265,8 +303,8 @@ ISD::SETCC, dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT), NewLHS, NewRHS, DAG.getCondCode(CCCode)); - NewLHS = makeLibCall(DAG, LC2, RetVT, Ops, false/*sign irrelevant*/, - dl).first; + NewLHS = + makeLibCall(DAG, LC2, RetVT, Ops, false /*sign irrelevant*/, dl).first; NewLHS = DAG.getNode( ISD::SETCC, dl, getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), RetVT), @@ -279,8 +317,10 @@ /// Return the entry encoding for a jump table in the current function. The /// returned value is a member of the MachineJumpTableInfo::JTEntryKind enum. unsigned TargetLowering::getJumpTableEncoding() const { - // In non-pic modes, just use the address of a block. - if (!isPositionIndependent()) + const TargetMachine &TM = getTargetMachine(); + + // In non-pic modes and large code models, just use the address of a block. + if (!isPositionIndependent() || TM.getCodeModel() == CodeModel::Large) return MachineJumpTableInfo::EK_BlockAddress; // In PIC mode, if the target supports a GPRel32 directive, use it. @@ -305,15 +345,13 @@ /// This returns the relocation base for the given PIC jumptable, the same as /// getPICJumpTableRelocBase, but as an MCExpr. -const MCExpr * -TargetLowering::getPICJumpTableRelocBaseExpr(const MachineFunction *MF, - unsigned JTI,MCContext &Ctx) const{ +const MCExpr *TargetLowering::getPICJumpTableRelocBaseExpr( + const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const { // The normal PIC reloc base is the label at the start of the jump table. return MCSymbolRefExpr::create(MF->getJTISymbol(JTI, Ctx), Ctx); } -bool -TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { +bool TargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { const TargetMachine &TM = getTargetMachine(); const GlobalValue *GV = GA->getGlobal(); @@ -337,18 +375,20 @@ /// Check to see if the specified operand of the specified instruction is a /// constant integer. If so, check to see if there are any bits set in the /// constant that are not demanded. If so, shrink the constant and return true. -bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op, - const APInt &Demanded) { +bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant( + SDValue Op, const APInt &Demanded) { SDLoc dl(Op); // FIXME: ISD::SELECT, ISD::SELECT_CC switch (Op.getOpcode()) { - default: break; + default: + break; case ISD::XOR: case ISD::AND: case ISD::OR: { ConstantSDNode *C = dyn_cast(Op.getOperand(1)); - if (!C) return false; + if (!C) + return false; if (Op.getOpcode() == ISD::XOR && (C->getAPIntValue() | (~Demanded)).isAllOnesValue()) @@ -357,10 +397,9 @@ // if we can expand it to have all bits set, do it if (C->getAPIntValue().intersects(~Demanded)) { EVT VT = Op.getValueType(); - SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), - DAG.getConstant(Demanded & - C->getAPIntValue(), - dl, VT)); + SDValue New = + DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), + DAG.getConstant(Demanded & C->getAPIntValue(), dl, VT)); return CombineTo(Op, New); } @@ -404,14 +443,13 @@ if (TLI.isTruncateFree(Op.getValueType(), SmallVT) && TLI.isZExtFree(SmallVT, Op.getValueType())) { // We found a type with free casts. - SDValue X = DAG.getNode(Op.getOpcode(), dl, SmallVT, - DAG.getNode(ISD::TRUNCATE, dl, SmallVT, - Op.getNode()->getOperand(0)), - DAG.getNode(ISD::TRUNCATE, dl, SmallVT, - Op.getNode()->getOperand(1))); + SDValue X = DAG.getNode( + Op.getOpcode(), dl, SmallVT, + DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getNode()->getOperand(0)), + DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getNode()->getOperand(1))); bool NeedZext = DemandedSize > SmallVTBits; - SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND, - dl, Op.getValueType(), X); + SDValue Z = DAG.getNode(NeedZext ? ISD::ZERO_EXTEND : ISD::ANY_EXTEND, dl, + Op.getValueType(), X); return CombineTo(Op, Z); } } @@ -425,10 +463,8 @@ /// return a mask of KnownOne and KnownZero bits for the expression (used to /// simplify the caller). The KnownZero/One bits may only be accurate for those /// bits in the DemandedMask. -bool TargetLowering::SimplifyDemandedBits(SDValue Op, - const APInt &DemandedMask, - APInt &KnownZero, - APInt &KnownOne, +bool TargetLowering::SimplifyDemandedBits(SDValue Op, const APInt &DemandedMask, + APInt &KnownZero, APInt &KnownOne, TargetLoweringOpt &TLO, unsigned Depth) const { unsigned BitWidth = DemandedMask.getBitWidth(); @@ -457,7 +493,7 @@ if (!Op.isUndef()) return TLO.CombineTo(Op, TLO.DAG.getUNDEF(Op.getValueType())); return false; - } else if (Depth == 6) { // Limit search depth. + } else if (Depth == 6) { // Limit search depth. return false; } @@ -467,7 +503,7 @@ // We know all of the bits for a constant! KnownOne = cast(Op)->getAPIntValue(); KnownZero = ~KnownOne; - return false; // Don't fall through, will infinitely loop. + return false; // Don't fall through, will infinitely loop. case ISD::AND: // If the RHS is a constant, check to see if the LHS would be zero without // using the bits from the RHS. Below, we use knowledge about the RHS to @@ -486,12 +522,12 @@ return true; } - if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, - KnownOne, TLO, Depth+1)) + if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, KnownOne, + TLO, Depth + 1)) return true; assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); - if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, - KnownZero2, KnownOne2, TLO, Depth+1)) + if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, KnownZero2, + KnownOne2, TLO, Depth + 1)) return true; assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); @@ -502,7 +538,7 @@ if ((NewMask & ~KnownZero & KnownOne2) == (~KnownZero & NewMask)) return TLO.CombineTo(Op, Op.getOperand(1)); // If all of the demanded bits in the inputs are known zeros, return zero. - if ((NewMask & (KnownZero|KnownZero2)) == NewMask) + if ((NewMask & (KnownZero | KnownZero2)) == NewMask) return TLO.CombineTo(Op, TLO.DAG.getConstant(0, dl, Op.getValueType())); // If the RHS is a constant, see if we can simplify it. if (TLO.ShrinkDemandedConstant(Op, ~KnownZero2 & NewMask)) @@ -517,12 +553,12 @@ KnownZero |= KnownZero2; break; case ISD::OR: - if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, - KnownOne, TLO, Depth+1)) + if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, KnownOne, + TLO, Depth + 1)) return true; assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); - if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, - KnownZero2, KnownOne2, TLO, Depth+1)) + if (SimplifyDemandedBits(Op.getOperand(0), ~KnownOne & NewMask, KnownZero2, + KnownOne2, TLO, Depth + 1)) return true; assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); @@ -551,12 +587,12 @@ KnownOne |= KnownOne2; break; case ISD::XOR: - if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, - KnownOne, TLO, Depth+1)) + if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, KnownOne, + TLO, Depth + 1)) return true; assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); - if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, - KnownOne2, TLO, Depth+1)) + if (SimplifyDemandedBits(Op.getOperand(0), NewMask, KnownZero2, KnownOne2, + TLO, Depth + 1)) return true; assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); @@ -574,9 +610,9 @@ // (but not both) turn this into an *inclusive* or. // e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0 if ((NewMask & ~KnownZero & ~KnownZero2) == 0) - return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), - Op.getOperand(0), - Op.getOperand(1))); + return TLO.CombineTo(Op, + TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(), + Op.getOperand(0), Op.getOperand(1))); // Output known-0 bits are known if clear or set in both the LHS & RHS. KnownZeroOut = (KnownZero & KnownZero2) | (KnownOne & KnownOne2); @@ -588,12 +624,13 @@ // into an AND, as we know the bits will be cleared. // e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2 // NB: it is okay if more bits are known than are requested - if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known on one side + if ((NewMask & (KnownZero | KnownOne)) == + NewMask) { // all known on one side if (KnownOne == KnownOne2) { // set bits are the same on both sides EVT VT = Op.getValueType(); SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, dl, VT); - return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT, - Op.getOperand(0), ANDC)); + return TLO.CombineTo( + Op, TLO.DAG.getNode(ISD::AND, dl, VT, Op.getOperand(0), ANDC)); } } @@ -606,8 +643,9 @@ if (Expanded.isAllOnesValue()) { if (Expanded != C->getAPIntValue()) { EVT VT = Op.getValueType(); - SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0), - TLO.DAG.getConstant(Expanded, dl, VT)); + SDValue New = + TLO.DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), + TLO.DAG.getConstant(Expanded, dl, VT)); return TLO.CombineTo(Op, New); } // if it already has all the bits set, nothing to change @@ -618,14 +656,14 @@ } KnownZero = KnownZeroOut; - KnownOne = KnownOneOut; + KnownOne = KnownOneOut; break; case ISD::SELECT: - if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, - KnownOne, TLO, Depth+1)) + if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero, KnownOne, + TLO, Depth + 1)) return true; - if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, - KnownOne2, TLO, Depth+1)) + if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero2, KnownOne2, + TLO, Depth + 1)) return true; assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); @@ -639,11 +677,11 @@ KnownZero &= KnownZero2; break; case ISD::SELECT_CC: - if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, - KnownOne, TLO, Depth+1)) + if (SimplifyDemandedBits(Op.getOperand(3), NewMask, KnownZero, KnownOne, + TLO, Depth + 1)) return true; - if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, - KnownOne2, TLO, Depth+1)) + if (SimplifyDemandedBits(Op.getOperand(2), NewMask, KnownZero2, KnownOne2, + TLO, Depth + 1)) return true; assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); @@ -671,24 +709,25 @@ if (InOp.getOpcode() == ISD::SRL && isa(InOp.getOperand(1))) { if (ShAmt && (NewMask & APInt::getLowBitsSet(BitWidth, ShAmt)) == 0) { - unsigned C1= cast(InOp.getOperand(1))->getZExtValue(); + unsigned C1 = + cast(InOp.getOperand(1))->getZExtValue(); unsigned Opc = ISD::SHL; - int Diff = ShAmt-C1; + int Diff = ShAmt - C1; if (Diff < 0) { Diff = -Diff; Opc = ISD::SRL; } SDValue NewSA = - TLO.DAG.getConstant(Diff, dl, Op.getOperand(1).getValueType()); + TLO.DAG.getConstant(Diff, dl, Op.getOperand(1).getValueType()); EVT VT = Op.getValueType(); - return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, - InOp.getOperand(0), NewSA)); + return TLO.CombineTo( + Op, TLO.DAG.getNode(Opc, dl, VT, InOp.getOperand(0), NewSA)); } } - if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt), - KnownZero, KnownOne, TLO, Depth+1)) + if (SimplifyDemandedBits(InOp, NewMask.lshr(ShAmt), KnownZero, KnownOne, + TLO, Depth + 1)) return true; // Convert (shl (anyext x, c)) to (anyext (shl x, c)) if the high bits @@ -703,42 +742,37 @@ if (!APInt(BitWidth, ShAmt).isIntN(ShTy.getSizeInBits())) ShTy = InnerVT; SDValue NarrowShl = - TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, - TLO.DAG.getConstant(ShAmt, dl, ShTy)); - return - TLO.CombineTo(Op, - TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), - NarrowShl)); + TLO.DAG.getNode(ISD::SHL, dl, InnerVT, InnerOp, + TLO.DAG.getConstant(ShAmt, dl, ShTy)); + return TLO.CombineTo(Op, + TLO.DAG.getNode(ISD::ANY_EXTEND, dl, + Op.getValueType(), NarrowShl)); } // Repeat the SHL optimization above in cases where an extension // intervenes: (shl (anyext (shr x, c1)), c2) to // (shl (anyext x), c2-c1). This requires that the bottom c1 bits // aren't demanded (as above) and that the shifted upper c1 bits of // x aren't demanded. - if (InOp.hasOneUse() && - InnerOp.getOpcode() == ISD::SRL && - InnerOp.hasOneUse() && - isa(InnerOp.getOperand(1))) { - uint64_t InnerShAmt = cast(InnerOp.getOperand(1)) - ->getZExtValue(); - if (InnerShAmt < ShAmt && - InnerShAmt < InnerBits && + if (InOp.hasOneUse() && InnerOp.getOpcode() == ISD::SRL && + InnerOp.hasOneUse() && isa(InnerOp.getOperand(1))) { + uint64_t InnerShAmt = + cast(InnerOp.getOperand(1))->getZExtValue(); + if (InnerShAmt < ShAmt && InnerShAmt < InnerBits && NewMask.lshr(InnerBits - InnerShAmt + ShAmt) == 0 && NewMask.trunc(ShAmt) == 0) { - SDValue NewSA = - TLO.DAG.getConstant(ShAmt - InnerShAmt, dl, - Op.getOperand(1).getValueType()); + SDValue NewSA = TLO.DAG.getConstant( + ShAmt - InnerShAmt, dl, Op.getOperand(1).getValueType()); EVT VT = Op.getValueType(); - SDValue NewExt = TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, - InnerOp.getOperand(0)); - return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, VT, - NewExt, NewSA)); + SDValue NewExt = + TLO.DAG.getNode(ISD::ANY_EXTEND, dl, VT, InnerOp.getOperand(0)); + return TLO.CombineTo( + Op, TLO.DAG.getNode(ISD::SHL, dl, VT, NewExt, NewSA)); } } } KnownZero <<= SA->getZExtValue(); - KnownOne <<= SA->getZExtValue(); + KnownOne <<= SA->getZExtValue(); // low bits known zero. KnownZero |= APInt::getLowBitsSet(BitWidth, SA->getZExtValue()); } @@ -767,31 +801,32 @@ if (InOp.getOpcode() == ISD::SHL && isa(InOp.getOperand(1))) { if (ShAmt && (NewMask & APInt::getHighBitsSet(VTSize, ShAmt)) == 0) { - unsigned C1= cast(InOp.getOperand(1))->getZExtValue(); + unsigned C1 = + cast(InOp.getOperand(1))->getZExtValue(); unsigned Opc = ISD::SRL; - int Diff = ShAmt-C1; + int Diff = ShAmt - C1; if (Diff < 0) { Diff = -Diff; Opc = ISD::SHL; } SDValue NewSA = - TLO.DAG.getConstant(Diff, dl, Op.getOperand(1).getValueType()); - return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT, - InOp.getOperand(0), NewSA)); + TLO.DAG.getConstant(Diff, dl, Op.getOperand(1).getValueType()); + return TLO.CombineTo( + Op, TLO.DAG.getNode(Opc, dl, VT, InOp.getOperand(0), NewSA)); } } // Compute the new bits that are at the top now. - if (SimplifyDemandedBits(InOp, InDemandedMask, - KnownZero, KnownOne, TLO, Depth+1)) + if (SimplifyDemandedBits(InOp, InDemandedMask, KnownZero, KnownOne, TLO, + Depth + 1)) return true; assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); KnownZero = KnownZero.lshr(ShAmt); - KnownOne = KnownOne.lshr(ShAmt); + KnownOne = KnownOne.lshr(ShAmt); APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); - KnownZero |= HighBits; // High bits known zero. + KnownZero |= HighBits; // High bits known zero. } break; case ISD::SRA: @@ -825,12 +860,12 @@ if (HighBits.intersects(NewMask)) InDemandedMask |= APInt::getSignBit(VT.getScalarType().getSizeInBits()); - if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, - KnownZero, KnownOne, TLO, Depth+1)) + if (SimplifyDemandedBits(Op.getOperand(0), InDemandedMask, KnownZero, + KnownOne, TLO, Depth + 1)) return true; assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); KnownZero = KnownZero.lshr(ShAmt); - KnownOne = KnownOne.lshr(ShAmt); + KnownOne = KnownOne.lshr(ShAmt); // Handle the sign bit, adjusted to where it is now in the mask. APInt SignBit = APInt::getSignBit(BitWidth).lshr(ShAmt); @@ -848,11 +883,10 @@ int Log2 = NewMask.exactLogBase2(); if (Log2 >= 0) { // The bit must come from the sign. - SDValue NewSA = - TLO.DAG.getConstant(BitWidth - 1 - Log2, dl, - Op.getOperand(1).getValueType()); - return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, VT, - Op.getOperand(0), NewSA)); + SDValue NewSA = TLO.DAG.getConstant(BitWidth - 1 - Log2, dl, + Op.getOperand(1).getValueType()); + return TLO.CombineTo( + Op, TLO.DAG.getNode(ISD::SRL, dl, VT, Op.getOperand(0), NewSA)); } if (KnownOne.intersects(SignBit)) @@ -870,7 +904,7 @@ SDValue InOp = Op.getOperand(0); unsigned VTBits = Op->getValueType(0).getScalarType().getSizeInBits(); bool AlreadySignExtended = - TLO.DAG.ComputeNumSignBits(InOp) >= VTBits-ShAmt+1; + TLO.DAG.ComputeNumSignBits(InOp) >= VTBits - ShAmt + 1; // However if the input is already sign extended we expect the sign // extension to be dropped altogether later and do not simplify. if (!AlreadySignExtended) { @@ -880,37 +914,35 @@ if (TLO.LegalTypes() && !ShiftAmtTy.isVector()) ShiftAmtTy = getShiftAmountTy(ShiftAmtTy, DL); - SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, dl, - ShiftAmtTy); - return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, - Op.getValueType(), InOp, - ShiftAmt)); + SDValue ShiftAmt = + TLO.DAG.getConstant(BitWidth - ShAmt, dl, ShiftAmtTy); + return TLO.CombineTo( + Op, + TLO.DAG.getNode(ISD::SHL, dl, Op.getValueType(), InOp, ShiftAmt)); } } // Sign extension. Compute the demanded bits in the result that are not // present in the input. - APInt NewBits = - APInt::getHighBitsSet(BitWidth, - BitWidth - ExVT.getScalarType().getSizeInBits()); + APInt NewBits = APInt::getHighBitsSet( + BitWidth, BitWidth - ExVT.getScalarType().getSizeInBits()); // If none of the extended bits are demanded, eliminate the sextinreg. if ((NewBits & NewMask) == 0) return TLO.CombineTo(Op, Op.getOperand(0)); APInt InSignBit = - APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth); + APInt::getSignBit(ExVT.getScalarType().getSizeInBits()).zext(BitWidth); APInt InputDemandedBits = - APInt::getLowBitsSet(BitWidth, - ExVT.getScalarType().getSizeInBits()) & - NewMask; + APInt::getLowBitsSet(BitWidth, ExVT.getScalarType().getSizeInBits()) & + NewMask; // Since the sign extended bits are demanded, we know that the sign // bit is demanded. InputDemandedBits |= InSignBit; - if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, - KnownZero, KnownOne, TLO, Depth+1)) + if (SimplifyDemandedBits(Op.getOperand(0), InputDemandedBits, KnownZero, + KnownOne, TLO, Depth + 1)) return true; assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); @@ -919,13 +951,13 @@ // If the input sign bit is known zero, convert this into a zero extension. if (KnownZero.intersects(InSignBit)) - return TLO.CombineTo(Op, - TLO.DAG.getZeroExtendInReg(Op.getOperand(0),dl,ExVT)); + return TLO.CombineTo( + Op, TLO.DAG.getZeroExtendInReg(Op.getOperand(0), dl, ExVT)); - if (KnownOne.intersects(InSignBit)) { // Input sign bit known set + if (KnownOne.intersects(InSignBit)) { // Input sign bit known set KnownOne |= NewBits; KnownZero &= ~NewBits; - } else { // Input sign bit unknown + } else { // Input sign bit unknown KnownZero &= ~NewBits; KnownOne &= ~NewBits; } @@ -941,36 +973,36 @@ APInt KnownZeroLo, KnownOneLo; APInt KnownZeroHi, KnownOneHi; - if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownZeroLo, - KnownOneLo, TLO, Depth + 1)) + if (SimplifyDemandedBits(Op.getOperand(0), MaskLo, KnownZeroLo, KnownOneLo, + TLO, Depth + 1)) return true; - if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownZeroHi, - KnownOneHi, TLO, Depth + 1)) + if (SimplifyDemandedBits(Op.getOperand(1), MaskHi, KnownZeroHi, KnownOneHi, + TLO, Depth + 1)) return true; KnownZero = KnownZeroLo.zext(BitWidth) | KnownZeroHi.zext(BitWidth).shl(HalfBitWidth); - KnownOne = KnownOneLo.zext(BitWidth) | - KnownOneHi.zext(BitWidth).shl(HalfBitWidth); + KnownOne = + KnownOneLo.zext(BitWidth) | KnownOneHi.zext(BitWidth).shl(HalfBitWidth); break; } case ISD::ZERO_EXTEND: { unsigned OperandBitWidth = - Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); + Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); APInt InMask = NewMask.trunc(OperandBitWidth); // If none of the top bits are demanded, convert this into an any_extend. APInt NewBits = - APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; + APInt::getHighBitsSet(BitWidth, BitWidth - OperandBitWidth) & NewMask; if (!NewBits.intersects(NewMask)) return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), Op.getOperand(0))); - if (SimplifyDemandedBits(Op.getOperand(0), InMask, - KnownZero, KnownOne, TLO, Depth+1)) + if (SimplifyDemandedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, TLO, + Depth + 1)) return true; assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); KnownZero = KnownZero.zext(BitWidth); @@ -981,15 +1013,15 @@ case ISD::SIGN_EXTEND: { EVT InVT = Op.getOperand(0).getValueType(); unsigned InBits = InVT.getScalarType().getSizeInBits(); - APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); + APInt InMask = APInt::getLowBitsSet(BitWidth, InBits); APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits); - APInt NewBits = ~InMask & NewMask; + APInt NewBits = ~InMask & NewMask; // If none of the top bits are demanded, convert this into an any_extend. if (NewBits == 0) - return TLO.CombineTo(Op,TLO.DAG.getNode(ISD::ANY_EXTEND, dl, - Op.getValueType(), - Op.getOperand(0))); + return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ANY_EXTEND, dl, + Op.getValueType(), + Op.getOperand(0))); // Since some of the sign extended bits are demanded, we know that the sign // bit is demanded. @@ -998,7 +1030,7 @@ InDemandedBits = InDemandedBits.trunc(InBits); if (SimplifyDemandedBits(Op.getOperand(0), InDemandedBits, KnownZero, - KnownOne, TLO, Depth+1)) + KnownOne, TLO, Depth + 1)) return true; KnownZero = KnownZero.zext(BitWidth); KnownOne = KnownOne.zext(BitWidth); @@ -1013,7 +1045,7 @@ if (KnownOne.intersects(InSignBit)) { KnownOne |= NewBits; assert((KnownZero & NewBits) == 0); - } else { // Otherwise, top bits aren't known. + } else { // Otherwise, top bits aren't known. assert((KnownOne & NewBits) == 0); assert((KnownZero & NewBits) == 0); } @@ -1021,10 +1053,10 @@ } case ISD::ANY_EXTEND: { unsigned OperandBitWidth = - Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); + Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); APInt InMask = NewMask.trunc(OperandBitWidth); - if (SimplifyDemandedBits(Op.getOperand(0), InMask, - KnownZero, KnownOne, TLO, Depth+1)) + if (SimplifyDemandedBits(Op.getOperand(0), InMask, KnownZero, KnownOne, TLO, + Depth + 1)) return true; assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); KnownZero = KnownZero.zext(BitWidth); @@ -1035,10 +1067,10 @@ // Simplify the input, using demanded bit information, and compute the known // zero/one bits live out. unsigned OperandBitWidth = - Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); + Op.getOperand(0).getValueType().getScalarType().getSizeInBits(); APInt TruncMask = NewMask.zext(OperandBitWidth); - if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, - KnownZero, KnownOne, TLO, Depth+1)) + if (SimplifyDemandedBits(Op.getOperand(0), TruncMask, KnownZero, KnownOne, + TLO, Depth + 1)) return true; KnownZero = KnownZero.trunc(BitWidth); KnownOne = KnownOne.trunc(BitWidth); @@ -1048,7 +1080,8 @@ if (Op.getOperand(0).getNode()->hasOneUse()) { SDValue In = Op.getOperand(0); switch (In.getOpcode()) { - default: break; + default: + break; case ISD::SRL: // Shrink SRL by a constant if none of the high bits shifted in are // demanded. @@ -1067,20 +1100,18 @@ getShiftAmountTy(Op.getValueType(), DL)); } - APInt HighBits = APInt::getHighBitsSet(OperandBitWidth, - OperandBitWidth - BitWidth); + APInt HighBits = + APInt::getHighBitsSet(OperandBitWidth, OperandBitWidth - BitWidth); HighBits = HighBits.lshr(ShAmt->getZExtValue()).trunc(BitWidth); if (ShAmt->getZExtValue() < BitWidth && !(HighBits & NewMask)) { // None of the shifted in bits are needed. Add a truncate of the // shift input, then shift it. - SDValue NewTrunc = TLO.DAG.getNode(ISD::TRUNCATE, dl, - Op.getValueType(), - In.getOperand(0)); - return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SRL, dl, - Op.getValueType(), - NewTrunc, - Shift)); + SDValue NewTrunc = TLO.DAG.getNode( + ISD::TRUNCATE, dl, Op.getValueType(), In.getOperand(0)); + return TLO.CombineTo(Op, + TLO.DAG.getNode(ISD::SRL, dl, Op.getValueType(), + NewTrunc, Shift)); } break; } @@ -1093,10 +1124,9 @@ // AssertZext demands all of the high bits, plus any of the low bits // demanded by its users. EVT VT = cast(Op.getOperand(1))->getVT(); - APInt InMask = APInt::getLowBitsSet(BitWidth, - VT.getSizeInBits()); - if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask, - KnownZero, KnownOne, TLO, Depth+1)) + APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); + if (SimplifyDemandedBits(Op.getOperand(0), ~InMask | NewMask, KnownZero, + KnownOne, TLO, Depth + 1)) return true; assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); @@ -1106,15 +1136,15 @@ case ISD::BITCAST: // If this is an FP->Int bitcast and if the sign bit is the only // thing demanded, turn this into a FGETSIGN. - if (!TLO.LegalOperations() && - !Op.getValueType().isVector() && + if (!TLO.LegalOperations() && !Op.getValueType().isVector() && !Op.getOperand(0).getValueType().isVector() && NewMask == APInt::getSignBit(Op.getValueType().getSizeInBits()) && Op.getOperand(0).getValueType().isFloatingPoint()) { - bool OpVTLegal = isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); - bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); + bool OpVTLegal = + isOperationLegalOrCustom(ISD::FGETSIGN, Op.getValueType()); + bool i32Legal = isOperationLegalOrCustom(ISD::FGETSIGN, MVT::i32); if ((OpVTLegal || i32Legal) && Op.getValueType().isSimple() && - Op.getOperand(0).getValueType() != MVT::f128) { + Op.getOperand(0).getValueType() != MVT::f128) { // Cannot eliminate/lower SHL for f128 yet. EVT Ty = OpVTLegal ? Op.getValueType() : MVT::i32; // Make a FGETSIGN + SHL to move the sign bit into the appropriate @@ -1123,11 +1153,10 @@ unsigned OpVTSizeInBits = Op.getValueType().getSizeInBits(); if (!OpVTLegal && OpVTSizeInBits > 32) Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); - unsigned ShVal = Op.getValueType().getSizeInBits()-1; + unsigned ShVal = Op.getValueType().getSizeInBits() - 1; SDValue ShAmt = TLO.DAG.getConstant(ShVal, dl, Op.getValueType()); - return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::SHL, dl, - Op.getValueType(), - Sign, ShAmt)); + return TLO.CombineTo( + Op, TLO.DAG.getNode(ISD::SHL, dl, Op.getValueType(), Sign, ShAmt)); } } break; @@ -1136,13 +1165,13 @@ case ISD::SUB: { // Add, Sub, and Mul don't demand any bits in positions beyond that // of the highest bit demanded of them. - APInt LoMask = APInt::getLowBitsSet(BitWidth, - BitWidth - NewMask.countLeadingZeros()); - if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, - KnownOne2, TLO, Depth+1)) + APInt LoMask = + APInt::getLowBitsSet(BitWidth, BitWidth - NewMask.countLeadingZeros()); + if (SimplifyDemandedBits(Op.getOperand(0), LoMask, KnownZero2, KnownOne2, + TLO, Depth + 1)) return true; - if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, - KnownOne2, TLO, Depth+1)) + if (SimplifyDemandedBits(Op.getOperand(1), LoMask, KnownZero2, KnownOne2, + TLO, Depth + 1)) return true; // See if the operation should be performed at a smaller bit width. if (TLO.ShrinkDemandedOp(Op, BitWidth, NewMask, dl)) @@ -1157,11 +1186,12 @@ // If we know the value of all of the demanded bits, return this as a // constant. - if ((NewMask & (KnownZero|KnownOne)) == NewMask) { + if ((NewMask & (KnownZero | KnownOne)) == NewMask) { // Avoid folding to a constant if any OpaqueConstant is involved. const SDNode *N = Op.getNode(); for (SDNodeIterator I = SDNodeIterator::begin(N), - E = SDNodeIterator::end(N); I != E; ++I) { + E = SDNodeIterator::end(N); + I != E; ++I) { SDNode *Op = *I; if (ConstantSDNode *C = dyn_cast(Op)) if (C->isOpaque()) @@ -1357,9 +1387,11 @@ // These setcc operations always fold. switch (Cond) { - default: break; + default: + break; case ISD::SETFALSE: - case ISD::SETFALSE2: return DAG.getConstant(0, dl, VT); + case ISD::SETFALSE2: + return DAG.getConstant(0, dl, VT); case ISD::SETTRUE: case ISD::SETTRUE2: { TargetLowering::BooleanContent Cnt = @@ -1387,8 +1419,8 @@ if (N0.getOpcode() == ISD::SRL && (C1 == 0 || C1 == 1) && N0.getOperand(0).getOpcode() == ISD::CTLZ && N0.getOperand(1).getOpcode() == ISD::Constant) { - const APInt &ShAmt - = cast(N0.getOperand(1))->getAPIntValue(); + const APInt &ShAmt = + cast(N0.getOperand(1))->getAPIntValue(); if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && ShAmt == Log2_32(N0.getValueType().getSizeInBits())) { if ((C1 == 0) == (Cond == ISD::SETEQ)) { @@ -1401,8 +1433,7 @@ Cond = ISD::SETEQ; } SDValue Zero = DAG.getConstant(0, dl, N0.getValueType()); - return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), - Zero, Cond); + return DAG.getSetCC(dl, VT, N0.getOperand(0).getOperand(0), Zero, Cond); } } @@ -1412,16 +1443,18 @@ CTPOP = N0.getOperand(0); if (CTPOP.hasOneUse() && CTPOP.getOpcode() == ISD::CTPOP && - (N0 == CTPOP || N0.getValueType().getSizeInBits() > - Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) { + (N0 == CTPOP || + N0.getValueType().getSizeInBits() > + Log2_32_Ceil(CTPOP.getValueType().getSizeInBits()))) { EVT CTVT = CTPOP.getValueType(); SDValue CTOp = CTPOP.getOperand(0); // (ctpop x) u< 2 -> (x & x-1) == 0 // (ctpop x) u> 1 -> (x & x-1) != 0 - if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ - SDValue Sub = DAG.getNode(ISD::SUB, dl, CTVT, CTOp, - DAG.getConstant(1, dl, CTVT)); + if ((Cond == ISD::SETULT && C1 == 2) || + (Cond == ISD::SETUGT && C1 == 1)) { + SDValue Sub = + DAG.getNode(ISD::SUB, dl, CTVT, CTOp, DAG.getConstant(1, dl, CTVT)); SDValue And = DAG.getNode(ISD::AND, dl, CTVT, CTOp, Sub); ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; return DAG.getSetCC(dl, VT, And, DAG.getConstant(0, dl, CTVT), CC); @@ -1432,8 +1465,8 @@ // (zext x) == C --> x == (trunc C) // (sext x) == C --> x == (trunc C) - if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && - DCI.isBeforeLegalize() && N0->hasOneUse()) { + if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && DCI.isBeforeLegalize() && + N0->hasOneUse()) { unsigned MinBits = N0.getValueSizeInBits(); SDValue PreExt; bool Signed = false; @@ -1444,7 +1477,7 @@ } else if (N0->getOpcode() == ISD::AND) { // DAGCombine turns costly ZExts into ANDs if (auto *C = dyn_cast(N0->getOperand(1))) - if ((C->getAPIntValue()+1).isPowerOf2()) { + if ((C->getAPIntValue() + 1).isPowerOf2()) { MinBits = C->getAPIntValue().countTrailingOnes(); PreExt = N0->getOperand(0); } @@ -1466,14 +1499,11 @@ } // Figure out how many bits we need to preserve this constant. - unsigned ReqdBits = Signed ? - C1.getBitWidth() - C1.getNumSignBits() + 1 : - C1.getActiveBits(); + unsigned ReqdBits = Signed ? C1.getBitWidth() - C1.getNumSignBits() + 1 + : C1.getActiveBits(); // Make sure we're not losing bits from the constant. - if (MinBits > 0 && - MinBits < C1.getBitWidth() && - MinBits >= ReqdBits) { + if (MinBits > 0 && MinBits < C1.getBitWidth() && MinBits >= ReqdBits) { EVT MinVT = EVT::getIntegerVT(*DAG.getContext(), MinBits); if (isTypeDesirableForOp(ISD::SETCC, MinVT)) { // Will get folded away. @@ -1513,9 +1543,7 @@ cast(TopSetCC.getOperand(2))->get(), TopSetCC.getOperand(0).getValueType().isInteger()); return DAG.getSetCC(dl, VT, TopSetCC.getOperand(0), - TopSetCC.getOperand(1), - InvCond); - + TopSetCC.getOperand(1), InvCond); } } } @@ -1523,10 +1551,8 @@ // If the LHS is '(and load, const)', the RHS is 0, // the test is for equality or unsigned, and all 1 bits of the const are // in the same partial word, see if we can shorten the load. - if (DCI.isBeforeLegalize() && - !ISD::isSignedIntSetCC(Cond) && - N0.getOpcode() == ISD::AND && C1 == 0 && - N0.getNode()->hasOneUse() && + if (DCI.isBeforeLegalize() && !ISD::isSignedIntSetCC(Cond) && + N0.getOpcode() == ISD::AND && C1 == 0 && N0.getNode()->hasOneUse() && isa(N0.getOperand(0)) && N0.getOperand(0).getNode()->hasOneUse() && isa(N0.getOperand(1))) { @@ -1541,16 +1567,16 @@ if (Lod->getExtensionType() != ISD::NON_EXTLOAD) origWidth = Lod->getMemoryVT().getSizeInBits(); const APInt &Mask = - cast(N0.getOperand(1))->getAPIntValue(); - for (unsigned width = origWidth / 2; width>=8; width /= 2) { + cast(N0.getOperand(1))->getAPIntValue(); + for (unsigned width = origWidth / 2; width >= 8; width /= 2) { APInt newMask = APInt::getLowBitsSet(maskWidth, width); - for (unsigned offset=0; offsetgetChain(), Ptr, Lod->getPointerInfo().getWithOffset(bestOffset), NewAlign); - return DAG.getSetCC(dl, VT, - DAG.getNode(ISD::AND, dl, newVT, NewLoad, - DAG.getConstant(bestMask.trunc(bestWidth), - dl, newVT)), - DAG.getConstant(0LL, dl, newVT), Cond); + return DAG.getSetCC( + dl, VT, DAG.getNode(ISD::AND, dl, newVT, NewLoad, + DAG.getConstant(bestMask.trunc(bestWidth), dl, + newVT)), + DAG.getConstant(0LL, dl, newVT), Cond); } } } @@ -1590,10 +1616,12 @@ switch (Cond) { case ISD::SETUGT: case ISD::SETUGE: - case ISD::SETEQ: return DAG.getConstant(0, dl, VT); + case ISD::SETEQ: + return DAG.getConstant(0, dl, VT); case ISD::SETULT: case ISD::SETULE: - case ISD::SETNE: return DAG.getConstant(1, dl, VT); + case ISD::SETNE: + return DAG.getConstant(1, dl, VT); case ISD::SETGT: case ISD::SETGE: // True if the sign bit of C1 is set. @@ -1623,14 +1651,14 @@ getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), newVT); SDValue NewConst = DAG.getConstant(C1.trunc(InSize), dl, newVT); - SDValue NewSetCC = DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0), - NewConst, Cond); + SDValue NewSetCC = + DAG.getSetCC(dl, NewSetCCVT, N0.getOperand(0), NewConst, Cond); return DAG.getBoolExtOrTrunc(NewSetCC, dl, VT, N0.getValueType()); } break; } default: - break; // todo, be more careful with signed comparisons + break; // todo, be more careful with signed comparisons } } else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG && (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { @@ -1651,22 +1679,21 @@ } else { APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); ZextOp = DAG.getNode(ISD::AND, dl, Op0Ty, N0.getOperand(0), - DAG.getConstant(Imm, dl, Op0Ty)); + DAG.getConstant(Imm, dl, Op0Ty)); } if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(ZextOp.getNode()); // Otherwise, make this a use of a zext. - return DAG.getSetCC(dl, VT, ZextOp, - DAG.getConstant(C1 & APInt::getLowBitsSet( - ExtDstTyBits, - ExtSrcTyBits), - dl, ExtDstTy), - Cond); + return DAG.getSetCC( + dl, VT, ZextOp, + DAG.getConstant(C1 & APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits), + dl, ExtDstTy), + Cond); } else if ((N1C->isNullValue() || N1C->getAPIntValue() == 1) && - (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { + (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC - if (N0.getOpcode() == ISD::SETCC && - isTypeLegal(VT) && VT.bitsLE(N0.getValueType())) { + if (N0.getOpcode() == ISD::SETCC && isTypeLegal(VT) && + VT.bitsLE(N0.getValueType())) { bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (N1C->getAPIntValue() != 1); if (TrueWhenTrue) return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); @@ -1688,20 +1715,18 @@ // If this is (X^1) == 0/1, swap the RHS and eliminate the xor. We // can only do this if the top bits are known zero. unsigned BitWidth = N0.getValueSizeInBits(); - if (DAG.MaskedValueIsZero(N0, - APInt::getHighBitsSet(BitWidth, - BitWidth-1))) { + if (DAG.MaskedValueIsZero( + N0, APInt::getHighBitsSet(BitWidth, BitWidth - 1))) { // Okay, get the un-inverted input value. SDValue Val; if (N0.getOpcode() == ISD::XOR) Val = N0.getOperand(0); else { assert(N0.getOpcode() == ISD::AND && - N0.getOperand(0).getOpcode() == ISD::XOR); + N0.getOperand(0).getOpcode() == ISD::XOR); // ((X^1)&1)^1 -> X & 1 Val = DAG.getNode(ISD::AND, dl, N0.getValueType(), - N0.getOperand(0).getOperand(0), - N0.getOperand(1)); + N0.getOperand(0).getOperand(0), N0.getOperand(1)); } return DAG.getSetCC(dl, VT, Val, N1, @@ -1728,13 +1753,15 @@ cast(Op0.getOperand(1))->getAPIntValue() == 1) { // If this is (X&1) == / != 1, normalize it to (X&1) != / == 0. if (Op0.getValueType().bitsGT(VT)) - Op0 = DAG.getNode(ISD::AND, dl, VT, - DAG.getNode(ISD::TRUNCATE, dl, VT, Op0.getOperand(0)), - DAG.getConstant(1, dl, VT)); + Op0 = + DAG.getNode(ISD::AND, dl, VT, DAG.getNode(ISD::TRUNCATE, dl, VT, + Op0.getOperand(0)), + DAG.getConstant(1, dl, VT)); else if (Op0.getValueType().bitsLT(VT)) - Op0 = DAG.getNode(ISD::AND, dl, VT, - DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), - DAG.getConstant(1, dl, VT)); + Op0 = DAG.getNode( + ISD::AND, dl, VT, + DAG.getNode(ISD::ANY_EXTEND, dl, VT, Op0.getOperand(0)), + DAG.getConstant(1, dl, VT)); return DAG.getSetCC(dl, VT, Op0, DAG.getConstant(0, dl, Op0.getValueType()), @@ -1760,7 +1787,8 @@ // Canonicalize GE/LE comparisons to use GT/LT comparisons. if (Cond == ISD::SETGE || Cond == ISD::SETUGE) { - if (C1 == MinVal) return DAG.getConstant(1, dl, VT); // X >= MIN --> true + if (C1 == MinVal) + return DAG.getConstant(1, dl, VT); // X >= MIN --> true // X >= C0 --> X > (C0 - 1) APInt C = C1 - 1; ISD::CondCode NewCC = (Cond == ISD::SETGE) ? ISD::SETGT : ISD::SETUGT; @@ -1769,13 +1797,13 @@ (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 && isLegalICmpImmediate(C.getSExtValue())))) { return DAG.getSetCC(dl, VT, N0, - DAG.getConstant(C, dl, N1.getValueType()), - NewCC); + DAG.getConstant(C, dl, N1.getValueType()), NewCC); } } if (Cond == ISD::SETLE || Cond == ISD::SETULE) { - if (C1 == MaxVal) return DAG.getConstant(1, dl, VT); // X <= MAX --> true + if (C1 == MaxVal) + return DAG.getConstant(1, dl, VT); // X <= MAX --> true // X <= C0 --> X < (C0 + 1) APInt C = C1 + 1; ISD::CondCode NewCC = (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT; @@ -1784,19 +1812,18 @@ (!N1C->isOpaque() || (N1C->isOpaque() && C.getBitWidth() <= 64 && isLegalICmpImmediate(C.getSExtValue())))) { return DAG.getSetCC(dl, VT, N0, - DAG.getConstant(C, dl, N1.getValueType()), - NewCC); + DAG.getConstant(C, dl, N1.getValueType()), NewCC); } } if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) - return DAG.getConstant(0, dl, VT); // X < MIN --> false + return DAG.getConstant(0, dl, VT); // X < MIN --> false if ((Cond == ISD::SETGE || Cond == ISD::SETUGE) && C1 == MinVal) - return DAG.getConstant(1, dl, VT); // X >= MIN --> true + return DAG.getConstant(1, dl, VT); // X >= MIN --> true if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal) - return DAG.getConstant(0, dl, VT); // X > MAX --> false + return DAG.getConstant(0, dl, VT); // X > MAX --> false if ((Cond == ISD::SETLE || Cond == ISD::SETULE) && C1 == MaxVal) - return DAG.getConstant(1, dl, VT); // X <= MAX --> true + return DAG.getConstant(1, dl, VT); // X <= MAX --> true // Canonicalize setgt X, Min --> setne X, Min if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MinVal) @@ -1806,12 +1833,12 @@ return DAG.getSetCC(dl, VT, N0, N1, ISD::SETNE); // If we have setult X, 1, turn it into seteq X, 0 - if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) + if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal + 1) return DAG.getSetCC(dl, VT, N0, DAG.getConstant(MinVal, dl, N0.getValueType()), ISD::SETEQ); // If we have setugt X, Max-1, turn it into seteq X, Max - if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal-1) + if ((Cond == ISD::SETGT || Cond == ISD::SETUGT) && C1 == MaxVal - 1) return DAG.getSetCC(dl, VT, N0, DAG.getConstant(MaxVal, dl, N0.getValueType()), ISD::SETEQ); @@ -1820,18 +1847,14 @@ // by changing cc. // SETUGT X, SINTMAX -> SETLT X, 0 - if (Cond == ISD::SETUGT && - C1 == APInt::getSignedMaxValue(OperandBitSize)) - return DAG.getSetCC(dl, VT, N0, - DAG.getConstant(0, dl, N1.getValueType()), + if (Cond == ISD::SETUGT && C1 == APInt::getSignedMaxValue(OperandBitSize)) + return DAG.getSetCC(dl, VT, N0, DAG.getConstant(0, dl, N1.getValueType()), ISD::SETLT); // SETULT X, SINTMIN -> SETGT X, -1 - if (Cond == ISD::SETULT && - C1 == APInt::getSignedMinValue(OperandBitSize)) { - SDValue ConstMinusOne = - DAG.getConstant(APInt::getAllOnesValue(OperandBitSize), dl, - N1.getValueType()); + if (Cond == ISD::SETULT && C1 == APInt::getSignedMinValue(OperandBitSize)) { + SDValue ConstMinusOne = DAG.getConstant( + APInt::getAllOnesValue(OperandBitSize), dl, N1.getValueType()); return DAG.getSetCC(dl, VT, N0, ConstMinusOne, ISD::SETGT); } @@ -1845,22 +1868,23 @@ EVT ShiftTy = DCI.isBeforeLegalize() ? getPointerTy(DL) : getShiftAmountTy(N0.getValueType(), DL); - if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3 + if (Cond == ISD::SETNE && C1 == 0) { // (X & 8) != 0 --> (X & 8) >> 3 // Perform the xform if the AND RHS is a single bit. if (AndRHS->getAPIntValue().isPowerOf2()) { - return DAG.getNode(ISD::TRUNCATE, dl, VT, - DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, - DAG.getConstant(AndRHS->getAPIntValue().logBase2(), dl, - ShiftTy))); + return DAG.getNode( + ISD::TRUNCATE, dl, VT, + DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, + DAG.getConstant(AndRHS->getAPIntValue().logBase2(), + dl, ShiftTy))); } } else if (Cond == ISD::SETEQ && C1 == AndRHS->getAPIntValue()) { // (X & 8) == 8 --> (X & 8) >> 3 // Perform the xform if C1 is a single bit. if (C1.isPowerOf2()) { - return DAG.getNode(ISD::TRUNCATE, dl, VT, - DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, - DAG.getConstant(C1.logBase2(), dl, - ShiftTy))); + return DAG.getNode( + ISD::TRUNCATE, dl, VT, + DAG.getNode(ISD::SRL, dl, N0.getValueType(), N0, + DAG.getConstant(C1.logBase2(), dl, ShiftTy))); } } } @@ -1880,9 +1904,9 @@ ? getPointerTy(DL) : getShiftAmountTy(N0.getValueType(), DL); EVT CmpTy = N0.getValueType(); - SDValue Shift = DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0), - DAG.getConstant(ShiftBits, dl, - ShiftTy)); + SDValue Shift = + DAG.getNode(ISD::SRL, dl, CmpTy, N0.getOperand(0), + DAG.getConstant(ShiftBits, dl, ShiftTy)); SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, CmpTy); return DAG.getSetCC(dl, VT, Shift, CmpRHS, Cond); } @@ -1906,7 +1930,7 @@ } NewC = NewC.lshr(ShiftBits); if (ShiftBits && NewC.getMinSignedBits() <= 64 && - isLegalICmpImmediate(NewC.getSExtValue())) { + isLegalICmpImmediate(NewC.getSExtValue())) { auto &DL = DAG.getDataLayout(); EVT ShiftTy = DCI.isBeforeLegalize() ? getPointerTy(DL) @@ -1924,19 +1948,21 @@ if (isa(N0.getNode())) { // Constant fold or commute setcc. SDValue O = DAG.FoldSetCC(VT, N0, N1, Cond, dl); - if (O.getNode()) return O; + if (O.getNode()) + return O; } else if (auto *CFP = dyn_cast(N1.getNode())) { // If the RHS of an FP comparison is a constant, simplify it away in // some cases. if (CFP->getValueAPF().isNaN()) { // If an operand is known to be a nan, we can fold it. switch (ISD::getUnorderedFlavor(Cond)) { - default: llvm_unreachable("Unknown flavor!"); - case 0: // Known false. + default: + llvm_unreachable("Unknown flavor!"); + case 0: // Known false. return DAG.getConstant(0, dl, VT); - case 1: // Known true. + case 1: // Known true. return DAG.getConstant(1, dl, VT); - case 2: // Undefined. + case 2: // Undefined. return DAG.getUNDEF(VT); } } @@ -2005,15 +2031,16 @@ return DAG.getConstant(EqVal, dl, VT); } unsigned UOF = ISD::getUnorderedFlavor(Cond); - if (UOF == 2) // FP operators that are undefined on NaNs. + if (UOF == 2) // FP operators that are undefined on NaNs. return DAG.getConstant(EqVal, dl, VT); if (UOF == unsigned(ISD::isTrueWhenEqual(Cond))) return DAG.getConstant(EqVal, dl, VT); // Otherwise, we can't fold it. However, we can simplify it to SETUO/SETO // if it is not already. ISD::CondCode NewCond = UOF == 0 ? ISD::SETO : ISD::SETUO; - if (NewCond != Cond && (DCI.isBeforeLegalizeOps() || - getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal)) + if (NewCond != Cond && + (DCI.isBeforeLegalizeOps() || + getCondCodeAction(NewCond, N0.getSimpleValueType()) == Legal)) return DAG.getSetCC(dl, VT, N0, N1, NewCond); } @@ -2046,10 +2073,11 @@ if (auto *LHSR = dyn_cast(N0.getOperand(1))) { // Turn (X+C1) == C2 --> X == C2-C1 if (N0.getOpcode() == ISD::ADD && N0.getNode()->hasOneUse()) { - return DAG.getSetCC(dl, VT, N0.getOperand(0), - DAG.getConstant(RHSC->getAPIntValue()- - LHSR->getAPIntValue(), - dl, N0.getValueType()), Cond); + return DAG.getSetCC( + dl, VT, N0.getOperand(0), + DAG.getConstant(RHSC->getAPIntValue() - LHSR->getAPIntValue(), + dl, N0.getValueType()), + Cond); } // Turn (X^C1) == C2 into X == C1^C2 iff X&~C1 = 0. @@ -2057,23 +2085,21 @@ // If we know that all of the inverted bits are zero, don't bother // performing the inversion. if (DAG.MaskedValueIsZero(N0.getOperand(0), ~LHSR->getAPIntValue())) - return - DAG.getSetCC(dl, VT, N0.getOperand(0), - DAG.getConstant(LHSR->getAPIntValue() ^ - RHSC->getAPIntValue(), - dl, N0.getValueType()), - Cond); + return DAG.getSetCC( + dl, VT, N0.getOperand(0), + DAG.getConstant(LHSR->getAPIntValue() ^ RHSC->getAPIntValue(), + dl, N0.getValueType()), + Cond); } // Turn (C1-X) == C2 --> X == C1-C2 if (auto *SUBC = dyn_cast(N0.getOperand(0))) { if (N0.getOpcode() == ISD::SUB && N0.getNode()->hasOneUse()) { - return - DAG.getSetCC(dl, VT, N0.getOperand(1), - DAG.getConstant(SUBC->getAPIntValue() - - RHSC->getAPIntValue(), - dl, N0.getValueType()), - Cond); + return DAG.getSetCC( + dl, VT, N0.getOperand(1), + DAG.getConstant(SUBC->getAPIntValue() - RHSC->getAPIntValue(), + dl, N0.getValueType()), + Cond); } } @@ -2116,11 +2142,11 @@ // Simplify X == (X+Z) --> Z == 0 if (N1.getOperand(0) == N0) return DAG.getSetCC(dl, VT, N1.getOperand(1), - DAG.getConstant(0, dl, N1.getValueType()), Cond); + DAG.getConstant(0, dl, N1.getValueType()), Cond); if (N1.getOperand(1) == N0) { if (DAG.isCommutativeBinOp(N1.getOpcode())) return DAG.getSetCC(dl, VT, N1.getOperand(0), - DAG.getConstant(0, dl, N1.getValueType()), Cond); + DAG.getConstant(0, dl, N1.getValueType()), Cond); if (N1.getNode()->hasOneUse()) { assert(N1.getOpcode() == ISD::SUB && "Unexpected operation!"); auto &DL = DAG.getDataLayout(); @@ -2143,14 +2169,15 @@ SDValue Temp; if (N0.getValueType() == MVT::i1 && foldBooleans) { switch (Cond) { - default: llvm_unreachable("Unknown integer setcc!"); - case ISD::SETEQ: // X == Y -> ~(X^Y) + default: + llvm_unreachable("Unknown integer setcc!"); + case ISD::SETEQ: // X == Y -> ~(X^Y) Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); N0 = DAG.getNOT(dl, Temp, MVT::i1); if (!DCI.isCalledByLegalizer()) DCI.AddToWorklist(Temp.getNode()); break; - case ISD::SETNE: // X != Y --> (X^Y) + case ISD::SETNE: // X != Y --> (X^Y) N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1); break; case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y @@ -2238,20 +2265,22 @@ if (S == 1) { switch (Constraint[0]) { - default: break; - case 'r': return C_RegisterClass; - case 'm': // memory - case 'o': // offsetable - case 'V': // not offsetable + default: + break; + case 'r': + return C_RegisterClass; + case 'm': // memory + case 'o': // offsetable + case 'V': // not offsetable return C_Memory; - case 'i': // Simple Integer or Relocatable Constant - case 'n': // Simple Integer - case 'E': // Floating Point Constant - case 'F': // Floating Point Constant - case 's': // Relocatable Constant - case 'p': // Address. - case 'X': // Allow ANY value. - case 'I': // Target registers. + case 'i': // Simple Integer or Relocatable Constant + case 'n': // Simple Integer + case 'E': // Floating Point Constant + case 'F': // Floating Point Constant + case 's': // Relocatable Constant + case 'p': // Address. + case 'X': // Allow ANY value. + case 'I': // Target registers. case 'J': case 'K': case 'L': @@ -2265,7 +2294,7 @@ } } - if (S > 1 && Constraint[0] == '{' && Constraint[S-1] == '}') { + if (S > 1 && Constraint[0] == '{' && Constraint[S - 1] == '}') { if (S == 8 && Constraint.substr(1, 6) == "memory") // "{memory}" return C_Memory; return C_Register; @@ -2276,11 +2305,11 @@ /// Try to replace an X constraint, which matches anything, with another that /// has more specific requirements based on the type of the corresponding /// operand. -const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{ +const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const { if (ConstraintVT.isInteger()) return "r"; if (ConstraintVT.isFloatingPoint()) - return "f"; // works for many targets + return "f"; // works for many targets return nullptr; } @@ -2291,20 +2320,22 @@ std::vector &Ops, SelectionDAG &DAG) const { - if (Constraint.length() > 1) return; + if (Constraint.length() > 1) + return; char ConstraintLetter = Constraint[0]; switch (ConstraintLetter) { - default: break; - case 'X': // Allows any operand; labels (basic block) use this. + default: + break; + case 'X': // Allows any operand; labels (basic block) use this. if (Op.getOpcode() == ISD::BasicBlock) { Ops.push_back(Op); return; } - // fall through - case 'i': // Simple Integer or Relocatable Constant - case 'n': // Simple Integer - case 's': { // Relocatable Constant + // fall through + case 'i': // Simple Integer or Relocatable Constant + case 'n': // Simple Integer + case 's': { // Relocatable Constant // These operands are interested in values of the form (GV+C), where C may // be folded in as an offset of GV, or it may be explicitly added. Also, it // is possible and fine if either GV or C are missing. @@ -2327,17 +2358,17 @@ // If we find a valid operand, map to the TargetXXX version so that the // value itself doesn't get selected. - if (GA) { // Either &GV or &GV+C + if (GA) { // Either &GV or &GV+C if (ConstraintLetter != 'n') { int64_t Offs = GA->getOffset(); - if (C) Offs += C->getZExtValue(); - Ops.push_back(DAG.getTargetGlobalAddress(GA->getGlobal(), - C ? SDLoc(C) : SDLoc(), - Op.getValueType(), Offs)); + if (C) + Offs += C->getZExtValue(); + Ops.push_back(DAG.getTargetGlobalAddress( + GA->getGlobal(), C ? SDLoc(C) : SDLoc(), Op.getValueType(), Offs)); } return; } - if (C) { // just C, no GV. + if (C) { // just C, no GV. // Simple constants are not allowed for 's'. if (ConstraintLetter != 's') { // gcc prints these as sign extended. Sign extend value to 64 bits @@ -2358,18 +2389,19 @@ StringRef Constraint, MVT VT) const { if (Constraint.empty() || Constraint[0] != '{') - return std::make_pair(0u, static_cast(nullptr)); - assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?"); + return std::make_pair(0u, static_cast(nullptr)); + assert(*(Constraint.end() - 1) == '}' && "Not a brace enclosed constraint?"); // Remove the braces from around the name. - StringRef RegName(Constraint.data()+1, Constraint.size()-2); + StringRef RegName(Constraint.data() + 1, Constraint.size() - 2); - std::pair R = - std::make_pair(0u, static_cast(nullptr)); + std::pair R = + std::make_pair(0u, static_cast(nullptr)); // Figure out which register class contains this reg. for (TargetRegisterInfo::regclass_iterator RCI = RI->regclass_begin(), - E = RI->regclass_end(); RCI != E; ++RCI) { + E = RI->regclass_end(); + RCI != E; ++RCI) { const TargetRegisterClass *RC = *RCI; // If none of the value types for this register class are valid, we @@ -2377,11 +2409,11 @@ if (!isLegalRC(RC)) continue; - for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); - I != E; ++I) { + for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I != E; + ++I) { if (RegName.equals_lower(RI->getRegAsmName(*I))) { - std::pair S = - std::make_pair(*I, RC); + std::pair S = + std::make_pair(*I, RC); // If this register class has the requested value type, return it, // otherwise keep searching and return the first class found @@ -2430,8 +2462,8 @@ // Do a prepass over the constraints, canonicalizing them, and building up the // ConstraintOperands list. - unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. - unsigned ResNo = 0; // ResNo - The result number of the next output. + unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. + unsigned ResNo = 0; // ResNo - The result number of the next output. for (InlineAsm::ConstraintInfo &CI : IA->ParseConstraints()) { ConstraintOperands.emplace_back(std::move(CI)); @@ -2454,8 +2486,7 @@ // The return value of the call is this value. As such, there is no // corresponding argument. - assert(!CS.getType()->isVoidTy() && - "Bad inline asm!"); + assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); if (StructType *STy = dyn_cast(CS.getType())) { OpInfo.ConstraintVT = getSimpleValueType(DL, STy->getElementType(ResNo)); @@ -2492,7 +2523,8 @@ if (!OpTy->isSingleValueType() && OpTy->isSized()) { unsigned BitSize = DL.getTypeSizeInBits(OpTy); switch (BitSize) { - default: break; + default: + break; case 1: case 8: case 16: @@ -2500,7 +2532,7 @@ case 64: case 128: OpInfo.ConstraintVT = - MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true); + MVT::getVT(IntegerType::get(OpTy->getContext(), BitSize), true); break; } } else if (PointerType *PT = dyn_cast(OpTy)) { @@ -2525,8 +2557,8 @@ for (maIndex = 0; maIndex < maCount; ++maIndex) { int weightSum = 0; for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); - cIndex != eIndex; ++cIndex) { - AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; + cIndex != eIndex; ++cIndex) { + AsmOperandInfo &OpInfo = ConstraintOperands[cIndex]; if (OpInfo.Type == InlineAsm::isClobber) continue; @@ -2541,7 +2573,7 @@ Input.ConstraintVT.isInteger()) || (OpInfo.ConstraintVT.getSizeInBits() != Input.ConstraintVT.getSizeInBits())) { - weightSum = -1; // Can't match. + weightSum = -1; // Can't match. break; } } @@ -2562,8 +2594,8 @@ // Now select chosen alternative in each constraint. for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); - cIndex != eIndex; ++cIndex) { - AsmOperandInfo& cInfo = ConstraintOperands[cIndex]; + cIndex != eIndex; ++cIndex) { + AsmOperandInfo &cInfo = ConstraintOperands[cIndex]; if (cInfo.Type == InlineAsm::isClobber) continue; cInfo.selectAlternative(bestMAIndex); @@ -2573,8 +2605,8 @@ // Check and hook up tied operands, choose constraint code to use. for (unsigned cIndex = 0, eIndex = ConstraintOperands.size(); - cIndex != eIndex; ++cIndex) { - AsmOperandInfo& OpInfo = ConstraintOperands[cIndex]; + cIndex != eIndex; ++cIndex) { + AsmOperandInfo &OpInfo = ConstraintOperands[cIndex]; // If this is an output operand with a matching input operand, look up the // matching input. If their types mismatch, e.g. one is an integer, the @@ -2624,8 +2656,8 @@ /// This object must already have been set up with the operand type /// and the current alternative constraint selected. TargetLowering::ConstraintWeight - TargetLowering::getMultipleConstraintMatchWeight( - AsmOperandInfo &info, int maIndex) const { +TargetLowering::getMultipleConstraintMatchWeight(AsmOperandInfo &info, + int maIndex) const { InlineAsm::ConstraintCodeVector *rCodes; if (maIndex >= (int)info.multipleAlternatives.size()) rCodes = &info.Codes; @@ -2636,7 +2668,7 @@ // Loop over the options, keeping track of the most general one. for (unsigned i = 0, e = rCodes->size(); i != e; ++i) { ConstraintWeight weight = - getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str()); + getSingleConstraintMatchWeight(info, (*rCodes)[i].c_str()); if (weight > BestWeight) BestWeight = weight; } @@ -2648,47 +2680,47 @@ /// This object must already have been set up with the operand type /// and the current alternative constraint selected. TargetLowering::ConstraintWeight - TargetLowering::getSingleConstraintMatchWeight( - AsmOperandInfo &info, const char *constraint) const { +TargetLowering::getSingleConstraintMatchWeight(AsmOperandInfo &info, + const char *constraint) const { ConstraintWeight weight = CW_Invalid; Value *CallOperandVal = info.CallOperandVal; - // If we don't have a value, we can't do a match, - // but allow it at the lowest weight. + // If we don't have a value, we can't do a match, + // but allow it at the lowest weight. if (!CallOperandVal) return CW_Default; // Look at the constraint type. switch (*constraint) { - case 'i': // immediate integer. - case 'n': // immediate integer with a known value. - if (isa(CallOperandVal)) - weight = CW_Constant; - break; - case 's': // non-explicit intregal immediate. - if (isa(CallOperandVal)) - weight = CW_Constant; - break; - case 'E': // immediate float if host format. - case 'F': // immediate float. - if (isa(CallOperandVal)) - weight = CW_Constant; - break; - case '<': // memory operand with autodecrement. - case '>': // memory operand with autoincrement. - case 'm': // memory operand. - case 'o': // offsettable memory operand - case 'V': // non-offsettable memory operand - weight = CW_Memory; - break; - case 'r': // general register. - case 'g': // general register, memory operand or immediate integer. - // note: Clang converts "g" to "imr". - if (CallOperandVal->getType()->isIntegerTy()) - weight = CW_Register; - break; - case 'X': // any operand. - default: - weight = CW_Default; - break; + case 'i': // immediate integer. + case 'n': // immediate integer with a known value. + if (isa(CallOperandVal)) + weight = CW_Constant; + break; + case 's': // non-explicit intregal immediate. + if (isa(CallOperandVal)) + weight = CW_Constant; + break; + case 'E': // immediate float if host format. + case 'F': // immediate float. + if (isa(CallOperandVal)) + weight = CW_Constant; + break; + case '<': // memory operand with autodecrement. + case '>': // memory operand with autoincrement. + case 'm': // memory operand. + case 'o': // offsettable memory operand + case 'V': // non-offsettable memory operand + weight = CW_Memory; + break; + case 'r': // general register. + case 'g': // general register, memory operand or immediate integer. + // note: Clang converts "g" to "imr". + if (CallOperandVal->getType()->isIntegerTy()) + weight = CW_Register; + break; + case 'X': // any operand. + default: + weight = CW_Default; + break; } return weight; } @@ -2714,8 +2746,8 @@ /// 'm' over 'r', for example. /// static void ChooseConstraint(TargetLowering::AsmOperandInfo &OpInfo, - const TargetLowering &TLI, - SDValue Op, SelectionDAG *DAG) { + const TargetLowering &TLI, SDValue Op, + SelectionDAG *DAG) { assert(OpInfo.Codes.size() > 1 && "Doesn't have multiple constraint options"); unsigned BestIdx = 0; TargetLowering::ConstraintType BestType = TargetLowering::C_Unknown; @@ -2724,7 +2756,7 @@ // Loop over the options, keeping track of the most general one. for (unsigned i = 0, e = OpInfo.Codes.size(); i != e; ++i) { TargetLowering::ConstraintType CType = - TLI.getConstraintType(OpInfo.Codes[i]); + TLI.getConstraintType(OpInfo.Codes[i]); // If this is an 'other' constraint, see if the operand is valid for it. // For example, on X86 we might have an 'rI' constraint. If the operand @@ -2734,8 +2766,7 @@ assert(OpInfo.Codes[i].size() == 1 && "Unhandled multi-letter 'other' constraint"); std::vector ResultOps; - TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i], - ResultOps, *DAG); + TLI.LowerAsmOperandForConstraint(Op, OpInfo.Codes[i], ResultOps, *DAG); if (!ResultOps.empty()) { BestType = CType; BestIdx = i; @@ -2763,8 +2794,7 @@ /// Determines the constraint code and constraint type to use for the specific /// AsmOperandInfo, setting OpInfo.ConstraintCode and OpInfo.ConstraintType. -void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, - SDValue Op, +void TargetLowering::ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG) const { assert(!OpInfo.Codes.empty() && "Must have at least one constraint"); @@ -2819,7 +2849,7 @@ // Calculate the multiplicative inverse, using Newton's method. APInt t, xn = d; - while ((t = d*xn) != 1) + while ((t = d * xn) != 1) xn *= APInt(d.getBitWidth(), 2) - t; SDValue Op2 = DAG.getConstant(xn, dl, Op1.getValueType()); @@ -2834,7 +2864,7 @@ AttributeSet Attr = DAG.getMachineFunction().getFunction()->getAttributes(); const TargetLowering &TLI = DAG.getTargetLoweringInfo(); if (TLI.isIntDivCheap(N->getValueType(0), Attr)) - return SDValue(N,0); // Lower SDIV as SDIV + return SDValue(N, 0); // Lower SDIV as SDIV return SDValue(); } @@ -2864,17 +2894,18 @@ // Multiply the numerator (operand 0) by the magic value // FIXME: We should support doing a MUL in a wider type SDValue Q; - if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) : - isOperationLegalOrCustom(ISD::MULHS, VT)) + if (IsAfterLegalization ? isOperationLegal(ISD::MULHS, VT) + : isOperationLegalOrCustom(ISD::MULHS, VT)) Q = DAG.getNode(ISD::MULHS, dl, VT, N->getOperand(0), DAG.getConstant(magics.m, dl, VT)); - else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) : - isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) + else if (IsAfterLegalization ? isOperationLegal(ISD::SMUL_LOHI, VT) + : isOperationLegalOrCustom(ISD::SMUL_LOHI, VT)) Q = SDValue(DAG.getNode(ISD::SMUL_LOHI, dl, DAG.getVTList(VT, VT), - N->getOperand(0), - DAG.getConstant(magics.m, dl, VT)).getNode(), 1); + N->getOperand(0), DAG.getConstant(magics.m, dl, VT)) + .getNode(), + 1); else - return SDValue(); // No mulhs or equvialent + return SDValue(); // No mulhs or equvialent // If d > 0 and m < 0, add the numerator if (Divisor.isStrictlyPositive() && magics.m.isNegative()) { Q = DAG.getNode(ISD::ADD, dl, VT, Q, N->getOperand(0)); @@ -2942,15 +2973,17 @@ // Multiply the numerator (operand 0) by the magic value // FIXME: We should support doing a MUL in a wider type - if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) : - isOperationLegalOrCustom(ISD::MULHU, VT)) + if (IsAfterLegalization ? isOperationLegal(ISD::MULHU, VT) + : isOperationLegalOrCustom(ISD::MULHU, VT)) Q = DAG.getNode(ISD::MULHU, dl, VT, Q, DAG.getConstant(magics.m, dl, VT)); - else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) : - isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) + else if (IsAfterLegalization ? isOperationLegal(ISD::UMUL_LOHI, VT) + : isOperationLegalOrCustom(ISD::UMUL_LOHI, VT)) Q = SDValue(DAG.getNode(ISD::UMUL_LOHI, dl, DAG.getVTList(VT, VT), Q, - DAG.getConstant(magics.m, dl, VT)).getNode(), 1); + DAG.getConstant(magics.m, dl, VT)) + .getNode(), + 1); else - return SDValue(); // No mulhu or equvialent + return SDValue(); // No mulhu or equvialent Created->push_back(Q.getNode()); @@ -2976,8 +3009,8 @@ } } -bool TargetLowering:: -verifyReturnAddressArgumentIsConstant(SDValue Op, SelectionDAG &DAG) const { +bool TargetLowering::verifyReturnAddressArgumentIsConstant( + SDValue Op, SelectionDAG &DAG) const { if (!isa(Op.getOperand(0))) { DAG.getContext()->emitError("argument to '__builtin_return_address' must " "be a constant integer"); @@ -3096,7 +3129,7 @@ } bool TargetLowering::expandFP_TO_SINT(SDNode *Node, SDValue &Result, - SelectionDAG &DAG) const { + SelectionDAG &DAG) const { EVT VT = Node->getOperand(0).getValueType(); EVT NVT = Node->getValueType(0); SDLoc dl(SDValue(Node, 0)); @@ -3108,13 +3141,12 @@ // Expand f32 -> i64 conversion // This algorithm comes from compiler-rt's implementation of fixsfdi: // https://github.com/llvm-mirror/compiler-rt/blob/master/lib/builtins/fixsfdi.c - EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), - VT.getSizeInBits()); + EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); SDValue ExponentMask = DAG.getConstant(0x7F800000, dl, IntVT); SDValue ExponentLoBit = DAG.getConstant(23, dl, IntVT); SDValue Bias = DAG.getConstant(127, dl, IntVT); - SDValue SignMask = DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()), dl, - IntVT); + SDValue SignMask = + DAG.getConstant(APInt::getSignBit(VT.getSizeInBits()), dl, IntVT); SDValue SignLowBit = DAG.getConstant(VT.getSizeInBits() - 1, dl, IntVT); SDValue MantissaMask = DAG.getConstant(0x007FFFFF, dl, IntVT); @@ -3132,8 +3164,8 @@ Sign = DAG.getSExtOrTrunc(Sign, dl, NVT); SDValue R = DAG.getNode(ISD::OR, dl, IntVT, - DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask), - DAG.getConstant(0x00800000, dl, IntVT)); + DAG.getNode(ISD::AND, dl, IntVT, Bits, MantissaMask), + DAG.getConstant(0x00800000, dl, IntVT)); R = DAG.getZExtOrTrunc(R, dl, NVT); @@ -3150,11 +3182,10 @@ ISD::SETGT); SDValue Ret = DAG.getNode(ISD::SUB, dl, NVT, - DAG.getNode(ISD::XOR, dl, NVT, R, Sign), - Sign); + DAG.getNode(ISD::XOR, dl, NVT, R, Sign), Sign); Result = DAG.getSelectCC(dl, Exponent, DAG.getConstant(0, dl, IntVT), - DAG.getConstant(0, dl, NVT), Ret, ISD::SETLT); + DAG.getConstant(0, dl, NVT), Ret, ISD::SETLT); return true; } @@ -3196,7 +3227,7 @@ SDValue NewChain = DAG.getNode(ISD::TokenFactor, SL, MVT::Other, LoadChains); SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, SL, LD->getValueType(0), Vals); - return DAG.getMergeValues({ Value, NewChain }, SL); + return DAG.getMergeValues({Value, NewChain}, SL); } // FIXME: This relies on each element having a byte size, otherwise the stride @@ -3267,12 +3298,12 @@ // Expand to a (misaligned) integer load of the same size, // then bitconvert to floating point or vector. - SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, - LD->getMemOperand()); + SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getMemOperand()); SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad); if (LoadedVT != VT) - Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND : - ISD::ANY_EXTEND, dl, VT, Result); + Result = + DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND : ISD::ANY_EXTEND, + dl, VT, Result); return std::make_pair(Result, newLoad.getValue(1)); } @@ -3310,13 +3341,13 @@ // Increment the pointers. Offset += RegBytes; Ptr = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr, PtrIncrement); - StackPtr = DAG.getNode(ISD::ADD, dl, StackPtrVT, StackPtr, - StackPtrIncrement); + StackPtr = + DAG.getNode(ISD::ADD, dl, StackPtrVT, StackPtr, StackPtrIncrement); } // The last copy may be partial. Do an extending load. - EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), - 8 * (LoadedBytes - Offset)); + EVT MemVT = + EVT::getIntegerVT(*DAG.getContext(), 8 * (LoadedBytes - Offset)); SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, LD->getPointerInfo().getWithOffset(Offset), MemVT, @@ -3346,7 +3377,7 @@ // integer MVT. unsigned NumBits = LoadedVT.getSizeInBits(); EVT NewLoadedVT; - NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2); + NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits / 2); NumBits >>= 1; unsigned Alignment = LD->getAlignment(); @@ -3382,14 +3413,13 @@ } // aggregate the two parts - SDValue ShiftAmount = - DAG.getConstant(NumBits, dl, getShiftAmountTy(Hi.getValueType(), - DAG.getDataLayout())); + SDValue ShiftAmount = DAG.getConstant( + NumBits, dl, getShiftAmountTy(Hi.getValueType(), DAG.getDataLayout())); SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), - Hi.getValue(1)); + Hi.getValue(1)); return std::make_pair(Result, TF); } @@ -3405,8 +3435,7 @@ int Alignment = ST->getAlignment(); SDLoc dl(ST); - if (ST->getMemoryVT().isFloatingPoint() || - ST->getMemoryVT().isVector()) { + if (ST->getMemoryVT().isFloatingPoint() || ST->getMemoryVT().isVector()) { EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); if (isTypeLegal(intVT)) { if (!isOperationLegalOrCustom(ISD::STORE, intVT)) { @@ -3426,10 +3455,9 @@ // Do a (aligned) store to a stack slot, then copy from the stack slot // to the final destination using (unaligned) integer loads and stores. EVT StoredVT = ST->getMemoryVT(); - MVT RegVT = - getRegisterType(*DAG.getContext(), - EVT::getIntegerVT(*DAG.getContext(), - StoredVT.getSizeInBits())); + MVT RegVT = getRegisterType( + *DAG.getContext(), + EVT::getIntegerVT(*DAG.getContext(), StoredVT.getSizeInBits())); EVT PtrVT = Ptr.getValueType(); unsigned StoredBytes = StoredVT.getSizeInBits() / 8; unsigned RegBytes = RegVT.getSizeInBits() / 8; @@ -3461,16 +3489,16 @@ ST->getMemOperand()->getFlags())); // Increment the pointers. Offset += RegBytes; - StackPtr = DAG.getNode(ISD::ADD, dl, StackPtrVT, - StackPtr, StackPtrIncrement); + StackPtr = + DAG.getNode(ISD::ADD, dl, StackPtrVT, StackPtr, StackPtrIncrement); Ptr = DAG.getNode(ISD::ADD, dl, PtrVT, Ptr, PtrIncrement); } // The last store may be partial. Do a truncating store. On big-endian // machines this requires an extending load from the stack slot to ensure // that the bits are in the right place. - EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), - 8 * (StoredBytes - Offset)); + EVT MemVT = + EVT::getIntegerVT(*DAG.getContext(), 8 * (StoredBytes - Offset)); // Load from the stack slot. SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, @@ -3486,8 +3514,7 @@ return Result; } - assert(ST->getMemoryVT().isInteger() && - !ST->getMemoryVT().isVector() && + assert(ST->getMemoryVT().isInteger() && !ST->getMemoryVT().isVector() && "Unaligned store of unknown type."); // Get the half-size VT EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext()); @@ -3495,9 +3522,8 @@ int IncrementSize = NumBits / 8; // Divide the stored value in two parts. - SDValue ShiftAmount = - DAG.getConstant(NumBits, dl, getShiftAmountTy(Val.getValueType(), - DAG.getDataLayout())); + SDValue ShiftAmount = DAG.getConstant( + NumBits, dl, getShiftAmountTy(Val.getValueType(), DAG.getDataLayout())); SDValue Lo = Val; SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); @@ -3518,7 +3544,7 @@ ST->getMemOperand()->getFlags(), ST->getAAInfo()); SDValue Result = - DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); + DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); return Result; } @@ -3537,7 +3563,7 @@ ArgListTy Args; ArgListEntry Entry; std::string NameString = ("__emutls_v." + GA->getGlobal()->getName()).str(); - Module *VariableModule = const_cast(GA->getGlobal()->getParent()); + Module *VariableModule = const_cast(GA->getGlobal()->getParent()); StringRef EmuTlsVarName(NameString); GlobalVariable *EmuTlsVar = VariableModule->getNamedGlobal(EmuTlsVarName); assert(EmuTlsVar && "Cannot find EmuTlsVar "); @@ -3555,7 +3581,7 @@ // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. // At last for X86 targets, maybe good for other targets too? MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo(); - MFI.setAdjustsStack(true); // Is this only for X86 target? + MFI.setAdjustsStack(true); // Is this only for X86 target? MFI.setHasCalls(true); assert((GA->getOffset() == 0) && Index: test/CodeGen/X86/2016-08-07-jumptable-largecodemodel.ll =================================================================== --- /dev/null +++ test/CodeGen/X86/2016-08-07-jumptable-largecodemodel.ll @@ -0,0 +1,38 @@ +; RUN: llc < %s -code-model=large | FileCheck %s + +; Make sure that we're emitting EK_BlockAddress jumps for a jumptable when the +; code-model is Large. + +; CHECK: @test +; CHECK-NOT: movslq (%rax,%rdi,4), %rsi +; CHECK: ret +define i32 @test(i32 %i, i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) { +entry: + switch i32 %i, label %case_a [ i32 1, label %case_b + i32 2, label %case_c + i32 3, label %case_d + i32 4, label %case_e ] + +case_a: + br label %exit + +case_b: + br label %exit + +case_c: + br label %exit + +case_d: + br label %exit + +case_e: + br label %exit + +exit: + %result = phi i32 [ %a, %case_a ], + [ %b, %case_b ], + [ %c, %case_c ], + [ %d, %case_d ], + [ %e, %case_e ] + ret i32 %result +}