Index: llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td =================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td +++ llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td @@ -158,6 +158,14 @@ // //===----------------------------------------------------------------------===// +class InstE op, dag outs, dag ins, string asmstr, list pattern> + : InstSystemZ<2, outs, ins, asmstr, pattern> { + field bits<16> Inst; + field bits<16> SoftFail = 0; + + let Inst = op; +} + class InstI op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<2, outs, ins, asmstr, pattern> { field bits<16> Inst; @@ -487,6 +495,21 @@ let Inst{15-0} = BD2; } +class InstRSI op, dag outs, dag ins, string asmstr, list pattern> + : InstSystemZ<4, outs, ins, asmstr, pattern> { + field bits<32> Inst; + field bits<32> SoftFail = 0; + + bits<4> R1; + bits<4> R3; + bits<16> RI2; + + let Inst{31-24} = op; + let Inst{23-20} = R1; + let Inst{19-16} = R3; + let Inst{15-0} = RI2; +} + class InstRSY op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<6, outs, ins, asmstr, pattern> { field bits<48> Inst; @@ -560,6 +583,51 @@ let Inst{15-0} = BD2; } +class InstSSd op, dag outs, dag ins, string asmstr, list pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<20> XBD1; + bits<16> BD2; + bits<4> R3; + + let Inst{47-40} = op; + let Inst{39-36} = XBD1{19-16}; + let Inst{35-32} = R3; + let Inst{31-16} = XBD1{15-0}; + let Inst{15-0} = BD2; +} + +class InstSSE op, dag outs, dag ins, string asmstr, list pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<16> BD1; + bits<16> BD2; + + let Inst{47-32} = op; + let Inst{31-16} = BD1; + let Inst{15-0} = BD2; +} + +class InstSSF op, dag outs, dag ins, string asmstr, list pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<16> BD1; + bits<16> BD2; + bits<4> R3; + + let Inst{47-40} = op{11-4}; + let Inst{39-36} = R3; + let Inst{35-32} = op{3-0}; + let Inst{31-16} = BD1; + let Inst{15-0} = BD2; +} + class InstS op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<4, outs, ins, asmstr, pattern> { field bits<32> Inst; @@ -966,6 +1034,11 @@ // form of the source register in the destination register and // branches on the result. // +// BranchBinary: +// One register output operand, two register input operands and one branch +// displacement. The instructions stores a modified form of one of the +// source registers in the destination register and branches on the result. +// // LoadMultiple: // One address input operand and two explicit output operands. // The instruction loads a range of registers from the address, @@ -1060,6 +1133,15 @@ let DisableEncoding = "$R1src"; } +class BranchBinaryRSI opcode, RegisterOperand cls> + : InstRSI { + let isBranch = 1; + let isTerminator = 1; + let Constraints = "$R1 = $R1src"; + let DisableEncoding = "$R1src"; +} + class LoadMultipleRS opcode, RegisterOperand cls, AddressingMode mode = bdaddr12only> : InstRS; } +def BRXH : BranchBinaryRSI<"brxh", 0x84, GR64>; +def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR64>; + //===----------------------------------------------------------------------===// // Select instructions //===----------------------------------------------------------------------===// @@ -1680,6 +1683,25 @@ "exrl\t$R1, $I2", []>; } +let Defs = [CC] in { + let hasSideEffects = 1 in + def PR : InstE<0x0101, (outs), (ins), "pr", []>; + + let mayLoad = 1, mayStore = 1 in + def MVCK : InstSSd<0xD9, (outs), + (ins bdxaddr12only:$XBD1, bdaddr12only:$BD2, + GR64:$R3), + "mvck\t$XBD1, $BD2, $R3", []>; +} + +let mayStore = 1 in + def STRAG : InstSSE<0xE502, (outs), (ins bdaddr12only:$BD1, bdaddr12only:$BD2), + "strag\t$BD1, $BD2", []>; + +let Defs = [R0D, R1D], mayLoad = 1 in + def ECTG : InstSSF<0xC81, (outs), + (ins bdaddr12only:$BD1, bdaddr12only:$BD2, GR64:$R3), + "ectg\t$BD1, $BD2, $R3", []>; //===----------------------------------------------------------------------===// // Peepholes. Index: llvm/trunk/test/MC/Disassembler/SystemZ/insns-pcrel.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/SystemZ/insns-pcrel.txt +++ llvm/trunk/test/MC/Disassembler/SystemZ/insns-pcrel.txt @@ -1762,3 +1762,51 @@ # 0x00000a02: # CHECK: exrl %r15, 0x100000a00 0xc6 0xf0 0x7f 0xff 0xff 0xff + +# 0x00000a08: +# CHECK: brxh %r0, %r1, 0xa08 +0x84 0x01 0x00 0x00 + +# 0x00000a0c: +# CHECK: brxh %r14, %r1, 0xa0c +0x84 0xe1 0x00 0x00 + +# 0x00000a10: +# CHECK: brxh %r15, %r1, 0xa10 +0x84 0xf1 0x00 0x00 + +# 0x00000a14: +# CHECK: brxh %r0, %r1, 0xa12 +0x84 0x01 0xff 0xff + +# 0x00000a18: +# CHECK: brxh %r14, %r1, 0xffffffffffff0a18 +0x84 0xe1 0x80 0x00 + +# 0x00000a1c: +# CHECK: brxh %r15, %r1, 0x10a1a +0x84 0xf1 0x7f 0xff + +# 0x00000a20: +# CHECK: brxle %r0, %r1, 0xa20 +0x85 0x01 0x00 0x00 + +# 0x00000a24: +# CHECK: brxle %r14, %r1, 0xa24 +0x85 0xe1 0x00 0x00 + +# 0x00000a28: +# CHECK: brxle %r15, %r1, 0xa28 +0x85 0xf1 0x00 0x00 + +# 0x00000a2c: +# CHECK: brxle %r0, %r1, 0xa2a +0x85 0x01 0xff 0xff + +# 0x00000a30: +# CHECK: brxle %r14, %r1, 0xffffffffffff0a30 +0x85 0xe1 0x80 0x00 + +# 0x00000a34: +# CHECK: brxle %r15, %r1, 0x10a32 +0x85 0xf1 0x7f 0xff Index: llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt =================================================================== --- llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt +++ llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt @@ -3199,6 +3199,27 @@ # CHECK: ear %r15, %a15 0xb2 0x4f 0x00 0xff +# CHECK: ectg 0, 0, %r0 +0xc8 0x01 0x00 0x00 0x00 0x00 + +# CHECK: ectg 0, 4095, %r2 +0xc8 0x21 0x00 0x00 0x0f 0xff + +# CHECK: ectg 0, 0(%r1), %r2 +0xc8 0x21 0x00 0x00 0x10 0x00 + +# CHECK: ectg 0, 0(%r15), %r2 +0xc8 0x21 0x00 0x00 0xf0 0x00 + +# CHECK: ectg 0(%r1), 4095(%r15), %r2 +0xc8 0x21 0x10 0x00 0xff 0xff + +# CHECK: ectg 0(%r1), 0(%r15), %r2 +0xc8 0x21 0x10 0x00 0xf0 0x00 + +# CHECK: ectg 4095(%r1), 0(%r15), %r2 +0xc8 0x21 0x1f 0xff 0xf0 0x00 + # CHECK: etnd %r0 0xb2 0xec 0x00 0x00 @@ -6502,6 +6523,27 @@ # CHECK: mvc 0(256,%r15), 0 0xd2 0xff 0xf0 0x00 0x00 0x00 +# CHECK: mvck 0, 0, %r0 +0xd9 0x00 0x00 0x00 0x00 0x00 + +# CHECK: mvck 0, 4095, %r2 +0xd9 0x02 0x00 0x00 0x0f 0xff + +# CHECK: mvck 0, 0(%r1), %r2 +0xd9 0x02 0x00 0x00 0x10 0x00 + +# CHECK: mvck 0, 0(%r15), %r2 +0xd9 0x02 0x00 0x00 0xf0 0x00 + +# CHECK: mvck 0(%r1), 4095(%r15), %r2 +0xd9 0x02 0x10 0x00 0xff 0xff + +# CHECK: mvck 0(%r1), 0(%r15), %r2 +0xd9 0x02 0x10 0x00 0xf0 0x00 + +# CHECK: mvck 4095(%r15,%r1), 0(%r15), %r2 +0xd9 0xf2 0x1f 0xff 0xf0 0x00 + # CHECK: mvghi 0, 0 0xe5 0x48 0x00 0x00 0x00 0x00 @@ -7309,6 +7351,9 @@ # CHECK: pfd 15, 0 0xe3 0xf0 0x00 0x00 0x00 0x36 +# CHECK: pr +0x01 0x01 + # CHECK: popcnt %r0, %r0 0xb9 0xe1 0x00 0x00 @@ -9022,6 +9067,24 @@ # CHECK: stmy %r0, %r0, 524287(%r15) 0xeb 0x00 0xff 0xff 0x7f 0x90 +# CHECK: strag 0, 0 +0xe5 0x02 0x00 0x00 0x00 0x00 + +# CHECK: strag 0, 4095 +0xe5 0x02 0x00 0x00 0x0f 0xff + +# CHECK: strag 0, 0(%r1) +0xe5 0x02 0x00 0x00 0x10 0x00 + +# CHECK: strag 0, 0(%r15) +0xe5 0x02 0x00 0x00 0xf0 0x00 + +# CHECK: strag 0(%r1), 4095(%r15) +0xe5 0x02 0x10 0x00 0xff 0xff + +# CHECK: strag 4095(%r1), 0(%r15) +0xe5 0x02 0x1f 0xff 0xf0 0x00 + # CHECK: strvg %r0, -524288 0xe3 0x00 0x00 0x00 0x80 0x2f Index: llvm/trunk/test/MC/SystemZ/insn-bad.s =================================================================== --- llvm/trunk/test/MC/SystemZ/insn-bad.s +++ llvm/trunk/test/MC/SystemZ/insn-bad.s @@ -370,6 +370,34 @@ brctg %r0, 1 brctg %r0, 0x10000 +#CHECK: error: offset out of range +#CHECK: brxh %r0, %r2, -0x100002 +#CHECK: error: offset out of range +#CHECK: brxh %r0, %r2, -1 +#CHECK: error: offset out of range +#CHECK: brxh %r0, %r2, 1 +#CHECK: error: offset out of range +#CHECK: brxh %r0, %r2, 0x10000 + + brxh %r0, %r2, -0x100002 + brxh %r0, %r2, -1 + brxh %r0, %r2, 1 + brxh %r0, %r2, 0x10000 + +#CHECK: error: offset out of range +#CHECK: brxle %r0, %r2, -0x100002 +#CHECK: error: offset out of range +#CHECK: brxle %r0, %r2, -1 +#CHECK: error: offset out of range +#CHECK: brxle %r0, %r2, 1 +#CHECK: error: offset out of range +#CHECK: brxle %r0, %r2, 0x10000 + + brxle %r0, %r2, -0x100002 + brxle %r0, %r2, -1 + brxle %r0, %r2, 1 + brxle %r0, %r2, 0x10000 + #CHECK: error: invalid operand #CHECK: c %r0, -1 #CHECK: error: invalid operand @@ -1419,6 +1447,23 @@ ex %r0, -1 ex %r0, 4096 +#CHECK: error: invalid use of indexed addressing +#CHECK: ectg 160(%r1,%r15),160(%r15), %r2 +#CHECK: error: invalid operand +#CHECK: ectg -1(%r1),160(%r15), %r2 +#CHECK: error: invalid operand +#CHECK: ectg 4096(%r1),160(%r15), %r2 +#CHECK: error: invalid operand +#CHECK: ectg 0(%r1),-1(%r15), %r2 +#CHECK: error: invalid operand +#CHECK: ectg 0(%r1),4096(%r15), %r2 + + ectg 160(%r1,%r15),160(%r15), %r2 + ectg -1(%r1),160(%r15), %r2 + ectg 4096(%r1),160(%r15), %r2 + ectg 0(%r1),-1(%r15), %r2 + ectg 0(%r1),4096(%r15), %r2 + #CHECK: error: invalid operand #CHECK: fidbr %f0, -1, %f0 #CHECK: error: invalid operand @@ -2371,6 +2416,38 @@ mvc 0(1,%r2), 0(%r1,%r2) mvc 0(-), 0 +#CHECK: error: invalid use of length addressing +#CHECK: mvck 0(%r1,%r1), 0(2,%r1), %r3 +#CHECK: error: %r0 used in an address +#CHECK: mvck 0(%r0,%r1), 0(%r1), %r3 +#CHECK: error: invalid operand +#CHECK: mvck -1(%r1,%r1), 0(%r1), %r3 +#CHECK: error: invalid operand +#CHECK: mvck 4096(%r1,%r1), 0(%r1), %r3 +#CHECK: error: invalid operand +#CHECK: mvck 0(%r1,%r1), -1(%r1), %r3 +#CHECK: error: invalid operand +#CHECK: mvck 0(%r1,%r1), 4096(%r1), %r3 +#CHECK: error: %r0 used in an address +#CHECK: mvck 0(%r1,%r0), 0(%r1), %r3 +#CHECK: error: %r0 used in an address +#CHECK: mvck 0(%r1,%r1), 0(%r0), %r3 +#CHECK: error: invalid use of indexed addressing +#CHECK: mvck 0(%r1,%r2), 0(%r1,%r2), %r3 +#CHECK: error: unknown token in expression +#CHECK: mvck 0(-), 0, %r3 + + mvck 0(%r1,%r1), 0(2,%r1), %r3 + mvck 0(%r0,%r1), 0(%r1), %r3 + mvck -1(%r1,%r1), 0(%r1), %r3 + mvck 4096(%r1,%r1), 0(%r1), %r3 + mvck 0(%r1,%r1), -1(%r1), %r3 + mvck 0(%r1,%r1), 4096(%r1), %r3 + mvck 0(%r1,%r0), 0(%r1), %r3 + mvck 0(%r1,%r1), 0(%r0), %r3 + mvck 0(%r1,%r2), 0(%r1,%r2), %r3 + mvck 0(-), 0, %r3 + #CHECK: error: invalid operand #CHECK: mvghi -1, 0 #CHECK: error: invalid operand @@ -2840,6 +2917,10 @@ popcnt %r0, %r0 #CHECK: error: invalid operand +#CHECK: pr %r0 + pr %r0 + +#CHECK: error: invalid operand #CHECK: risbg %r0,%r0,0,0,-1 #CHECK: error: invalid operand #CHECK: risbg %r0,%r0,0,0,64 @@ -3403,6 +3484,23 @@ stmy %r0, %r0, 524288 stmy %r0, %r0, 0(%r1,%r2) +#CHECK: error: invalid use of indexed addressing +#CHECK: strag 160(%r1,%r15),160(%r15) +#CHECK: error: invalid operand +#CHECK: strag -1(%r1),160(%r15) +#CHECK: error: invalid operand +#CHECK: strag 4096(%r1),160(%r15) +#CHECK: error: invalid operand +#CHECK: strag 0(%r1),-1(%r15) +#CHECK: error: invalid operand +#CHECK: strag 0(%r1),4096(%r15) + + strag 160(%r1,%r15),160(%r15) + strag -1(%r1),160(%r15) + strag 4096(%r1),160(%r15) + strag 0(%r1),-1(%r15) + strag 0(%r1),4096(%r15) + #CHECK: error: offset out of range #CHECK: strl %r0, -0x1000000002 #CHECK: error: offset out of range Index: llvm/trunk/test/MC/SystemZ/insn-good.s =================================================================== --- llvm/trunk/test/MC/SystemZ/insn-good.s +++ llvm/trunk/test/MC/SystemZ/insn-good.s @@ -1281,6 +1281,92 @@ #CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC16DBL brctg %r15, 0 +#CHECK: brxh %r0, %r2, .[[LAB:L.*]]-65536 # encoding: [0x84,0x02,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-65536)+2, kind: FK_390_PC16DBL + brxh %r0,%r2, -0x10000 +#CHECK: brxh %r0, %r2, .[[LAB:L.*]]-2 # encoding: [0x84,0x02,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC16DBL + brxh %r0, %r2, -2 +#CHECK: brxh %r0, %r2, .[[LAB:L.*]] # encoding: [0x84,0x02,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC16DBL + brxh %r0,%r2, 0 +#CHECK: brxh %r0, %r2, .[[LAB:L.*]]+65534 # encoding: [0x84,0x02,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+65534)+2, kind: FK_390_PC16DBL + brxh %r0,%r2, 0xfffe + +#CHECK: brxh %r0, %r2, foo # encoding: [0x84,0x02,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL +#CHECK: brxh %r14, %r2, foo # encoding: [0x84,0xe2,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL +#CHECK: brxh %r15, %r2, foo # encoding: [0x84,0xf2,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL + brxh %r0,%r2,foo + brxh %r14,%r2,foo + brxh %r15,%r2,foo + +#CHECK: brxh %r0, %r2, bar+100 # encoding: [0x84,0x02,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL +#CHECK: brxh %r14, %r2, bar+100 # encoding: [0x84,0xe2,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL +#CHECK: brxh %r15, %r2, bar+100 # encoding: [0x84,0xf2,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL + brxh %r0,%r2,bar+100 + brxh %r14,%r2,bar+100 + brxh %r15,%r2,bar+100 + +#CHECK: brxh %r0, %r2, bar@PLT # encoding: [0x84,0x02,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL +#CHECK: brxh %r14, %r2, bar@PLT # encoding: [0x84,0xe2,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL +#CHECK: brxh %r15, %r2, bar@PLT # encoding: [0x84,0xf2,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL + brxh %r0,%r2,bar@PLT + brxh %r14,%r2,bar@PLT + brxh %r15,%r2,bar@PLT + +#CHECK: brxle %r0, %r2, .[[LAB:L.*]]-65536 # encoding: [0x85,0x02,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-65536)+2, kind: FK_390_PC16DBL + brxle %r0,%r2, -0x10000 +#CHECK: brxle %r0, %r2, .[[LAB:L.*]]-2 # encoding: [0x85,0x02,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]-2)+2, kind: FK_390_PC16DBL + brxle %r0, %r2, -2 +#CHECK: brxle %r0, %r2, .[[LAB:L.*]] # encoding: [0x85,0x02,A,A] +#CHECK: fixup A - offset: 2, value: .[[LAB]]+2, kind: FK_390_PC16DBL + brxle %r0,%r2, 0 +#CHECK: brxle %r0, %r2, .[[LAB:L.*]]+65534 # encoding: [0x85,0x02,A,A] +#CHECK: fixup A - offset: 2, value: (.[[LAB]]+65534)+2, kind: FK_390_PC16DBL + brxle %r0,%r2, 0xfffe + +#CHECK: brxle %r0, %r2, foo # encoding: [0x85,0x02,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL +#CHECK: brxle %r14, %r2, foo # encoding: [0x85,0xe2,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL +#CHECK: brxle %r15, %r2, foo # encoding: [0x85,0xf2,A,A] +#CHECK: fixup A - offset: 2, value: foo+2, kind: FK_390_PC16DBL + brxle %r0,%r2,foo + brxle %r14,%r2,foo + brxle %r15,%r2,foo + +#CHECK: brxle %r0, %r2, bar+100 # encoding: [0x85,0x02,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL +#CHECK: brxle %r14, %r2, bar+100 # encoding: [0x85,0xe2,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL +#CHECK: brxle %r15, %r2, bar+100 # encoding: [0x85,0xf2,A,A] +#CHECK: fixup A - offset: 2, value: (bar+100)+2, kind: FK_390_PC16DBL + brxle %r0,%r2,bar+100 + brxle %r14,%r2,bar+100 + brxle %r15,%r2,bar+100 + +#CHECK: brxle %r0, %r2, bar@PLT # encoding: [0x85,0x02,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL +#CHECK: brxle %r14, %r2, bar@PLT # encoding: [0x85,0xe2,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL +#CHECK: brxle %r15, %r2, bar@PLT # encoding: [0x85,0xf2,A,A] +#CHECK: fixup A - offset: 2, value: bar@PLT+2, kind: FK_390_PC16DBL + brxle %r0,%r2,bar@PLT + brxle %r14,%r2,bar@PLT + brxle %r15,%r2,bar@PLT + #CHECK: c %r0, 0 # encoding: [0x59,0x00,0x00,0x00] #CHECK: c %r0, 4095 # encoding: [0x59,0x00,0x0f,0xff] #CHECK: c %r0, 0(%r1) # encoding: [0x59,0x00,0x10,0x00] @@ -5326,6 +5412,20 @@ ear %r7, %a8 ear %r15, %a15 +#CHECK: ectg 0, 0, %r0 # encoding: [0xc8,0x01,0x00,0x00,0x00,0x00] +#CHECK: ectg 0(%r1), 0(%r15), %r2 # encoding: [0xc8,0x21,0x10,0x00,0xf0,0x00] +#CHECK: ectg 1(%r1), 0(%r15), %r2 # encoding: [0xc8,0x21,0x10,0x01,0xf0,0x00] +#CHECK: ectg 4095(%r1), 0(%r15), %r2 # encoding: [0xc8,0x21,0x1f,0xff,0xf0,0x00] +#CHECK: ectg 0(%r1), 1(%r15), %r2 # encoding: [0xc8,0x21,0x10,0x00,0xf0,0x01] +#CHECK: ectg 0(%r1), 4095(%r15), %r2 # encoding: [0xc8,0x21,0x10,0x00,0xff,0xff] + + ectg 0,0,%r0 + ectg 0(%r1),0(%r15),%r2 + ectg 1(%r1),0(%r15),%r2 + ectg 4095(%r1),0(%r15),%r2 + ectg 0(%r1),1(%r15),%r2 + ectg 0(%r1),4095(%r15),%r2 + #CHECK: ex %r0, 0 # encoding: [0x44,0x00,0x00,0x00] #CHECK: ex %r0, 4095 # encoding: [0x44,0x00,0x0f,0xff] #CHECK: ex %r0, 0(%r1) # encoding: [0x44,0x00,0x10,0x00] @@ -7652,6 +7752,32 @@ mvc 0(256,%r1), 0 mvc 0(256,%r15), 0 +#CHECK: mvck 0(%r1), 0, %r3 # encoding: [0xd9,0x03,0x10,0x00,0x00,0x00] +#CHECK: mvck 0(%r1), 0(%r1), %r3 # encoding: [0xd9,0x03,0x10,0x00,0x10,0x00] +#CHECK: mvck 0(%r1), 0(%r15), %r3 # encoding: [0xd9,0x03,0x10,0x00,0xf0,0x00] +#CHECK: mvck 0(%r1), 4095, %r3 # encoding: [0xd9,0x03,0x10,0x00,0x0f,0xff] +#CHECK: mvck 0(%r1), 4095(%r1), %r3 # encoding: [0xd9,0x03,0x10,0x00,0x1f,0xff] +#CHECK: mvck 0(%r1), 4095(%r15), %r3 # encoding: [0xd9,0x03,0x10,0x00,0xff,0xff] +#CHECK: mvck 0(%r2,%r1), 0, %r3 # encoding: [0xd9,0x23,0x10,0x00,0x00,0x00] +#CHECK: mvck 0(%r2,%r15), 0, %r3 # encoding: [0xd9,0x23,0xf0,0x00,0x00,0x00] +#CHECK: mvck 4095(%r2,%r1), 0, %r3 # encoding: [0xd9,0x23,0x1f,0xff,0x00,0x00] +#CHECK: mvck 4095(%r2,%r15), 0, %r3 # encoding: [0xd9,0x23,0xff,0xff,0x00,0x00] +#CHECK: mvck 0(%r2,%r1), 0, %r3 # encoding: [0xd9,0x23,0x10,0x00,0x00,0x00] +#CHECK: mvck 0(%r2,%r15), 0, %r3 # encoding: [0xd9,0x23,0xf0,0x00,0x00,0x00] + + mvck 0(%r1), 0, %r3 + mvck 0(%r1), 0(%r1), %r3 + mvck 0(%r1), 0(%r15), %r3 + mvck 0(%r1), 4095, %r3 + mvck 0(%r1), 4095(%r1), %r3 + mvck 0(%r1), 4095(%r15), %r3 + mvck 0(%r2,%r1), 0, %r3 + mvck 0(%r2,%r15), 0, %r3 + mvck 4095(%r2,%r1), 0, %r3 + mvck 4095(%r2,%r15), 0, %r3 + mvck 0(%r2,%r1), 0, %r3 + mvck 0(%r2,%r15), 0, %r3 + #CHECK: mvghi 0, 0 # encoding: [0xe5,0x48,0x00,0x00,0x00,0x00] #CHECK: mvghi 4095, 0 # encoding: [0xe5,0x48,0x0f,0xff,0x00,0x00] #CHECK: mvghi 0, -32768 # encoding: [0xe5,0x48,0x00,0x00,0x80,0x00] @@ -8273,6 +8399,9 @@ pfdrl 7, frob@PLT pfdrl 8, frob@PLT +#CHECK: pr # encoding: [0x01,0x01] + pr + #CHECK: risbg %r0, %r0, 0, 0, 0 # encoding: [0xec,0x00,0x00,0x00,0x00,0x55] #CHECK: risbg %r0, %r0, 0, 0, 63 # encoding: [0xec,0x00,0x00,0x00,0x3f,0x55] #CHECK: risbg %r0, %r0, 0, 255, 0 # encoding: [0xec,0x00,0x00,0xff,0x00,0x55] @@ -9409,6 +9538,28 @@ stmy %r0,%r0,524287(%r1) stmy %r0,%r0,524287(%r15) +#CHECK: strag 0, 0 # encoding: [0xe5,0x02,0x00,0x00,0x00,0x00] +#CHECK: strag 0(%r1), 0(%r2) # encoding: [0xe5,0x02,0x10,0x00,0x20,0x00] +#CHECK: strag 160(%r1), 320(%r15) # encoding: [0xe5,0x02,0x10,0xa0,0xf1,0x40] +#CHECK: strag 0(%r1), 4095 # encoding: [0xe5,0x02,0x10,0x00,0x0f,0xff] +#CHECK: strag 0(%r1), 4095(%r2) # encoding: [0xe5,0x02,0x10,0x00,0x2f,0xff] +#CHECK: strag 0(%r1), 4095(%r15) # encoding: [0xe5,0x02,0x10,0x00,0xff,0xff] +#CHECK: strag 0(%r1), 0 # encoding: [0xe5,0x02,0x10,0x00,0x00,0x00] +#CHECK: strag 0(%r15), 0 # encoding: [0xe5,0x02,0xf0,0x00,0x00,0x00] +#CHECK: strag 4095(%r1), 0 # encoding: [0xe5,0x02,0x1f,0xff,0x00,0x00] +#CHECK: strag 4095(%r15), 0 # encoding: [0xe5,0x02,0xff,0xff,0x00,0x00] + + strag 0, 0 + strag 0(%r1), 0(%r2) + strag 160(%r1), 320(%r15) + strag 0(%r1), 4095 + strag 0(%r1), 4095(%r2) + strag 0(%r1), 4095(%r15) + strag 0(%r1), 0 + strag 0(%r15), 0 + strag 4095(%r1), 0 + strag 4095(%r15), 0 + #CHECK: strl %r0, .[[LAB:L.*]]-4294967296 # encoding: [0xc4,0x0f,A,A,A,A] #CHECK: fixup A - offset: 2, value: (.[[LAB]]-4294967296)+2, kind: FK_390_PC32DBL strl %r0, -0x100000000