Index: lib/Target/Mips/InstPrinter/MipsInstPrinter.h =================================================================== --- lib/Target/Mips/InstPrinter/MipsInstPrinter.h +++ lib/Target/Mips/InstPrinter/MipsInstPrinter.h @@ -97,7 +97,6 @@ void printUImm(const MCInst *MI, int opNum, raw_ostream &O); void printMemOperand(const MCInst *MI, int opNum, raw_ostream &O); void printMemOperandEA(const MCInst *MI, int opNum, raw_ostream &O); - void printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O); void printRegisterPair(const MCInst *MI, int opNum, raw_ostream &O); void printSHFMask(const MCInst *MI, int opNum, raw_ostream &O); Index: lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp =================================================================== --- lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp +++ lib/Target/Mips/InstPrinter/MipsInstPrinter.cpp @@ -192,12 +192,6 @@ } void MipsInstPrinter:: -printFCCOperand(const MCInst *MI, int opNum, raw_ostream &O) { - const MCOperand& MO = MI->getOperand(opNum); - O << MipsFCCToString((Mips::CondCode)MO.getImm()); -} - -void MipsInstPrinter:: printRegisterPair(const MCInst *MI, int opNum, raw_ostream &O) { printRegName(O, MI->getOperand(opNum).getReg()); } Index: lib/Target/Mips/MicroMipsInstrFPU.td =================================================================== --- lib/Target/Mips/MicroMipsInstrFPU.td +++ lib/Target/Mips/MicroMipsInstrFPU.td @@ -26,11 +26,6 @@ def SUXC1_MM : MMRel, SWXC1_FT<"suxc1", AFGR64Opnd, II_SUXC1>, SWXC1_FM_MM<0x188>, INSN_MIPS5_32R2_NOT_32R6_64R6; -def FCMP_S32_MM : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, - CEQS_FM_MM<0>; -def FCMP_D32_MM : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, - CEQS_FM_MM<1>; - def BC1F_MM : MMRel, BC1F_FT<"bc1f", brtarget_mm, II_BC1F, MIPS_BRANCH_F>, BC1F_FM_MM<0x1c>, ISA_MIPS1_NOT_32R6_64R6; def BC1T_MM : MMRel, BC1F_FT<"bc1t", brtarget_mm, II_BC1T, MIPS_BRANCH_T>, @@ -166,4 +161,76 @@ def : LoadRegImmPat; def : StoreRegImmPat; } + + // Floating point comparisons + multiclass C_COND_M_MM fmt, + InstrItinClass itin> { + def C_F_#NAME : MMRel, C_COND_FT<"f", TypeStr, RC, itin>, + C_COND_FM_MM; + def C_UN_#NAME : MMRel, C_COND_FT<"un", TypeStr, RC, itin>, + C_COND_FM_MM; + def C_EQ_#NAME : MMRel, C_COND_FT<"eq", TypeStr, RC, itin>, + C_COND_FM_MM; + def C_UEQ_#NAME : MMRel, C_COND_FT<"ueq", TypeStr, RC, itin>, + C_COND_FM_MM; + def C_OLT_#NAME : MMRel, C_COND_FT<"olt", TypeStr, RC, itin>, + C_COND_FM_MM; + def C_ULT_#NAME : MMRel, C_COND_FT<"ult", TypeStr, RC, itin>, + C_COND_FM_MM; + def C_OLE_#NAME : MMRel, C_COND_FT<"ole", TypeStr, RC, itin>, + C_COND_FM_MM; + def C_ULE_#NAME : MMRel, C_COND_FT<"ule", TypeStr, RC, itin>, + C_COND_FM_MM; + def C_SF_#NAME : MMRel, C_COND_FT<"sf", TypeStr, RC, itin>, + C_COND_FM_MM; + def C_NGLE_#NAME : MMRel, C_COND_FT<"ngle", TypeStr, RC, itin>, + C_COND_FM_MM; + def C_SEQ_#NAME : MMRel, C_COND_FT<"seq", TypeStr, RC, itin>, + C_COND_FM_MM; + def C_NGL_#NAME : MMRel, C_COND_FT<"ngl", TypeStr, RC, itin>, + C_COND_FM_MM; + def C_LT_#NAME : MMRel, C_COND_FT<"lt", TypeStr, RC, itin>, + C_COND_FM_MM; + def C_NGE_#NAME : MMRel, C_COND_FT<"nge", TypeStr, RC, itin>, + C_COND_FM_MM; + def C_LE_#NAME : MMRel, C_COND_FT<"le", TypeStr, RC, itin>, + C_COND_FM_MM; + def C_NGT_#NAME : MMRel, C_COND_FT<"ngt", TypeStr, RC, itin>, + C_COND_FM_MM; + } + + defm S_MM : C_COND_M_MM<"s", FGR32Opnd, 0b00, II_C_CC_S>; + defm D32_MM : C_COND_M_MM<"d", AFGR64Opnd, 0b01, II_C_CC_D>, FGR_32; + + // Floating point branch patterns + defm S_MM : FPBrcondPats, ISA_MIPS1_NOT_32R6_64R6; + defm D32_MM : FPBrcondPats, FGR_32, ISA_MIPS1_NOT_32R6_64R6; + + // Floating point setcc + defm S_MM : FPSetccPats; + defm D32_MM : FPSetccPats, FGR_32; + + // Floating point select patterns + defm : FPSelectPats, + ISA_MIPS1_NOT_32R6_64R6; + defm : FPSelectPats, + FGR_32, ISA_MIPS1_NOT_32R6_64R6; + + defm : FPSelectPats, + FGR_32, ISA_MIPS1_NOT_32R6_64R6; + defm : FPSelectPats, + FGR_32, ISA_MIPS1_NOT_32R6_64R6; + + defm : FPSelectPats, + ISA_MIPS1_NOT_32R6_64R6; + defm : FPSelectPats, + FGR_32, ISA_MIPS1_NOT_32R6_64R6; +} + +//===----------------------------------------------------------------------===// +// Instruction aliases. +//===----------------------------------------------------------------------===// +let AdditionalPredicates = [InMicroMips] in { + defm S_MM : FPCAliases; + defm D32_MM : FPCAliases; } Index: lib/Target/Mips/MicroMipsInstrFormats.td =================================================================== --- lib/Target/Mips/MicroMipsInstrFormats.td +++ lib/Target/Mips/MicroMipsInstrFormats.td @@ -722,6 +722,23 @@ list Pattern = []; } +class C_COND_FM_MM fmt, bits<4> cond> : MMArch { + bits <5> ft; + bits <5> fs; + bits <3> cc; + + bits<32> Inst; + + let Inst{31-26} = 0b010101; + let Inst{25-21} = ft; + let Inst{20-16} = fs; + let Inst{15-13} = cc; + let Inst{12} = 0; + let Inst{11-10} = fmt; + let Inst{9-6} = cond; + let Inst{5-0} = 0b111100; +} + class LWXC1_FM_MM funct> : MMArch { bits<5> fd; bits<5> base; Index: lib/Target/Mips/MipsAsmPrinter.h =================================================================== --- lib/Target/Mips/MipsAsmPrinter.h +++ lib/Target/Mips/MipsAsmPrinter.h @@ -136,8 +136,6 @@ void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O); void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O); void printMemOperandEA(const MachineInstr *MI, int opNum, raw_ostream &O); - void printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, - const char *Modifier = nullptr); void printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O); void EmitStartOfAsmFile(Module &M) override; void EmitEndOfAsmFile(Module &M) override; Index: lib/Target/Mips/MipsAsmPrinter.cpp =================================================================== --- lib/Target/Mips/MipsAsmPrinter.cpp +++ lib/Target/Mips/MipsAsmPrinter.cpp @@ -654,13 +654,6 @@ } void MipsAsmPrinter:: -printFCCOperand(const MachineInstr *MI, int opNum, raw_ostream &O, - const char *Modifier) { - const MachineOperand &MO = MI->getOperand(opNum); - O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm()); -} - -void MipsAsmPrinter:: printRegisterList(const MachineInstr *MI, int opNum, raw_ostream &O) { for (int i = opNum, e = MI->getNumOperands(); i != e; ++i) { if (i != opNum) O << ", "; Index: lib/Target/Mips/MipsCondMov.td =================================================================== --- lib/Target/Mips/MipsCondMov.td +++ lib/Target/Mips/MipsCondMov.td @@ -261,22 +261,220 @@ defm : MovnPats, INSN_MIPS4_32_NOT_32R6_64R6, FGR_64; +multiclass FPSetccPats { + def : MipsPat<(seteq RC:$lhs, RC:$rhs), + (MOVF ZERO, (!cast("C_EQ_"#NAME) RC:$lhs, RC:$rhs), + ADD)>; + def : MipsPat<(setgt RC:$lhs, RC:$rhs), + (MOVT ZERO, (!cast("C_ULE_"#NAME) RC:$lhs, RC:$rhs), + ADD)>; + def : MipsPat<(setge RC:$lhs, RC:$rhs), + (MOVT ZERO, (!cast("C_ULT_"#NAME) RC:$lhs, RC:$rhs), + ADD)>; + def : MipsPat<(setlt RC:$lhs, RC:$rhs), + (MOVF ZERO, (!cast("C_OLT_"#NAME) RC:$lhs, RC:$rhs), + ADD)>; + def : MipsPat<(setle RC:$lhs, RC:$rhs), + (MOVF ZERO, (!cast("C_OLE_"#NAME) RC:$lhs, RC:$rhs), + ADD)>; + def : MipsPat<(setne RC:$lhs, RC:$rhs), + (MOVT ZERO, (!cast("C_UEQ_"#NAME) RC:$lhs, RC:$rhs), + ADD)>; + def : MipsPat<(setoeq RC:$lhs, RC:$rhs), + (MOVF ZERO, (!cast("C_EQ_"#NAME) RC:$lhs, RC:$rhs), + ADD)>; + def : MipsPat<(setogt RC:$lhs, RC:$rhs), + (MOVT ZERO, (!cast("C_ULE_"#NAME) RC:$lhs, RC:$rhs), + ADD)>; + def : MipsPat<(setoge RC:$lhs, RC:$rhs), + (MOVT ZERO, (!cast("C_ULT_"#NAME) RC:$lhs, RC:$rhs), + ADD)>; + def : MipsPat<(setolt RC:$lhs, RC:$rhs), + (MOVF ZERO, (!cast("C_OLT_"#NAME) RC:$lhs, RC:$rhs), + ADD)>; + def : MipsPat<(setole RC:$lhs, RC:$rhs), + (MOVF ZERO, (!cast("C_OLE_"#NAME) RC:$lhs, RC:$rhs), + ADD)>; + def : MipsPat<(setone RC:$lhs, RC:$rhs), + (MOVT ZERO, (!cast("C_UEQ_"#NAME) RC:$lhs, RC:$rhs), + ADD)>; + def : MipsPat<(seto RC:$lhs, RC:$rhs), + (MOVT ZERO, (!cast("C_UN_"#NAME) RC:$lhs, RC:$rhs), + ADD)>; + def : MipsPat<(setuo RC:$lhs, RC:$rhs), + (MOVF ZERO, (!cast("C_UN_"#NAME) RC:$lhs, RC:$rhs), + ADD)>; + def : MipsPat<(setueq RC:$lhs, RC:$rhs), + (MOVF ZERO, (!cast("C_UEQ_"#NAME) RC:$lhs, RC:$rhs), + ADD)>; + def : MipsPat<(setugt RC:$lhs, RC:$rhs), + (MOVT ZERO, (!cast("C_OLE_"#NAME) RC:$lhs, RC:$rhs), + ADD)>; + def : MipsPat<(setuge RC:$lhs, RC:$rhs), + (MOVT ZERO, (!cast("C_OLT_"#NAME) RC:$lhs, RC:$rhs), + ADD)>; + def : MipsPat<(setult RC:$lhs, RC:$rhs), + (MOVF ZERO, (!cast("C_ULT_"#NAME) RC:$lhs, RC:$rhs), + ADD)>; + def : MipsPat<(setule RC:$lhs, RC:$rhs), + (MOVF ZERO, (!cast("C_ULE_"#NAME) RC:$lhs, RC:$rhs), + ADD)>; + def : MipsPat<(setune RC:$lhs, RC:$rhs), + (MOVT ZERO, (!cast("C_EQ_"#NAME) RC:$lhs, RC:$rhs), + ADD)>; +} + +let AdditionalPredicates = [NotInMicroMips] in { + defm S : FPSetccPats, + INSN_MIPS4_32_NOT_32R6_64R6; + defm D32 : FPSetccPats, FGR_32, + INSN_MIPS4_32_NOT_32R6_64R6; + defm D64 : FPSetccPats, FGR_64, + INSN_MIPS4_32_NOT_32R6_64R6; +} + +multiclass FPSelectPats { + // Ordered + def : MipsPat<(select (i32 (setoeq RC:$lhs, RC:$rhs)), RO:$t, RO:$f), + (MOVT RO:$t, (!cast("C_EQ_"#Type) RC:$lhs, + RC:$rhs), + RO:$f)>; + def : MipsPat<(select (i32 (setogt RC:$lhs, RC:$rhs)), RO:$t, RO:$f), + (MOVF RO:$t, (!cast("C_ULE_"#Type) RC:$lhs, + RC:$rhs), + RO:$f)>; + def : MipsPat<(select (i32 (setoge RC:$lhs, RC:$rhs)), RO:$t, RO:$f), + (MOVF RO:$t, (!cast("C_ULT_"#Type) RC:$lhs, + RC:$rhs), + RO:$f)>; + def : MipsPat<(select (i32 (setolt RC:$lhs, RC:$rhs)), RO:$t, RO:$f), + (MOVT RO:$t, (!cast("C_OLT_"#Type) RC:$lhs, + RC:$rhs), + RO:$f)>; + def : MipsPat<(select (i32 (setole RC:$lhs, RC:$rhs)), RO:$t, RO:$f), + (MOVT RO:$t, (!cast("C_OLE_"#Type) RC:$lhs, + RC:$rhs), + RO:$f)>; + def : MipsPat<(select (i32 (setone RC:$lhs, RC:$rhs)), RO:$t, RO:$f), + (MOVF RO:$t, (!cast("C_UEQ_"#Type) RC:$lhs, + RC:$rhs), + RO:$f)>; + def : MipsPat<(select (i32 (seto RC:$lhs, RC:$rhs)), RO:$t, RO:$f), + (MOVF RO:$t, (!cast("C_UN_"#Type) RC:$lhs, + RC:$rhs), + RO:$f)>; + // Unordered + def : MipsPat<(select (i32 (setuo RC:$lhs, RC:$rhs)), RO:$t, RO:$f), + (MOVT RO:$t, (!cast("C_UN_"#Type) RC:$lhs, + RC:$rhs), + RO:$f)>; + def : MipsPat<(select (i32 (setueq RC:$lhs, RC:$rhs)), RO:$t, RO:$f), + (MOVT RO:$t, (!cast("C_UEQ_"#Type) RC:$lhs, + RC:$rhs), + RO:$f)>; + def : MipsPat<(select (i32 (setugt RC:$lhs, RC:$rhs)), RO:$t, RO:$f), + (MOVF RO:$t, (!cast("C_ULE_"#Type) RC:$lhs, + RC:$rhs), + RO:$f)>; + def : MipsPat<(select (i32 (setuge RC:$lhs, RC:$rhs)), RO:$t, RO:$f), + (MOVF RO:$t, (!cast("C_ULE_"#Type) RC:$lhs, + RC:$rhs), + RO:$f)>; + def : MipsPat<(select (i32 (setult RC:$lhs, RC:$rhs)), RO:$t, RO:$f), + (MOVT RO:$t, (!cast("C_ULT_"#Type) RC:$lhs, + RC:$rhs), + RO:$f)>; + def : MipsPat<(select (i32 (setule RC:$lhs, RC:$rhs)), RO:$t, RO:$f), + (MOVT RO:$t, (!cast("C_ULE_"#Type) RC:$lhs, + RC:$rhs), + RO:$f)>; + def : MipsPat<(select (i32 (setune RC:$lhs, RC:$rhs)), RO:$t, RO:$f), + (MOVF RO:$t, (!cast("C_UEQ_"#Type) RC:$lhs, + RC:$rhs), + RO:$f)>; + def : MipsPat<(select (i32 (setuo RC:$lhs, RC:$rhs)), RO:$t, RO:$f), + (MOVT RO:$t, (!cast("C_EQ_"#Type) RC:$lhs, + RC:$rhs), + RO:$f)>; + // Unspecified ordering - treated as ordered. + def : MipsPat<(select (i32 (seteq RC:$lhs, RC:$rhs)), RO:$t, RO:$f), + (MOVT RO:$t, (!cast("C_EQ_"#Type) RC:$lhs, + RC:$rhs), + RO:$f)>; + def : MipsPat<(select (i32 (setgt RC:$lhs, RC:$rhs)), RO:$t, RO:$f), + (MOVF RO:$t, (!cast("C_OLE_"#Type) RC:$lhs, + RC:$rhs), + RO:$f)>; + def : MipsPat<(select (i32 (setge RC:$lhs, RC:$rhs)), RO:$t, RO:$f), + (MOVF RO:$t, (!cast("C_LT_"#Type) RC:$lhs, + RC:$rhs), + RO:$f)>; + def : MipsPat<(select (i32 (setlt RC:$lhs, RC:$rhs)), RO:$t, RO:$f), + (MOVT RO:$t, (!cast("C_LT_"#Type) RC:$lhs, + RC:$rhs), + RO:$f)>; + def : MipsPat<(select (i32 (setle RC:$lhs, RC:$rhs)), RO:$t, RO:$f), + (MOVT RO:$t, (!cast("C_OLE_"#Type) RC:$lhs, + RC:$rhs), + RO:$f)>; + def : MipsPat<(select (i32 (setne RC:$lhs, RC:$rhs)), RO:$t, RO:$f), + (MOVF RO:$t, (!cast("C_EQ_"#Type) RC:$lhs, + RC:$rhs), + RO:$f)>; +} + +let AdditionalPredicates = [NotInMicroMips] in { + defm : FPSelectPats, + INSN_MIPS4_32_NOT_32R6_64R6; + defm : FPSelectPats, + FGR_32, INSN_MIPS4_32_NOT_32R6_64R6; + defm : FPSelectPats, + FGR_64, INSN_MIPS4_32_NOT_32R6_64R6; + + defm : FPSelectPats, + FGR_32, INSN_MIPS4_32_NOT_32R6_64R6; + defm : FPSelectPats, + FGR_32, INSN_MIPS4_32_NOT_32R6_64R6; + + + defm : FPSelectPats, + FGR_64, INSN_MIPS4_32_NOT_32R6_64R6; + defm : FPSelectPats, + FGR_64, INSN_MIPS4_32_NOT_32R6_64R6; + + defm : FPSelectPats, + INSN_MIPS4_32_NOT_32R6_64R6; + defm : FPSelectPats, + FGR_32, INSN_MIPS4_32_NOT_32R6_64R6; + defm : FPSelectPats, + FGR_64, INSN_MIPS4_32_NOT_32R6_64R6; + + defm : FPSelectPats, + INSN_MIPS4_32_NOT_32R6_64R6; + defm : FPSelectPats, + FGR_32, INSN_MIPS4_32_NOT_32R6_64R6; + defm : FPSelectPats, + FGR_64, INSN_MIPS4_32_NOT_32R6_64R6; +} + // For targets that don't have conditional-move instructions // we have to match SELECT nodes with pseudo instructions. let usesCustomInserter = 1 in { class Select_Pseudo : - PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F), + PseudoSE<(outs RC:$dst), (ins RC:$T, GPR32Opnd:$cond, RC:$F), [(set RC:$dst, (select GPR32Opnd:$cond, RC:$T, RC:$F))]>, ISA_MIPS1_NOT_4_32; class SelectFP_Pseudo_T : - PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F), - [(set RC:$dst, (MipsCMovFP_T RC:$T, GPR32Opnd:$cond, RC:$F))]>, + PseudoSE<(outs RC:$dst), (ins RC:$T, FCC:$cond, RC:$F), + [(set RC:$dst, (MipsCMovFP_T RC:$T, FCC:$cond, RC:$F))]>, ISA_MIPS1_NOT_4_32; class SelectFP_Pseudo_F : - PseudoSE<(outs RC:$dst), (ins GPR32Opnd:$cond, RC:$T, RC:$F), - [(set RC:$dst, (MipsCMovFP_F RC:$T, GPR32Opnd:$cond, RC:$F))]>, + PseudoSE<(outs RC:$dst), (ins RC:$T, FCC:$cond, RC:$F), + [(set RC:$dst, (MipsCMovFP_F RC:$T, FCC:$cond, RC:$F))]>, ISA_MIPS1_NOT_4_32; } @@ -297,3 +495,12 @@ def PseudoSELECTFP_F_S : SelectFP_Pseudo_F; def PseudoSELECTFP_F_D32 : SelectFP_Pseudo_F, FGR_32; def PseudoSELECTFP_F_D64 : SelectFP_Pseudo_F, FGR_64; + +let AdditionalPredicates = [NotInMicroMips] in { + defm : FPSelectPats, ISA_MIPS1_NOT_4_32; + defm : FPSelectPats, FGR_32, ISA_MIPS1_NOT_4_32; + defm : FPSelectPats, FGR_64, ISA_MIPS1_NOT_4_32; +} Index: lib/Target/Mips/MipsFastISel.cpp =================================================================== --- lib/Target/Mips/MipsFastISel.cpp +++ lib/Target/Mips/MipsFastISel.cpp @@ -709,8 +709,7 @@ unsigned RegWithOne = createResultReg(&Mips::GPR32RegClass); emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0); emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1); - emitInst(Opc).addReg(LeftReg).addReg(RightReg).addReg( - Mips::FCC0, RegState::ImplicitDefine); + emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg).addReg(RightReg); emitInst(CondMovOpc, ResultReg) .addReg(RegWithOne) .addReg(Mips::FCC0) Index: lib/Target/Mips/MipsISelLowering.h =================================================================== --- lib/Target/Mips/MipsISelLowering.h +++ lib/Target/Mips/MipsISelLowering.h @@ -108,6 +108,9 @@ Ext, Ins, + // Pseudo Node used to read the FCC registers. + PseudoReadFCC, + // EXTR.W instrinsic nodes. EXTP, EXTPDP, Index: lib/Target/Mips/MipsISelLowering.cpp =================================================================== --- lib/Target/Mips/MipsISelLowering.cpp +++ lib/Target/Mips/MipsISelLowering.cpp @@ -144,6 +144,7 @@ case MipsISD::Sync: return "MipsISD::Sync"; case MipsISD::Ext: return "MipsISD::Ext"; case MipsISD::Ins: return "MipsISD::Ins"; + case MipsISD::PseudoReadFCC: return "MipsISD::PseudoReadFCC"; case MipsISD::LWL: return "MipsISD::LWL"; case MipsISD::LWR: return "MipsISD::LWR"; case MipsISD::SWL: return "MipsISD::SWL"; @@ -274,12 +275,6 @@ setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); setOperationAction(ISD::JumpTable, MVT::i32, Custom); setOperationAction(ISD::ConstantPool, MVT::i32, Custom); - setOperationAction(ISD::SELECT, MVT::f32, Custom); - setOperationAction(ISD::SELECT, MVT::f64, Custom); - setOperationAction(ISD::SELECT, MVT::i32, Custom); - setOperationAction(ISD::SETCC, MVT::f32, Custom); - setOperationAction(ISD::SETCC, MVT::f64, Custom); - setOperationAction(ISD::BRCOND, MVT::Other, Custom); setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); @@ -290,7 +285,6 @@ setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); setOperationAction(ISD::JumpTable, MVT::i64, Custom); setOperationAction(ISD::ConstantPool, MVT::i64, Custom); - setOperationAction(ISD::SELECT, MVT::i64, Custom); setOperationAction(ISD::LOAD, MVT::i64, Custom); setOperationAction(ISD::STORE, MVT::i64, Custom); setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom); @@ -500,79 +494,6 @@ return SDValue(); } -static Mips::CondCode condCodeToFCC(ISD::CondCode CC) { - switch (CC) { - default: llvm_unreachable("Unknown fp condition code!"); - case ISD::SETEQ: - case ISD::SETOEQ: return Mips::FCOND_OEQ; - case ISD::SETUNE: return Mips::FCOND_UNE; - case ISD::SETLT: - case ISD::SETOLT: return Mips::FCOND_OLT; - case ISD::SETGT: - case ISD::SETOGT: return Mips::FCOND_OGT; - case ISD::SETLE: - case ISD::SETOLE: return Mips::FCOND_OLE; - case ISD::SETGE: - case ISD::SETOGE: return Mips::FCOND_OGE; - case ISD::SETULT: return Mips::FCOND_ULT; - case ISD::SETULE: return Mips::FCOND_ULE; - case ISD::SETUGT: return Mips::FCOND_UGT; - case ISD::SETUGE: return Mips::FCOND_UGE; - case ISD::SETUO: return Mips::FCOND_UN; - case ISD::SETO: return Mips::FCOND_OR; - case ISD::SETNE: - case ISD::SETONE: return Mips::FCOND_ONE; - case ISD::SETUEQ: return Mips::FCOND_UEQ; - } -} - - -/// This function returns true if the floating point conditional branches and -/// conditional moves which use condition code CC should be inverted. -static bool invertFPCondCodeUser(Mips::CondCode CC) { - if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) - return false; - - assert((CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) && - "Illegal Condition Code"); - - return true; -} - -// Creates and returns an FPCmp node from a setcc node. -// Returns Op if setcc is not a floating point comparison. -static SDValue createFPCmp(SelectionDAG &DAG, const SDValue &Op) { - // must be a SETCC node - if (Op.getOpcode() != ISD::SETCC) - return Op; - - SDValue LHS = Op.getOperand(0); - - if (!LHS.getValueType().isFloatingPoint()) - return Op; - - SDValue RHS = Op.getOperand(1); - SDLoc DL(Op); - - // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of - // node if necessary. - ISD::CondCode CC = cast(Op.getOperand(2))->get(); - - return DAG.getNode(MipsISD::FPCmp, DL, MVT::Glue, LHS, RHS, - DAG.getConstant(condCodeToFCC(CC), DL, MVT::i32)); -} - -// Creates and returns a CMovFPT/F node. -static SDValue createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, - SDValue False, const SDLoc &DL) { - ConstantSDNode *CC = cast(Cond.getOperand(2)); - bool invert = invertFPCondCodeUser((Mips::CondCode)CC->getSExtValue()); - SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); - - return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, - True.getValueType(), True, FCC0, False, Cond); -} - static SDValue performSELECTCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const MipsSubtarget &Subtarget) { @@ -894,14 +815,11 @@ switch (Op.getOpcode()) { case ISD::BR_JT: return lowerBR_JT(Op, DAG); - case ISD::BRCOND: return lowerBRCOND(Op, DAG); case ISD::ConstantPool: return lowerConstantPool(Op, DAG); case ISD::GlobalAddress: return lowerGlobalAddress(Op, DAG); case ISD::BlockAddress: return lowerBlockAddress(Op, DAG); case ISD::GlobalTLSAddress: return lowerGlobalTLSAddress(Op, DAG); case ISD::JumpTable: return lowerJumpTable(Op, DAG); - case ISD::SELECT: return lowerSELECT(Op, DAG); - case ISD::SETCC: return lowerSETCC(Op, DAG); case ISD::VASTART: return lowerVASTART(Op, DAG); case ISD::VAARG: return lowerVAARG(Op, DAG); case ISD::FCOPYSIGN: return lowerFCOPYSIGN(Op, DAG); @@ -1693,58 +1611,6 @@ return DAG.getNode(ISD::BRIND, DL, MVT::Other, Chain, Addr); } -SDValue MipsTargetLowering::lowerBRCOND(SDValue Op, SelectionDAG &DAG) const { - // The first operand is the chain, the second is the condition, the third is - // the block to branch to if the condition is true. - SDValue Chain = Op.getOperand(0); - SDValue Dest = Op.getOperand(2); - SDLoc DL(Op); - - assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); - SDValue CondRes = createFPCmp(DAG, Op.getOperand(1)); - - // Return if flag is not set by a floating point comparison. - if (CondRes.getOpcode() != MipsISD::FPCmp) - return Op; - - SDValue CCNode = CondRes.getOperand(2); - Mips::CondCode CC = - (Mips::CondCode)cast(CCNode)->getZExtValue(); - unsigned Opc = invertFPCondCodeUser(CC) ? Mips::BRANCH_F : Mips::BRANCH_T; - SDValue BrCode = DAG.getConstant(Opc, DL, MVT::i32); - SDValue FCC0 = DAG.getRegister(Mips::FCC0, MVT::i32); - return DAG.getNode(MipsISD::FPBrcond, DL, Op.getValueType(), Chain, BrCode, - FCC0, Dest, CondRes); -} - -SDValue MipsTargetLowering:: -lowerSELECT(SDValue Op, SelectionDAG &DAG) const -{ - assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); - SDValue Cond = createFPCmp(DAG, Op.getOperand(0)); - - // Return if flag is not set by a floating point comparison. - if (Cond.getOpcode() != MipsISD::FPCmp) - return Op; - - return createCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), - SDLoc(Op)); -} - -SDValue MipsTargetLowering::lowerSETCC(SDValue Op, SelectionDAG &DAG) const { - assert(!Subtarget.hasMips32r6() && !Subtarget.hasMips64r6()); - SDValue Cond = createFPCmp(DAG, Op); - - assert(Cond.getOpcode() == MipsISD::FPCmp && - "Floating point operand expected."); - - SDLoc DL(Op); - SDValue True = DAG.getConstant(1, DL, MVT::i32); - SDValue False = DAG.getConstant(0, DL, MVT::i32); - - return createCMovFP(DAG, Cond, True, False, DL); -} - SDValue MipsTargetLowering::lowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { EVT Ty = Op.getValueType(); @@ -3990,12 +3856,12 @@ if (isFPCmp) { // bc1[tf] cc, sinkMBB BuildMI(BB, DL, TII->get(Opc)) - .addReg(MI.getOperand(1).getReg()) + .addReg(MI.getOperand(2).getReg()) .addMBB(sinkMBB); } else { // bne rs, $0, sinkMBB BuildMI(BB, DL, TII->get(Opc)) - .addReg(MI.getOperand(1).getReg()) + .addReg(MI.getOperand(2).getReg()) .addReg(Mips::ZERO) .addMBB(sinkMBB); } @@ -4014,7 +3880,7 @@ BB = sinkMBB; BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg()) - .addReg(MI.getOperand(2).getReg()) + .addReg(MI.getOperand(1).getReg()) .addMBB(thisMBB) .addReg(MI.getOperand(3).getReg()) .addMBB(copy0MBB); Index: lib/Target/Mips/MipsInstrFPU.td =================================================================== --- lib/Target/Mips/MipsInstrFPU.td +++ lib/Target/Mips/MipsInstrFPU.td @@ -23,12 +23,6 @@ // - 32 32-bit registers (within single-only mode) //===----------------------------------------------------------------------===// -// Floating Point Compare and Branch -def SDT_MipsFPBrcond : SDTypeProfile<0, 3, [SDTCisInt<0>, - SDTCisVT<1, i32>, - SDTCisVT<2, OtherVT>]>; -def SDT_MipsFPCmp : SDTypeProfile<0, 3, [SDTCisSameAs<0, 1>, SDTCisFP<1>, - SDTCisVT<2, i32>]>; def SDT_MipsCMovFP : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisVT<2, i32>, SDTCisSameAs<1, 3>]>; def SDT_MipsTruncIntFP : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisFP<1>]>; @@ -39,19 +33,15 @@ SDTCisVT<1, f64>, SDTCisVT<2, i32>]>; -def MipsFPCmp : SDNode<"MipsISD::FPCmp", SDT_MipsFPCmp, [SDNPOutGlue]>; def MipsCMovFP_T : SDNode<"MipsISD::CMovFP_T", SDT_MipsCMovFP, [SDNPInGlue]>; def MipsCMovFP_F : SDNode<"MipsISD::CMovFP_F", SDT_MipsCMovFP, [SDNPInGlue]>; -def MipsFPBrcond : SDNode<"MipsISD::FPBrcond", SDT_MipsFPBrcond, - [SDNPHasChain, SDNPOptInGlue]>; def MipsTruncIntFP : SDNode<"MipsISD::TruncIntFP", SDT_MipsTruncIntFP>; def MipsBuildPairF64 : SDNode<"MipsISD::BuildPairF64", SDT_MipsBuildPairF64>; def MipsExtractElementF64 : SDNode<"MipsISD::ExtractElementF64", SDT_MipsExtractElementF64>; // Operand for printing out a condition code. -let PrintMethod = "printFCCOperand", DecoderMethod = "DecodeCondCode" in - def condcode : Operand; +def invertbit : Operand; //===----------------------------------------------------------------------===// // Feature predicates. @@ -212,30 +202,22 @@ class BC1F_FT : InstSE<(outs), (ins FCCRegsOpnd:$fcc, opnd:$offset), - !strconcat(opstr, "\t$fcc, $offset"), - [(MipsFPBrcond Op, FCCRegsOpnd:$fcc, bb:$offset)], Itin, - FrmFI, opstr>, HARDFLOAT { + !strconcat(opstr, "\t$fcc, $offset"), [], Itin, FrmFI, opstr>, + HARDFLOAT { let isBranch = 1; let isTerminator = 1; let hasDelaySlot = DelaySlot; let Defs = [AT]; } -class CEQS_FT : - InstSE<(outs), (ins RC:$fs, RC:$ft, condcode:$cond), - !strconcat("c.$cond.", typestr, "\t$fs, $ft"), - [(OpNode RC:$fs, RC:$ft, imm:$cond)], Itin, FrmFR, - !strconcat("c.$cond.", typestr)>, HARDFLOAT { - let Defs = [FCC0]; - let isCodeGenOnly = 1; -} - class C_COND_FT : - InstSE<(outs), (ins RC:$fs, RC:$ft), - !strconcat("c.", CondStr, ".", Typestr, "\t$fs, $ft"), [], itin, - FrmFR>, HARDFLOAT; + InstrItinClass itin> : + InstSE<(outs FCCRegsOpnd:$fcc), (ins RC:$fs, RC:$ft), + !strconcat("c.", CondStr, ".", Typestr, "\t$fcc, $fs, $ft"), + [(set FCCRegsOpnd:$fcc, (null_frag RC:$fs, RC:$ft))], itin, + FrmFR>, HARDFLOAT { + let BaseOpcode = !strconcat("c.", CondStr, ".", Typestr); +} multiclass C_COND_M fmt, InstrItinClass itin> { @@ -258,11 +240,11 @@ } defm S : C_COND_M<"s", FGR32Opnd, 16, II_C_CC_S>, ISA_MIPS1_NOT_32R6_64R6; -defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, - FGR_32; +defm D32 : C_COND_M<"d", AFGR64Opnd, 17, II_C_CC_D>, + ISA_MIPS1_NOT_32R6_64R6, FGR_32; let DecoderNamespace = "Mips64" in -defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, ISA_MIPS1_NOT_32R6_64R6, - FGR_64; +defm D64 : C_COND_M<"d", FGR64Opnd, 17, II_C_CC_D>, + ISA_MIPS1_NOT_32R6_64R6, FGR_64; //===----------------------------------------------------------------------===// // Floating Point Instructions @@ -534,16 +516,60 @@ def BC1TL : MMRel, BC1F_FT<"bc1tl", brtarget, II_BC1TL, MIPS_BRANCH_T, 0>, BC1F_FM<1, 1>, ISA_MIPS2_NOT_32R6_64R6; -/// Floating Point Compare +// Compare and branch patterns +multiclass FPBrcondPats { + // Ordered + def : MipsPat<(brcond (i32 (setoeq RC:$lhs, RC:$rhs)), bb:$dst), + (BC1T (!cast("C_EQ_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>; + def : MipsPat<(brcond (i32 (setogt RC:$lhs, RC:$rhs)), bb:$dst), + (BC1F (!cast("C_OLE_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>; + def : MipsPat<(brcond (i32 (setoge RC:$lhs, RC:$rhs)), bb:$dst), + (BC1F (!cast("C_LT_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>; + def : MipsPat<(brcond (i32 (setolt RC:$lhs, RC:$rhs)), bb:$dst), + (BC1T (!cast("C_LT_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>; + def : MipsPat<(brcond (i32 (setole RC:$lhs, RC:$rhs)), bb:$dst), + (BC1T (!cast("C_OLE_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>; + def : MipsPat<(brcond (i32 (setone RC:$lhs, RC:$rhs)), bb:$dst), + (BC1F (!cast("C_EQ_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>; + def : MipsPat<(brcond (i32 (seto RC:$lhs, RC:$rhs)), bb:$dst), + (BC1F (!cast("C_UN_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>; + // Unordered + def : MipsPat<(brcond (i32 (setuo RC:$lhs, RC:$rhs)), bb:$dst), + (BC1T (!cast("C_UN_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>; + def : MipsPat<(brcond (i32 (setueq RC:$lhs, RC:$rhs)), bb:$dst), + (BC1T (!cast("C_UEQ_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>; + def : MipsPat<(brcond (i32 (setugt RC:$lhs, RC:$rhs)), bb:$dst), + (BC1F (!cast("C_OLE_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>; + def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst), + (BC1F (!cast("C_OLT_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>; + def : MipsPat<(brcond (i32 (setult RC:$lhs, RC:$rhs)), bb:$dst), + (BC1T (!cast("C_ULT_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>; + def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst), + (BC1T (!cast("C_ULE_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>; + def : MipsPat<(brcond (i32 (setune RC:$lhs, RC:$rhs)), bb:$dst), + (BC1F (!cast("C_EQ_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>; + def : MipsPat<(brcond (i32 (setuo RC:$lhs, RC:$rhs)), bb:$dst), + (BC1T (!cast("C_EQ_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>; + // Unspecified ordering - treated as ordered. + def : MipsPat<(brcond (i32 (seteq RC:$lhs, RC:$rhs)), bb:$dst), + (BC1T (!cast("C_EQ_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>; + def : MipsPat<(brcond (i32 (setgt RC:$lhs, RC:$rhs)), bb:$dst), + (BC1F (!cast("C_OLE_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>; + def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst), + (BC1F (!cast("C_LT_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>; + def : MipsPat<(brcond (i32 (setlt RC:$lhs, RC:$rhs)), bb:$dst), + (BC1T (!cast("C_LT_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>; + def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst), + (BC1T (!cast("C_OLE_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>; + def : MipsPat<(brcond (i32 (setne RC:$lhs, RC:$rhs)), bb:$dst), + (BC1F (!cast("C_EQ_"#NAME) RC:$lhs, RC:$rhs), bb:$dst)>; +} + let AdditionalPredicates = [NotInMicroMips] in { - def FCMP_S32 : MMRel, CEQS_FT<"s", FGR32, II_C_CC_S, MipsFPCmp>, CEQS_FM<16>, - ISA_MIPS1_NOT_32R6_64R6; - def FCMP_D32 : MMRel, CEQS_FT<"d", AFGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, - ISA_MIPS1_NOT_32R6_64R6, FGR_32; + defm S : FPBrcondPats, ISA_MIPS1_NOT_32R6_64R6; + defm D32 : FPBrcondPats, FGR_32, ISA_MIPS1_NOT_32R6_64R6; + defm D64 : FPBrcondPats, FGR_64, ISA_MIPS1_NOT_32R6_64R6; } -let DecoderNamespace = "Mips64" in -def FCMP_D64 : CEQS_FT<"d", FGR64, II_C_CC_D, MipsFPCmp>, CEQS_FM<17>, - ISA_MIPS1_NOT_32R6_64R6, FGR_64; //===----------------------------------------------------------------------===// // Floating Point Pseudo-Instructions @@ -587,6 +613,78 @@ "trunc.w.d\t$fd, $fs, $rs">, FGR_64, HARDFLOAT; +// Pseudo instructions to read $fcc0 - $fcc7 +def PseudoReadFCC : + PseudoSE<(outs GPR32Opnd:$rd), (ins invertbit:$invert, FCC:$fcc), + [], II_CFC1>; + +multiclass Mips3ReadFCC { + def : MipsPat<(seteq RC:$lhs, RC:$rhs), + (PseudoReadFCC 0, + (!cast("C_EQ_"#NAME) RC:$lhs, RC:$rhs))>; + def : MipsPat<(setgt RC:$lhs, RC:$rhs), + (PseudoReadFCC 1, + (!cast("C_ULE_"#NAME) RC:$lhs, RC:$rhs))>; + def : MipsPat<(setge RC:$lhs, RC:$rhs), + (PseudoReadFCC 1, + (!cast("C_ULT_"#NAME) RC:$lhs, RC:$rhs))>; + def : MipsPat<(setlt RC:$lhs, RC:$rhs), + (PseudoReadFCC 0, + (!cast("C_OLT_"#NAME) RC:$lhs, RC:$rhs))>; + def : MipsPat<(setle RC:$lhs, RC:$rhs), + (PseudoReadFCC 0, + (!cast("C_OLE_"#NAME) RC:$lhs, RC:$rhs))>; + def : MipsPat<(setne RC:$lhs, RC:$rhs), + (PseudoReadFCC 1, + (!cast("C_UEQ_"#NAME) RC:$lhs, RC:$rhs))>; + def : MipsPat<(setoeq RC:$lhs, RC:$rhs), + (PseudoReadFCC 0, + (!cast("C_EQ_"#NAME) RC:$lhs, RC:$rhs))>; + def : MipsPat<(setogt RC:$lhs, RC:$rhs), + (PseudoReadFCC 1, + (!cast("C_ULE_"#NAME) RC:$lhs, RC:$rhs))>; + def : MipsPat<(setoge RC:$lhs, RC:$rhs), + (PseudoReadFCC 1, + (!cast("C_ULT_"#NAME) RC:$lhs, RC:$rhs))>; + def : MipsPat<(setolt RC:$lhs, RC:$rhs), + (PseudoReadFCC 0, + (!cast("C_OLT_"#NAME) RC:$lhs, RC:$rhs))>; + def : MipsPat<(setole RC:$lhs, RC:$rhs), + (PseudoReadFCC 0, + (!cast("C_OLE_"#NAME) RC:$lhs, RC:$rhs))>; + def : MipsPat<(setone RC:$lhs, RC:$rhs), + (PseudoReadFCC 1, + (!cast("C_UEQ_"#NAME) RC:$lhs, RC:$rhs))>; + def : MipsPat<(seto RC:$lhs, RC:$rhs), + (PseudoReadFCC 1, + (!cast("C_UN_"#NAME) RC:$lhs, RC:$rhs))>; + def : MipsPat<(setuo RC:$lhs, RC:$rhs), + (PseudoReadFCC 0, + (!cast("C_UN_"#NAME) RC:$lhs, RC:$rhs))>; + def : MipsPat<(setueq RC:$lhs, RC:$rhs), + (PseudoReadFCC 0, + (!cast("C_UEQ_"#NAME) RC:$lhs, RC:$rhs))>; + def : MipsPat<(setugt RC:$lhs, RC:$rhs), + (PseudoReadFCC 1, + (!cast("C_OLE_"#NAME) RC:$lhs, RC:$rhs))>; + def : MipsPat<(setuge RC:$lhs, RC:$rhs), + (PseudoReadFCC 1, + (!cast("C_OLT_"#NAME) RC:$lhs, RC:$rhs))>; + def : MipsPat<(setult RC:$lhs, RC:$rhs), + (PseudoReadFCC 0, + (!cast("C_ULT_"#NAME) RC:$lhs, RC:$rhs))>; + def : MipsPat<(setule RC:$lhs, RC:$rhs), + (PseudoReadFCC 0, + (!cast("C_ULE_"#NAME) RC:$lhs, RC:$rhs))>; + def : MipsPat<(setune RC:$lhs, RC:$rhs), + (PseudoReadFCC 1, + (!cast("C_EQ_"#NAME) RC:$lhs, RC:$rhs))>; +} + +defm S : Mips3ReadFCC, ISA_MIPS1_NOT_4_32; +defm D32 : Mips3ReadFCC, FGR_32, ISA_MIPS1_NOT_4_32; +defm D64 : Mips3ReadFCC, FGR_64, ISA_MIPS1_NOT_4_32; + //===----------------------------------------------------------------------===// // InstAliases. //===----------------------------------------------------------------------===// @@ -599,6 +697,47 @@ def : MipsInstAlias<"bc1fl $offset", (BC1FL FCC0, brtarget:$offset)>, ISA_MIPS2_NOT_32R6_64R6, HARDFLOAT; +multiclass FPCAliases { + def : MipsInstAlias("C_F_"#NAME) FCC0, RC:$rs, RC:$rt), 1>; + def : MipsInstAlias("C_UN_"#NAME) FCC0, RC:$rs, RC:$rt), 1>; + def : MipsInstAlias("C_EQ_"#NAME) FCC0, RC:$rs, RC:$rt), 1>; + def : MipsInstAlias("C_UEQ_"#NAME) FCC0, RC:$rs, RC:$rt), 1>; + def : MipsInstAlias("C_OLT_"#NAME) FCC0, RC:$rs, RC:$rt), 1>; + def : MipsInstAlias("C_ULT_"#NAME) FCC0, RC:$rs, RC:$rt), 1>; + def : MipsInstAlias("C_OLE_"#NAME) FCC0, RC:$rs, RC:$rt), 1>; + def : MipsInstAlias("C_ULE_"#NAME) FCC0, RC:$rs, RC:$rt), 1>; + def : MipsInstAlias("C_SF_"#NAME) FCC0, RC:$rs, RC:$rt), 1>; + def : MipsInstAlias("C_NGLE_"#NAME) FCC0, RC:$rs, RC:$rt), 1>; + def : MipsInstAlias("C_SEQ_"#NAME) FCC0, RC:$rs, RC:$rt), 1>; + def : MipsInstAlias("C_NGL_"#NAME) FCC0, RC:$rs, RC:$rt), 1>; + def : MipsInstAlias("C_LT_"#NAME) FCC0, RC:$rs, RC:$rt), 1>; + def : MipsInstAlias("C_NGE_"#NAME) FCC0, RC:$rs, RC:$rt), 1>; + def : MipsInstAlias("C_LE_"#NAME) FCC0, RC:$rs, RC:$rt), 1>; + def : MipsInstAlias("C_NGT_"#NAME) FCC0, RC:$rs, RC:$rt), 1>; +} + +let AdditionalPredicates = [NotInMicroMips] in { + defm S : FPCAliases, HARDFLOAT, ISA_MIPS1_NOT_32R6_64R6; + defm D32 : FPCAliases, HARDFLOAT, ISA_MIPS1_NOT_32R6_64R6; + defm D64 : FPCAliases, HARDFLOAT, ISA_MIPS1_NOT_32R6_64R6; +} + //===----------------------------------------------------------------------===// // Floating Point Patterns //===----------------------------------------------------------------------===// Index: lib/Target/Mips/MipsInstrFormats.td =================================================================== --- lib/Target/Mips/MipsInstrFormats.td +++ lib/Target/Mips/MipsInstrFormats.td @@ -825,6 +825,7 @@ class CEQS_FM fmt> : StdArch { bits<5> fs; bits<5> ft; + bits<3> fcc; bits<4> cond; bits<32> Inst; @@ -833,7 +834,7 @@ let Inst{25-21} = fmt; let Inst{20-16} = ft; let Inst{15-11} = fs; - let Inst{10-8} = 0; // cc + let Inst{10-8} = fcc; let Inst{7-4} = 0x3; let Inst{3-0} = cond; } Index: lib/Target/Mips/MipsRegisterInfo.td =================================================================== --- lib/Target/Mips/MipsRegisterInfo.td +++ lib/Target/Mips/MipsRegisterInfo.td @@ -393,8 +393,7 @@ Unallocatable; // FP condition code registers. -def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>, - Unallocatable; +def FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>; // MIPS32r6/MIPS64r6 store FPU condition codes in normal FGR registers. // This class allows us to represent this in codegen patterns. Index: lib/Target/Mips/MipsSEInstrInfo.h =================================================================== --- lib/Target/Mips/MipsSEInstrInfo.h +++ lib/Target/Mips/MipsSEInstrInfo.h @@ -106,6 +106,15 @@ void expandCvtFPInt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, unsigned CvtOpc, unsigned MovOpc, bool IsI64) const; + /// Expand pseudo ReadFCC(I) instructions like so: + /// + /// cfc1 $dst, $fcr25 + /// srl $dst, $dst, (register number if not $fcc0) + /// nor $dst, $dst, $dst (if inverted) + /// andi $dst, $dst, 1 + /// + void expandReadFCC(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const; void expandExtractElementF64(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, bool FP64) const; void expandBuildPairF64(MachineBasicBlock &MBB, Index: lib/Target/Mips/MipsSEInstrInfo.cpp =================================================================== --- lib/Target/Mips/MipsSEInstrInfo.cpp +++ lib/Target/Mips/MipsSEInstrInfo.cpp @@ -377,6 +377,9 @@ case Mips::PseudoCVT_D64_W: expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true); break; + case Mips::PseudoReadFCC: + expandReadFCC(MBB, MI); + break; case Mips::PseudoCVT_D64_L: expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true); break; @@ -624,6 +627,37 @@ BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill); } +void MipsSEInstrInfo::expandReadFCC(MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const { + assert(I->getOperand(1).isImm() && "Malformed PseudoReadFCC Node"); + + bool Invert = (I->getOperand(1).getImm()) == 1; + const MachineOperand &Dest = I->getOperand(0), &Src = I->getOperand(2); + unsigned DstReg = Dest.getReg(), SrcReg = Src.getReg(); + + DebugLoc DL = I->getDebugLoc(); + BuildMI(MBB, I, DL, get(Mips::CFC1), DstReg).addReg(Mips::FCR31); + unsigned Shift = 0; + switch (SrcReg) { + case Mips::FCC0: Shift = 23; break; + case Mips::FCC1: Shift = 25; break; + case Mips::FCC2: Shift = 26; break; + case Mips::FCC3: Shift = 27; break; + case Mips::FCC4: Shift = 28; break; + case Mips::FCC5: Shift = 29; break; + case Mips::FCC6: Shift = 30; break; + case Mips::FCC7: Shift = 31; break; + default: + llvm_unreachable("Unknown $fcc register for expandReadFCC!"); + } + BuildMI(MBB, I, DL, get(Mips::SRL), DstReg).addReg(DstReg).addImm(Shift); + + if (Invert) + BuildMI(MBB, I, DL, get(Mips::NOR), DstReg).addReg(DstReg).addReg(DstReg); + + BuildMI(MBB, I, DL, get(Mips::ANDi), DstReg).addReg(DstReg).addImm(1); +} + void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, bool FP64) const { Index: test/CodeGen/Mips/fcmp.ll =================================================================== --- test/CodeGen/Mips/fcmp.ll +++ test/CodeGen/Mips/fcmp.ll @@ -55,10 +55,9 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.eq.s $f12, $f14 -; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movf $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14 ; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13 @@ -89,10 +88,9 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.ule.s $f12, $f14 -; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movt $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12 ; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12 @@ -123,10 +121,9 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.ult.s $f12, $f14 -; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movt $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f14, $f12 ; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f13, $f12 @@ -157,10 +154,9 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.olt.s $f12, $f14 -; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movf $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14 ; MM64R6-DAG: cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13 @@ -191,10 +187,9 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.ole.s $f12, $f14 -; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movf $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f14 ; MM64R6-DAG: cmp.le.s $[[T0:f[0-9]+]], $f12, $f13 @@ -227,10 +222,9 @@ ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: andi $2, $[[T2]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.ueq.s $f12, $f14 -; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movt $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14 ; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13 @@ -264,10 +258,9 @@ ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: andi $2, $[[T2]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.un.s $f12, $f14 -; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movt $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14 ; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13 @@ -299,10 +292,9 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.ueq.s $f12, $f14 -; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movf $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14 ; MM64R6-DAG: cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13 @@ -333,10 +325,9 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.ole.s $f12, $f14 -; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movt $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12 ; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12 @@ -367,10 +358,9 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.olt.s $f12, $f14 -; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movt $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12 ; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12 @@ -401,10 +391,9 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.ult.s $f12, $f14 -; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movf $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14 ; MM64R6-DAG: cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13 @@ -435,10 +424,9 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.ule.s $f12, $f14 -; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movf $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14 ; MM64R6-DAG: cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13 @@ -471,10 +459,9 @@ ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: andi $2, $[[T2]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.eq.s $f12, $f14 -; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movt $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14 ; MM64R6-DAG: cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13 @@ -506,10 +493,9 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.un.s $f12, $f14 -; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movf $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f14 ; MM64R6-DAG: cmp.un.s $[[T0:f[0-9]+]], $f12, $f13 @@ -574,10 +560,9 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.eq.d $f12, $f14 -; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movf $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14 ; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13 @@ -608,10 +593,9 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.ule.d $f12, $f14 -; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movt $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12 ; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12 @@ -642,10 +626,9 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.ult.d $f12, $f14 -; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movt $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f14, $f12 ; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f13, $f12 @@ -676,10 +659,9 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.olt.d $f12, $f14 -; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movf $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14 ; MM64R6-DAG: cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13 @@ -710,10 +692,9 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.ole.d $f12, $f14 -; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movf $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f14 ; MM64R6-DAG: cmp.le.d $[[T0:f[0-9]+]], $f12, $f13 @@ -746,10 +727,9 @@ ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: andi $2, $[[T2]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.ueq.d $f12, $f14 -; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movt $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14 ; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13 @@ -783,10 +763,9 @@ ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: andi $2, $[[T2]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.un.d $f12, $f14 -; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movt $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14 ; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13 @@ -818,10 +797,9 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.ueq.d $f12, $f14 -; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movf $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14 ; MM64R6-DAG: cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13 @@ -852,10 +830,9 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.ole.d $f12, $f14 -; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movt $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12 ; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12 @@ -886,10 +863,9 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.olt.d $f12, $f14 -; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movt $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12 ; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12 @@ -920,10 +896,9 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.ult.d $f12, $f14 -; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movf $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14 ; MM64R6-DAG: cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13 @@ -954,10 +929,9 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.ule.d $f12, $f14 -; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movf $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14 ; MM64R6-DAG: cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13 @@ -990,10 +964,9 @@ ; 64-CMP-DAG: not $[[T2:[0-9]+]], $[[T1]] ; 64-CMP-DAG: andi $2, $[[T2]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.eq.d $f12, $f14 -; MM32R3-DAG: movt $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movt $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14 ; MM64R6-DAG: cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13 @@ -1025,10 +998,9 @@ ; 64-CMP-DAG: mfc1 $[[T1:[0-9]+]], $[[T0]] ; 64-CMP-DAG: andi $2, $[[T1]], 1 -; MM32R3-DAG: li16 $[[T0:[0-9]+]], 0 -; MM32R3-DAG: li16 $[[T1:[0-9]+]], 1 +; MM32R3-DAG: li16 $[[T0:[0-9]+]], 1 ; MM32R3-DAG: c.un.d $f12, $f14 -; MM32R3-DAG: movf $[[T1]], $[[T0]], $fcc0 +; MM32R3-DAG: movf $[[T0]], $zero, $fcc0 ; MM32R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f14 ; MM64R6-DAG: cmp.un.d $[[T0:f[0-9]+]], $f12, $f13 Index: test/CodeGen/Mips/selectcc.ll =================================================================== --- test/CodeGen/Mips/selectcc.ll +++ test/CodeGen/Mips/selectcc.ll @@ -18,10 +18,10 @@ ; SOURCE-SCHED: lw ; SOURCE-SCHED: lui ; SOURCE-SCHED: sw +; SOURCE-SCHED: c.olt.s ; SOURCE-SCHED: lw ; SOURCE-SCHED: lwc1 ; SOURCE-SCHED: mtc1 -; SOURCE-SCHED: c.olt.s ; SOURCE-SCHED: jr store float 0.000000e+00, float* @gf0, align 4 store float 1.000000e+00, float* @gf1, align 4 Index: test/MC/Mips/mips32/valid-xfail.s =================================================================== --- test/MC/Mips/mips32/valid-xfail.s +++ test/MC/Mips/mips32/valid-xfail.s @@ -7,32 +7,20 @@ # XFAIL: * .set noat - c.eq.d $fcc1,$f15,$f15 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 - c.nge.s $fcc3,$f11,$f8 - c.ngl.s $fcc2,$f31,$f23 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 - c.seq.s $fcc7,$f1,$f25 - c.ueq.d $fcc4,$f13,$f25 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 - c.un.s $fcc1,$f30,$f4 + c.eq.ps $fcc5,$f0,$f9 + c.f.ps $fcc6,$f11,$f11 + c.le.ps $fcc1,$f7,$f20 + c.lt.ps $f19,$f5 + c.nge.ps $f1,$f26 + c.ngl.ps $f21,$f30 + c.ngle.ps $fcc7,$f12,$f20 + c.ngt.ps $fcc5,$f30,$f6 + c.ole.ps $fcc7,$f21,$f8 + c.olt.ps $fcc3,$f7,$f16 + c.seq.ps $fcc6,$f31,$f14 + c.sf.ps $fcc6,$f4,$f6 + c.ueq.ps $fcc1,$f5,$f29 + c.ule.ps $fcc6,$f17,$f3 + c.ult.ps $fcc7,$f14,$f0 + c.un.ps $fcc4,$f2,$f26 rorv $13,$a3,$s5 Index: test/MC/Mips/mips32/valid.s =================================================================== --- test/MC/Mips/mips32/valid.s +++ test/MC/Mips/mips32/valid.s @@ -41,10 +41,38 @@ bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 + c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32] + c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32] + c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30] + c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30] + c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e] + c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e] + c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c] + c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c] + c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d] + c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d] + c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b] + c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39] + c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b] + c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39] + c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f] + c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f] + c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36] + c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36] + c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34] + c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34] + c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a] + c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a] + c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38] + c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38] + c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33] + c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33] + c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37] + c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37] + c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35] + c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35] + c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] + c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] ceil.w.d $f11,$f25 ceil.w.s $f6,$f20 cfc1 $s1,$21 Index: test/MC/Mips/mips32r2/valid-xfail.s =================================================================== --- test/MC/Mips/mips32r2/valid-xfail.s +++ test/MC/Mips/mips32r2/valid-xfail.s @@ -12,50 +12,22 @@ addqh.w $s7,$s7,$k1 addqh_r.w $8,$v1,$zero alnv.ps $f12,$f18,$f30,$12 - c.eq.d $fcc1,$f15,$f15 c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 ceil.l.d $f1,$f3 ceil.l.s $f18,$f13 cfcmsa $s6,$19 Index: test/MC/Mips/mips32r2/valid.s =================================================================== --- test/MC/Mips/mips32r2/valid.s +++ test/MC/Mips/mips32r2/valid.s @@ -41,10 +41,38 @@ bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 + c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32] + c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32] + c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30] + c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30] + c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e] + c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e] + c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c] + c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c] + c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d] + c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d] + c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b] + c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39] + c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b] + c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39] + c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f] + c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f] + c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36] + c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36] + c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34] + c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34] + c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a] + c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a] + c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38] + c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38] + c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33] + c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33] + c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37] + c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37] + c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35] + c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35] + c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] + c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] ceil.w.d $f11,$f25 ceil.w.s $f6,$f20 cfc1 $s1,$21 Index: test/MC/Mips/mips32r3/valid-xfail.s =================================================================== --- test/MC/Mips/mips32r3/valid-xfail.s +++ test/MC/Mips/mips32r3/valid-xfail.s @@ -12,50 +12,22 @@ addqh.w $s7,$s7,$k1 addqh_r.w $8,$v1,$zero alnv.ps $f12,$f18,$f30,$12 - c.eq.d $fcc1,$f15,$f15 c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 ceil.l.d $f1,$f3 ceil.l.s $f18,$f13 cfcmsa $s6,$19 Index: test/MC/Mips/mips32r3/valid.s =================================================================== --- test/MC/Mips/mips32r3/valid.s +++ test/MC/Mips/mips32r3/valid.s @@ -41,10 +41,38 @@ bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 + c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32] + c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32] + c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30] + c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30] + c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e] + c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e] + c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c] + c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c] + c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d] + c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d] + c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b] + c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39] + c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b] + c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39] + c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f] + c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f] + c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36] + c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36] + c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34] + c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34] + c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a] + c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a] + c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38] + c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38] + c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33] + c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33] + c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37] + c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37] + c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35] + c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35] + c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] + c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] ceil.w.d $f11,$f25 ceil.w.s $f6,$f20 cfc1 $s1,$21 Index: test/MC/Mips/mips32r5/valid-xfail.s =================================================================== --- test/MC/Mips/mips32r5/valid-xfail.s +++ test/MC/Mips/mips32r5/valid-xfail.s @@ -12,50 +12,22 @@ addqh.w $s7,$s7,$k1 addqh_r.w $8,$v1,$zero alnv.ps $f12,$f18,$f30,$12 - c.eq.d $fcc1,$f15,$f15 c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 ceil.l.d $f1,$f3 ceil.l.s $f18,$f13 cfcmsa $s6,$19 Index: test/MC/Mips/mips32r5/valid.s =================================================================== --- test/MC/Mips/mips32r5/valid.s +++ test/MC/Mips/mips32r5/valid.s @@ -41,10 +41,38 @@ bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 + c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32] + c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32] + c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30] + c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30] + c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e] + c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e] + c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c] + c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c] + c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d] + c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d] + c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b] + c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39] + c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b] + c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39] + c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f] + c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f] + c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36] + c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36] + c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34] + c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34] + c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a] + c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a] + c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38] + c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38] + c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33] + c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33] + c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37] + c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37] + c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35] + c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35] + c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] + c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] ceil.w.d $f11,$f25 ceil.w.s $f6,$f20 cfc1 $s1,$21 Index: test/MC/Mips/mips4/valid-xfail.s =================================================================== --- test/MC/Mips/mips4/valid-xfail.s +++ test/MC/Mips/mips4/valid-xfail.s @@ -7,34 +7,22 @@ # XFAIL: * .set noat - c.eq.d $fcc1,$f15,$f15 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 - c.nge.s $fcc3,$f11,$f8 - c.ngl.s $fcc2,$f31,$f23 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 - c.seq.s $fcc7,$f1,$f25 - c.ueq.d $fcc4,$f13,$f25 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 - c.un.s $fcc1,$f30,$f4 + c.eq.ps $fcc5,$f0,$f9 + c.f.ps $fcc6,$f11,$f11 + c.le.ps $fcc1,$f7,$f20 + c.lt.ps $f19,$f5 + c.nge.ps $f1,$f26 + c.ngl.ps $f21,$f30 + c.ngle.ps $fcc7,$f12,$f20 + c.ngt.ps $fcc5,$f30,$f6 + c.ole.ps $fcc7,$f21,$f8 + c.olt.ps $fcc3,$f7,$f16 + c.seq.ps $fcc6,$f31,$f14 + c.sf.ps $fcc6,$f4,$f6 + c.ueq.ps $fcc1,$f5,$f29 + c.ule.ps $fcc6,$f17,$f3 + c.ult.ps $fcc7,$f14,$f0 + c.un.ps $fcc4,$f2,$f26 recip.d $f19,$f6 recip.s $f3,$f30 rsqrt.d $f3,$f28 Index: test/MC/Mips/mips4/valid.s =================================================================== --- test/MC/Mips/mips4/valid.s +++ test/MC/Mips/mips4/valid.s @@ -41,10 +41,38 @@ bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 + c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32] + c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32] + c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30] + c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30] + c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e] + c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e] + c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c] + c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c] + c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d] + c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d] + c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b] + c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39] + c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b] + c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39] + c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f] + c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f] + c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36] + c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36] + c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34] + c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34] + c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a] + c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a] + c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38] + c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38] + c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33] + c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33] + c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37] + c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37] + c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35] + c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35] + c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] + c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] ceil.l.d $f1,$f3 ceil.l.s $f18,$f13 ceil.w.d $f11,$f25 Index: test/MC/Mips/mips5/valid-xfail.s =================================================================== --- test/MC/Mips/mips5/valid-xfail.s +++ test/MC/Mips/mips5/valid-xfail.s @@ -10,50 +10,22 @@ abs.ps $f22,$f8 add.ps $f25,$f27,$f13 alnv.ps $f12,$f18,$f30,$12 - c.eq.d $fcc1,$f15,$f15 c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 cvt.ps.s $f3,$f18,$f19 cvt.s.pl $f30,$f1 cvt.s.pu $f14,$f25 Index: test/MC/Mips/mips5/valid.s =================================================================== --- test/MC/Mips/mips5/valid.s +++ test/MC/Mips/mips5/valid.s @@ -41,10 +41,38 @@ bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 + c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32] + c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32] + c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30] + c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30] + c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e] + c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e] + c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c] + c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c] + c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d] + c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d] + c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b] + c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39] + c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b] + c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39] + c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f] + c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f] + c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36] + c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36] + c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34] + c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34] + c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a] + c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a] + c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38] + c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38] + c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33] + c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33] + c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37] + c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37] + c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35] + c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35] + c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] + c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] ceil.l.d $f1,$f3 ceil.l.s $f18,$f13 ceil.w.d $f11,$f25 Index: test/MC/Mips/mips64/valid-xfail.s =================================================================== --- test/MC/Mips/mips64/valid-xfail.s +++ test/MC/Mips/mips64/valid-xfail.s @@ -13,50 +13,22 @@ alnv.ob $v31,$v23,$v30,$at alnv.ob $v8,$v17,$v30,$a1 alnv.ps $f12,$f18,$f30,$12 - c.eq.d $fcc1,$f15,$f15 c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 cvt.ps.s $f3,$f18,$f19 cvt.s.pl $f30,$f1 cvt.s.pu $f14,$f25 Index: test/MC/Mips/mips64/valid.s =================================================================== --- test/MC/Mips/mips64/valid.s +++ test/MC/Mips/mips64/valid.s @@ -41,10 +41,38 @@ bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 + c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32] + c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32] + c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30] + c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30] + c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e] + c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e] + c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c] + c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c] + c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d] + c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d] + c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b] + c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39] + c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b] + c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39] + c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f] + c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f] + c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36] + c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36] + c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34] + c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34] + c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a] + c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a] + c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38] + c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38] + c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33] + c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33] + c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37] + c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37] + c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35] + c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35] + c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] + c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] ceil.l.d $f1,$f3 ceil.l.s $f18,$f13 ceil.w.d $f11,$f25 Index: test/MC/Mips/mips64r2/valid-xfail.s =================================================================== --- test/MC/Mips/mips64r2/valid-xfail.s +++ test/MC/Mips/mips64r2/valid-xfail.s @@ -12,50 +12,22 @@ addqh.w $s7,$s7,$k1 addqh_r.w $8,$v1,$zero alnv.ps $f12,$f18,$f30,$12 - c.eq.d $fcc1,$f15,$f15 c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 cvt.ps.s $f3,$f18,$f19 cvt.s.pl $f30,$f1 cvt.s.pu $f14,$f25 Index: test/MC/Mips/mips64r2/valid.s =================================================================== --- test/MC/Mips/mips64r2/valid.s +++ test/MC/Mips/mips64r2/valid.s @@ -41,10 +41,38 @@ bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 + c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32] + c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32] + c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30] + c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30] + c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e] + c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e] + c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c] + c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c] + c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d] + c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d] + c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b] + c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39] + c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b] + c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39] + c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f] + c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f] + c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36] + c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36] + c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34] + c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34] + c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a] + c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a] + c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38] + c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38] + c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33] + c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33] + c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37] + c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37] + c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35] + c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35] + c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] + c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] ceil.l.d $f1,$f3 ceil.l.s $f18,$f13 ceil.w.d $f11,$f25 Index: test/MC/Mips/mips64r3/valid-xfail.s =================================================================== --- test/MC/Mips/mips64r3/valid-xfail.s +++ test/MC/Mips/mips64r3/valid-xfail.s @@ -15,50 +15,22 @@ alnv.ob $v31,$v23,$v30,$at alnv.ob $v8,$v17,$v30,$a1 alnv.ps $f12,$f18,$f30,$12 - c.eq.d $fcc1,$f15,$f15 c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 cvt.ps.s $f3,$f18,$f19 cvt.s.pl $f30,$f1 cvt.s.pu $f14,$f25 Index: test/MC/Mips/mips64r3/valid.s =================================================================== --- test/MC/Mips/mips64r3/valid.s +++ test/MC/Mips/mips64r3/valid.s @@ -41,10 +41,38 @@ bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 + c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32] + c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32] + c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30] + c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30] + c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e] + c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e] + c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c] + c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c] + c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d] + c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d] + c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b] + c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39] + c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b] + c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39] + c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f] + c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f] + c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36] + c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36] + c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34] + c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34] + c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a] + c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a] + c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38] + c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38] + c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33] + c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33] + c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37] + c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37] + c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35] + c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35] + c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] + c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] ceil.l.d $f1,$f3 ceil.l.s $f18,$f13 ceil.w.d $f11,$f25 Index: test/MC/Mips/mips64r5/valid-xfail.s =================================================================== --- test/MC/Mips/mips64r5/valid-xfail.s +++ test/MC/Mips/mips64r5/valid-xfail.s @@ -15,50 +15,22 @@ alnv.ob $v31,$v23,$v30,$at alnv.ob $v8,$v17,$v30,$a1 alnv.ps $f12,$f18,$f30,$12 - c.eq.d $fcc1,$f15,$f15 c.eq.ps $fcc5,$f0,$f9 - c.eq.s $fcc5,$f24,$f17 - c.f.d $fcc4,$f11,$f21 c.f.ps $fcc6,$f11,$f11 - c.f.s $fcc4,$f30,$f7 - c.le.d $fcc4,$f18,$f1 c.le.ps $fcc1,$f7,$f20 - c.le.s $fcc6,$f24,$f4 - c.lt.d $fcc3,$f9,$f3 c.lt.ps $f19,$f5 - c.lt.s $fcc2,$f17,$f14 - c.nge.d $fcc5,$f21,$f16 c.nge.ps $f1,$f26 - c.nge.s $fcc3,$f11,$f8 c.ngl.ps $f21,$f30 - c.ngl.s $fcc2,$f31,$f23 c.ngle.ps $fcc7,$f12,$f20 - c.ngle.s $fcc2,$f18,$f23 - c.ngt.d $fcc4,$f24,$f7 c.ngt.ps $fcc5,$f30,$f6 - c.ngt.s $fcc5,$f8,$f13 - c.ole.d $fcc2,$f16,$f31 c.ole.ps $fcc7,$f21,$f8 - c.ole.s $fcc3,$f7,$f20 - c.olt.d $fcc4,$f19,$f28 c.olt.ps $fcc3,$f7,$f16 - c.olt.s $fcc6,$f20,$f7 - c.seq.d $fcc4,$f31,$f7 c.seq.ps $fcc6,$f31,$f14 - c.seq.s $fcc7,$f1,$f25 c.sf.ps $fcc6,$f4,$f6 - c.ueq.d $fcc4,$f13,$f25 c.ueq.ps $fcc1,$f5,$f29 - c.ueq.s $fcc6,$f3,$f30 - c.ule.d $fcc7,$f25,$f18 c.ule.ps $fcc6,$f17,$f3 - c.ule.s $fcc7,$f21,$f30 - c.ult.d $fcc6,$f6,$f17 c.ult.ps $fcc7,$f14,$f0 - c.ult.s $fcc7,$f24,$f10 - c.un.d $fcc6,$f23,$f24 c.un.ps $fcc4,$f2,$f26 - c.un.s $fcc1,$f30,$f4 cvt.ps.s $f3,$f18,$f19 cvt.s.pl $f30,$f1 cvt.s.pu $f14,$f25 Index: test/MC/Mips/mips64r5/valid.s =================================================================== --- test/MC/Mips/mips64r5/valid.s +++ test/MC/Mips/mips64r5/valid.s @@ -41,10 +41,38 @@ bltzl $s1,-9964 # CHECK: bltzl $17, -9964 # encoding: [0x06,0x22,0xf6,0x45] bnel $gp,$s4,5107 # CHECK: bnel $gp, $20, 5107 # encoding: [0x57,0x94,0x04,0xfc] cache 1, 8($5) # CHECK: cache 1, 8($5) # encoding: [0xbc,0xa1,0x00,0x08] - c.ngl.d $f29,$f29 - c.ngle.d $f0,$f16 - c.sf.d $f30,$f0 - c.sf.s $f14,$f22 + c.eq.d $fcc1, $f14, $f14 # CHECK: c.eq.d $fcc1, $f14, $f14 # encoding: [0x46,0x2e,0x71,0x32] + c.eq.s $fcc5, $f24, $f17 # CHECK: c.eq.s $fcc5, $f24, $f17 # encoding: [0x46,0x11,0xc5,0x32] + c.f.d $fcc4, $f10, $f20 # CHECK: c.f.d $fcc4, $f10, $f20 # encoding: [0x46,0x34,0x54,0x30] + c.f.s $fcc4, $f30, $f7 # CHECK: c.f.s $fcc4, $f30, $f7 # encoding: [0x46,0x07,0xf4,0x30] + c.le.d $fcc4, $f18, $f0 # CHECK: c.le.d $fcc4, $f18, $f0 # encoding: [0x46,0x20,0x94,0x3e] + c.le.s $fcc6, $f24, $f4 # CHECK: c.le.s $fcc6, $f24, $f4 # encoding: [0x46,0x04,0xc6,0x3e] + c.lt.d $fcc3, $f8, $f2 # CHECK: c.lt.d $fcc3, $f8, $f2 # encoding: [0x46,0x22,0x43,0x3c] + c.lt.s $fcc2, $f17, $f14 # CHECK: c.lt.s $fcc2, $f17, $f14 # encoding: [0x46,0x0e,0x8a,0x3c] + c.nge.d $fcc5, $f20, $f16 # CHECK: c.nge.d $fcc5, $f20, $f16 # encoding: [0x46,0x30,0xa5,0x3d] + c.nge.s $fcc3, $f11, $f8 # CHECK: c.nge.s $fcc3, $f11, $f8 # encoding: [0x46,0x08,0x5b,0x3d] + c.ngl.s $fcc2, $f31, $f23 # CHECK: c.ngl.s $fcc2, $f31, $f23 # encoding: [0x46,0x17,0xfa,0x3b] + c.ngle.s $fcc2, $f18, $f23 # CHECK: c.ngle.s $fcc2, $f18, $f23 # encoding: [0x46,0x17,0x92,0x39] + c.ngl.d $f28, $f28 # CHECK: c.ngl.d $f28, $f28 # encoding: [0x46,0x3c,0xe0,0x3b] + c.ngle.d $f0, $f16 # CHECK: c.ngle.d $f0, $f16 # encoding: [0x46,0x30,0x00,0x39] + c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x46,0x26,0xc4,0x3f] + c.ngt.s $fcc5, $f8, $f13 # CHECK: c.ngt.s $fcc5, $f8, $f13 # encoding: [0x46,0x0d,0x45,0x3f] + c.ole.d $fcc2, $f16, $f30 # CHECK: c.ole.d $fcc2, $f16, $f30 # encoding: [0x46,0x3e,0x82,0x36] + c.ole.s $fcc3, $f7, $f20 # CHECK: c.ole.s $fcc3, $f7, $f20 # encoding: [0x46,0x14,0x3b,0x36] + c.olt.d $fcc4, $f18, $f28 # CHECK: c.olt.d $fcc4, $f18, $f28 # encoding: [0x46,0x3c,0x94,0x34] + c.olt.s $fcc6, $f20, $f7 # CHECK: c.olt.s $fcc6, $f20, $f7 # encoding: [0x46,0x07,0xa6,0x34] + c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x46,0x26,0xf4,0x3a] + c.seq.s $fcc7, $f1, $f25 # CHECK: c.seq.s $fcc7, $f1, $f25 # encoding: [0x46,0x19,0x0f,0x3a] + c.sf.d $f30, $f0 # CHECK: c.sf.d $f30, $f0 # encoding: [0x46,0x20,0xf0,0x38] + c.sf.s $f14, $f22 # CHECK: c.sf.s $f14, $f22 # encoding: [0x46,0x16,0x70,0x38] + c.ueq.d $fcc4, $f12, $f24 # CHECK: c.ueq.d $fcc4, $f12, $f24 # encoding: [0x46,0x38,0x64,0x33] + c.ueq.s $fcc6, $f3, $f30 # CHECK: c.ueq.s $fcc6, $f3, $f30 # encoding: [0x46,0x1e,0x1e,0x33] + c.ule.d $fcc7, $f24, $f18 # CHECK: c.ule.d $fcc7, $f24, $f18 # encoding: [0x46,0x32,0xc7,0x37] + c.ule.s $fcc7, $f21, $f30 # CHECK: c.ule.s $fcc7, $f21, $f30 # encoding: [0x46,0x1e,0xaf,0x37] + c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x46,0x30,0x36,0x35] + c.ult.s $fcc7, $f24, $f10 # CHECK: c.ult.s $fcc7, $f24, $f10 # encoding: [0x46,0x0a,0xc7,0x35] + c.un.d $fcc6, $f22, $f24 # CHECK: c.un.d $fcc6, $f22, $f24 # encoding: [0x46,0x38,0xb6,0x31] + c.un.s $fcc1, $f30, $f4 # CHECK: c.un.s $fcc1, $f30, $f4 # encoding: [0x46,0x04,0xf1,0x31] ceil.l.d $f1,$f3 ceil.l.s $f18,$f13 ceil.w.d $f11,$f25