Index: include/llvm/Target/TargetInstrInfo.h
===================================================================
--- include/llvm/Target/TargetInstrInfo.h
+++ include/llvm/Target/TargetInstrInfo.h
@@ -480,6 +480,19 @@
     return true;
   }
 
+
+  /// Return true if the offset is in range of the branch instruction and
+  /// false otherwise.
+  virtual bool isBranchOffsetInRange(unsigned Opcode, int Offset) const {
+    return true;
+  }
+
+  /// Return the opcode if there exist a branch instruction with a smaller
+  /// encoding, or ~0U otherwise.
+  virtual unsigned shrunkBranchOpcode(unsigned Opcode) const {
+    return ~0U;
+  }
+
   /// Represents a predicate at the MachineFunction level.  The control flow a
   /// MachineBranchPredicate represents is:
   ///
Index: lib/Target/ARM/ARMBaseInstrInfo.h
===================================================================
--- lib/Target/ARM/ARMBaseInstrInfo.h
+++ lib/Target/ARM/ARMBaseInstrInfo.h
@@ -120,6 +120,8 @@
                                      const ScheduleDAG *DAG) const override;
 
   // Branch analysis.
+  bool isBranchOffsetInRange(unsigned Opcode, int Offset) const override;
+  unsigned shrunkBranchOpcode(unsigned Opcode) const override;
   bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
                      MachineBasicBlock *&FBB,
                      SmallVectorImpl<MachineOperand> &Cond,
Index: lib/Target/ARM/ARMBaseInstrInfo.cpp
===================================================================
--- lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -290,6 +290,29 @@
 }
 
 // Branch analysis.
+bool
+ARMBaseInstrInfo::isBranchOffsetInRange(unsigned Opcode, int Offset) const {
+  switch (Opcode) {
+    case ARM::tBcc:
+      if (Offset < -256 || Offset > 254)
+        return false;
+    case ARM::tB:
+      if (Offset < -2048 || Offset > 2046)
+        return false;
+  }
+  return true;
+}
+
+unsigned ARMBaseInstrInfo::shrunkBranchOpcode(unsigned Opcode) const {
+  switch (Opcode) {
+  case ARM::t2B:
+    return ARM::tB;
+  case ARM::t2Bcc:
+    return ARM::tBcc;
+  }
+  return ~0U;
+}
+
 bool ARMBaseInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
                                      MachineBasicBlock *&TBB,
                                      MachineBasicBlock *&FBB,