Index: lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -946,6 +946,14 @@
     SDValue OpL = GetPromotedInteger(NewLHS);
     SDValue OpR = GetPromotedInteger(NewRHS);
 
+    auto IsSExtWithZero = [](const SDValue &Op1, const SDValue &New1,
+                             const SDValue &Op2) -> bool {
+      return Op1->getOpcode() == ISD::AssertSext &&
+             cast<VTSDNode>(Op1->getOperand(1))->getVT() ==
+                 New1.getValueType() &&
+             isa<ConstantSDNode>(Op2) &&
+             dyn_cast<ConstantSDNode>(Op2)->isNullValue();
+    };
     // We would prefer to promote the comparison operand with sign extension,
     // if we find the operand is actually to truncate an AssertSext. With this
     // optimization, we can avoid inserting real truncate instruction, which
@@ -956,6 +964,12 @@
         cast<VTSDNode>(OpR->getOperand(1))->getVT() == NewRHS.getValueType()) {
       NewLHS = OpL;
       NewRHS = OpR;
+    } else if (IsSExtWithZero(OpL, NewLHS, OpR) ||
+               IsSExtWithZero(OpR, NewRHS, OpL)) {
+      // If one operand is sign extension and the other is constant zero, we can
+      // avoid truncation.
+      NewLHS = OpL;
+      NewRHS = OpR;
     } else {
       NewLHS = ZExtPromotedInteger(NewLHS);
       NewRHS = ZExtPromotedInteger(NewRHS);
Index: test/CodeGen/AArch64/arm64-shrink-wrapping.ll
===================================================================
--- test/CodeGen/AArch64/arm64-shrink-wrapping.ll
+++ test/CodeGen/AArch64/arm64-shrink-wrapping.ll
@@ -508,8 +508,7 @@
 ; CHECK-LABEL: noreturn:
 ; DISABLE: stp
 ;
-; CHECK: and [[TEST:w[0-9]+]], w0, #0xff
-; CHECK-NEXT: cbnz [[TEST]], [[ABORT:LBB[0-9_]+]]
+; CHECK: cbnz w0, [[ABORT:LBB[0-9_]+]]
 ;
 ; CHECK: mov w0, #42
 ;
Index: test/CodeGen/ARM/2016-07-28-cmp-with-zero.ll
===================================================================
--- /dev/null
+++ test/CodeGen/ARM/2016-07-28-cmp-with-zero.ll
@@ -0,0 +1,45 @@
+;RUN: llc -mtriple=thumbv7-eabi < %s | FileCheck %s
+
+define void @test(i16 signext %x) optsize {
+;CHECK-LABEL: test
+entry:
+  %tobool = icmp eq i16 %x, 0
+  br i1 %tobool, label %if.else, label %if.then
+;CHECK-NOT: movw {{.*}}, #65535
+;CHECK: cbz r0,
+if.then:                                          ; preds = %entry
+  tail call void bitcast (void (...)* @foo1 to void ()*)()
+  br label %if.end
+
+if.else:                                          ; preds = %entry
+  tail call void bitcast (void (...)* @foo2 to void ()*)()
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %if.then
+  ret void
+}
+
+define void @test_u(i16 zeroext %x) optsize {
+;CHECK-LABEL: test_u
+entry:
+  %tobool = icmp eq i16 %x, 0
+  br i1 %tobool, label %if.else, label %if.then
+;CHECK-NOT: movw {{.*}}, #65535
+;CHECK: cbz r0,
+if.then:                                          ; preds = %entry
+  tail call void bitcast (void (...)* @foo1 to void ()*)()
+  br label %if.end
+
+if.else:                                          ; preds = %entry
+  tail call void bitcast (void (...)* @foo2 to void ()*)()
+  br label %if.end
+
+if.end:                                           ; preds = %if.else, %if.then
+  ret void
+}
+
+
+declare void @foo1(...)
+declare void @foo2(...)
+
+
Index: test/CodeGen/ARM/arm-shrink-wrapping.ll
===================================================================
--- test/CodeGen/ARM/arm-shrink-wrapping.ll
+++ test/CodeGen/ARM/arm-shrink-wrapping.ll
@@ -501,9 +501,13 @@
 ;
 ; CHECK-LABEL: noreturn:
 ; DISABLE: push
-;
-; CHECK: tst{{(\.w)?}}  r0, #255
-; CHECK-NEXT: bne      [[ABORT:LBB[0-9_]+]]
+; ARM-ENABLE: cmp r0, #0
+; ARM-DISABLE: cmp r0, #0
+; ARM-ENABLE: bne [[ABORT:LBB[0-9_]+]]
+; ARM-DISABLE: bne [[ABORT:LBB[0-9_]+]]
+; THUMB-ENABLE: cbnz r0,  [[ABORT:LBB[0-9_]+]]
+; THUMB-DISABLE: cbnz r0,  [[ABORT:LBB[0-9_]+]]
+
 ;
 ; CHECK: mov{{s?}} r0, #42
 ;
Index: test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
===================================================================
--- test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
+++ test/CodeGen/PowerPC/ppc-shrink-wrapping.ll
@@ -493,7 +493,7 @@
 ; CHECK-LABEL: noreturn:
 ; DISABLE: mflr {{[0-9]+}}
 ;
-; CHECK: cmplwi 3, 0
+; CHECK: cmplwi 0, 3, 0
 ; CHECK-NEXT: bne{{[-]?}} 0, .[[ABORT:LBB[0-9_]+]]
 ;
 ; CHECK: li 3, 42
Index: test/CodeGen/Thumb/thumb-shrink-wrapping.ll
===================================================================
--- test/CodeGen/Thumb/thumb-shrink-wrapping.ll
+++ test/CodeGen/Thumb/thumb-shrink-wrapping.ll
@@ -571,8 +571,7 @@
 ; CHECK-LABEL: noreturn:
 ; DISABLE: push
 ;
-; CHECK: movs [[TMP:r[0-9]+]], #255
-; CHECK-NEXT: tst  r0, [[TMP]]
+; CHECK: cmp r0, #0
 ; CHECK-NEXT: bne      [[ABORT:LBB[0-9_]+]]
 ;
 ; CHECK: movs r0, #42