Index: llvm/trunk/lib/Target/AArch64/AArch64BranchRelaxation.cpp =================================================================== --- llvm/trunk/lib/Target/AArch64/AArch64BranchRelaxation.cpp +++ llvm/trunk/lib/Target/AArch64/AArch64BranchRelaxation.cpp @@ -177,7 +177,7 @@ void AArch64BranchRelaxation::computeBlockSize(const MachineBasicBlock &MBB) { unsigned Size = 0; for (const MachineInstr &MI : MBB) - Size += TII->GetInstSizeInBytes(MI); + Size += TII->getInstSizeInBytes(MI); BlockInfo[MBB.getNumber()].Size = Size; } @@ -195,7 +195,7 @@ // Sum instructions before MI in MBB. for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) { assert(I != MBB->end() && "Didn't find MI in its own basic block?"); - Offset += TII->GetInstSizeInBytes(*I); + Offset += TII->getInstSizeInBytes(*I); } return Offset; } @@ -420,7 +420,7 @@ MachineBasicBlock *NewBB = splitBlockBeforeInstr(MI); // No need for the branch to the next block. We're adding an unconditional // branch to the destination. - int delta = TII->GetInstSizeInBytes(MBB->back()); + int delta = TII->getInstSizeInBytes(MBB->back()); BlockInfo[MBB->getNumber()].Size -= delta; MBB->back().eraseFromParent(); // BlockInfo[SplitBB].Offset is wrong temporarily, fixed below @@ -446,12 +446,12 @@ if (MI->getOpcode() == AArch64::Bcc) invertBccCondition(MIB); MIB.addMBB(NextBB); - BlockInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back()); + BlockInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back()); BuildMI(MBB, DebugLoc(), TII->get(AArch64::B)).addMBB(DestBB); - BlockInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back()); + BlockInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back()); // Remove the old conditional branch. It may or may not still be in MBB. - BlockInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(*MI); + BlockInfo[MI->getParent()->getNumber()].Size -= TII->getInstSizeInBytes(*MI); MI->eraseFromParent(); // Finally, keep the block offsets up to date. Index: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h =================================================================== --- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h +++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h @@ -39,7 +39,7 @@ /// always be able to get register info as well (through this method). const AArch64RegisterInfo &getRegisterInfo() const { return RI; } - unsigned GetInstSizeInBytes(const MachineInstr &MI) const; + unsigned getInstSizeInBytes(const MachineInstr &MI) const; bool isAsCheapAsAMove(const MachineInstr &MI) const override; Index: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp +++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -38,7 +38,7 @@ /// GetInstSize - Return the number of bytes of code the specified /// instruction may be. This returns the maximum number of bytes. -unsigned AArch64InstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const { +unsigned AArch64InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { const MachineBasicBlock &MBB = *MI.getParent(); const MachineFunction *MF = MBB.getParent(); const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); @@ -58,7 +58,7 @@ return 0; } - llvm_unreachable("GetInstSizeInBytes()- Unable to determin insn size"); + llvm_unreachable("getInstSizeInBytes()- Unable to determin insn size"); } static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target, Index: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h =================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h @@ -154,7 +154,7 @@ /// GetInstSize - Returns the size of the specified MachineInstr. /// - virtual unsigned GetInstSizeInBytes(const MachineInstr &MI) const; + virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const; unsigned isLoadFromStackSlot(const MachineInstr &MI, int &FrameIndex) const override; Index: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -610,7 +610,7 @@ /// GetInstSize - Return the size of the specified MachineInstr. /// -unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const { +unsigned ARMBaseInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { const MachineBasicBlock &MBB = *MI.getParent(); const MachineFunction *MF = MBB.getParent(); const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo(); @@ -669,7 +669,7 @@ MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end(); while (++I != E && I->isInsideBundle()) { assert(!I->isBundle() && "No nested bundle!"); - Size += GetInstSizeInBytes(*I); + Size += getInstSizeInBytes(*I); } return Size; } Index: llvm/trunk/lib/Target/ARM/ARMComputeBlockSize.cpp =================================================================== --- llvm/trunk/lib/Target/ARM/ARMComputeBlockSize.cpp +++ llvm/trunk/lib/Target/ARM/ARMComputeBlockSize.cpp @@ -42,8 +42,8 @@ BBI.PostAlign = 0; for (MachineInstr &I : *MBB) { - BBI.Size += TII->GetInstSizeInBytes(I); - // For inline asm, GetInstSizeInBytes returns a conservative estimate. + BBI.Size += TII->getInstSizeInBytes(I); + // For inline asm, getInstSizeInBytes returns a conservative estimate. // The actual size may be smaller, but still a multiple of the instr size. if (I.isInlineAsm()) BBI.Unalign = isThumb ? 1 : 2; Index: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp =================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp @@ -823,7 +823,7 @@ // Sum instructions before MI in MBB. for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) { assert(I != MBB->end() && "Didn't find MI in its own basic block?"); - Offset += TII->GetInstSizeInBytes(*I); + Offset += TII->getInstSizeInBytes(*I); } return Offset; } @@ -1331,7 +1331,7 @@ // iterates at least once. BaseInsertOffset = std::max(UserBBI.postOffset() - UPad - 8, - UserOffset + TII->GetInstSizeInBytes(*UserMI) + 1); + UserOffset + TII->getInstSizeInBytes(*UserMI) + 1); DEBUG(dbgs() << format("Move inside block: %#x\n", BaseInsertOffset)); } unsigned EndInsertOffset = BaseInsertOffset + 4 + UPad + @@ -1341,9 +1341,9 @@ unsigned CPUIndex = CPUserIndex+1; unsigned NumCPUsers = CPUsers.size(); MachineInstr *LastIT = nullptr; - for (unsigned Offset = UserOffset + TII->GetInstSizeInBytes(*UserMI); + for (unsigned Offset = UserOffset + TII->getInstSizeInBytes(*UserMI); Offset < BaseInsertOffset; - Offset += TII->GetInstSizeInBytes(*MI), MI = std::next(MI)) { + Offset += TII->getInstSizeInBytes(*MI), MI = std::next(MI)) { assert(MI != UserMBB->end() && "Fell off end of block"); if (CPUIndex < NumCPUsers && CPUsers[CPUIndex].MI == &*MI) { CPUser &U = CPUsers[CPUIndex]; @@ -1644,7 +1644,7 @@ splitBlockBeforeInstr(MI); // No need for the branch to the next block. We're adding an unconditional // branch to the destination. - int delta = TII->GetInstSizeInBytes(MBB->back()); + int delta = TII->getInstSizeInBytes(MBB->back()); BBInfo[MBB->getNumber()].Size -= delta; MBB->back().eraseFromParent(); // BBInfo[SplitBB].Offset is wrong temporarily, fixed below @@ -1660,18 +1660,18 @@ BuildMI(MBB, DebugLoc(), TII->get(MI->getOpcode())) .addMBB(NextBB).addImm(CC).addReg(CCReg); Br.MI = &MBB->back(); - BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back()); + BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back()); if (isThumb) BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB) .addImm(ARMCC::AL).addReg(0); else BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB); - BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back()); + BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back()); unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr); ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr)); // Remove the old conditional branch. It may or may not still be in MBB. - BBInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(*MI); + BBInfo[MI->getParent()->getNumber()].Size -= TII->getInstSizeInBytes(*MI); MI->eraseFromParent(); adjustBBOffsetsAfter(MBB); return true; @@ -2084,8 +2084,8 @@ } } - unsigned NewSize = TII->GetInstSizeInBytes(*NewJTMI); - unsigned OrigSize = TII->GetInstSizeInBytes(*MI); + unsigned NewSize = TII->getInstSizeInBytes(*NewJTMI); + unsigned OrigSize = TII->getInstSizeInBytes(*MI); MI->eraseFromParent(); int Delta = OrigSize - NewSize + DeadSize; Index: llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp =================================================================== --- llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp +++ llvm/trunk/lib/Target/ARM/ARMFrameLowering.cpp @@ -1359,7 +1359,7 @@ unsigned FnSize = 0; for (auto &MBB : MF) { for (auto &MI : MBB) - FnSize += TII.GetInstSizeInBytes(MI); + FnSize += TII.getInstSizeInBytes(MI); } return FnSize; } Index: llvm/trunk/lib/Target/ARM/README-Thumb.txt =================================================================== --- llvm/trunk/lib/Target/ARM/README-Thumb.txt +++ llvm/trunk/lib/Target/ARM/README-Thumb.txt @@ -238,7 +238,7 @@ //===---------------------------------------------------------------------===// Rather than having tBR_JTr print a ".align 2" and constant island pass pad it, -add a target specific ALIGN instruction instead. That way, GetInstSizeInBytes +add a target specific ALIGN instruction instead. That way, getInstSizeInBytes won't have to over-estimate. It can also be used for loop alignment pass. //===---------------------------------------------------------------------===// Index: llvm/trunk/lib/Target/AVR/AVRInstrInfo.h =================================================================== --- llvm/trunk/lib/Target/AVR/AVRInstrInfo.h +++ llvm/trunk/lib/Target/AVR/AVRInstrInfo.h @@ -70,7 +70,7 @@ const MCInstrDesc &getBrCond(AVRCC::CondCodes CC) const; AVRCC::CondCodes getCondFromBranchOpc(unsigned Opc) const; AVRCC::CondCodes getOppositeCondition(AVRCC::CondCodes CC) const; - unsigned GetInstSizeInBytes(const MachineInstr *MI) const; + unsigned getInstSizeInBytes(const MachineInstr *MI) const; void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, const DebugLoc &DL, unsigned DestReg, unsigned SrcReg, Index: llvm/trunk/lib/Target/AVR/AVRInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/AVR/AVRInstrInfo.cpp +++ llvm/trunk/lib/Target/AVR/AVRInstrInfo.cpp @@ -439,7 +439,7 @@ return false; } -unsigned AVRInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const { +unsigned AVRInstrInfo::getInstSizeInBytes(const MachineInstr *MI) const { unsigned Opcode = MI->getOpcode(); switch (Opcode) { Index: llvm/trunk/lib/Target/MSP430/MSP430BranchSelector.cpp =================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430BranchSelector.cpp +++ llvm/trunk/lib/Target/MSP430/MSP430BranchSelector.cpp @@ -70,7 +70,7 @@ for (MachineBasicBlock &MBB : Fn) { unsigned BlockSize = 0; for (MachineInstr &MI : MBB) - BlockSize += TII->GetInstSizeInBytes(MI); + BlockSize += TII->getInstSizeInBytes(MI); BlockSizes[MBB.getNumber()] = BlockSize; FuncSize += BlockSize; @@ -107,7 +107,7 @@ I != E; ++I) { if ((I->getOpcode() != MSP430::JCC || I->getOperand(0).isImm()) && I->getOpcode() != MSP430::JMP) { - MBBStartOffset += TII->GetInstSizeInBytes(*I); + MBBStartOffset += TII->getInstSizeInBytes(*I); continue; } Index: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h =================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h +++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h @@ -68,7 +68,7 @@ const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override; - unsigned GetInstSizeInBytes(const MachineInstr &MI) const; + unsigned getInstSizeInBytes(const MachineInstr &MI) const; // Branch folding goodness bool Index: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp +++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp @@ -293,7 +293,7 @@ /// GetInstSize - Return the number of bytes of code the specified /// instruction may be. This returns the maximum number of bytes. /// -unsigned MSP430InstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const { +unsigned MSP430InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { const MCInstrDesc &Desc = MI.getDesc(); switch (Desc.TSFlags & MSP430II::SizeMask) { Index: llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp +++ llvm/trunk/lib/Target/Mips/MipsConstantIslandPass.cpp @@ -801,7 +801,7 @@ BBI.Size = 0; for (const MachineInstr &MI : *MBB) - BBI.Size += TII->GetInstSizeInBytes(MI); + BBI.Size += TII->getInstSizeInBytes(MI); } /// getOffsetOf - Return the current offset of the specified machine instruction @@ -818,7 +818,7 @@ // Sum instructions before MI in MBB. for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) { assert(I != MBB->end() && "Didn't find MI in its own basic block?"); - Offset += TII->GetInstSizeInBytes(*I); + Offset += TII->getInstSizeInBytes(*I); } return Offset; } @@ -1297,9 +1297,9 @@ unsigned CPUIndex = CPUserIndex+1; unsigned NumCPUsers = CPUsers.size(); //MachineInstr *LastIT = 0; - for (unsigned Offset = UserOffset + TII->GetInstSizeInBytes(*UserMI); + for (unsigned Offset = UserOffset + TII->getInstSizeInBytes(*UserMI); Offset < BaseInsertOffset; - Offset += TII->GetInstSizeInBytes(*MI), MI = std::next(MI)) { + Offset += TII->getInstSizeInBytes(*MI), MI = std::next(MI)) { assert(MI != UserMBB->end() && "Fell off end of block"); if (CPUIndex < NumCPUsers && CPUsers[CPUIndex].MI == static_cast(MI)) { @@ -1622,7 +1622,7 @@ splitBlockBeforeInstr(*MI); // No need for the branch to the next block. We're adding an unconditional // branch to the destination. - int delta = TII->GetInstSizeInBytes(MBB->back()); + int delta = TII->getInstSizeInBytes(MBB->back()); BBInfo[MBB->getNumber()].Size -= delta; MBB->back().eraseFromParent(); // BBInfo[SplitBB].Offset is wrong temporarily, fixed below @@ -1644,14 +1644,14 @@ .addMBB(NextBB); } Br.MI = &MBB->back(); - BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back()); + BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back()); BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB); - BBInfo[MBB->getNumber()].Size += TII->GetInstSizeInBytes(MBB->back()); + BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back()); unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr); ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr)); // Remove the old conditional branch. It may or may not still be in MBB. - BBInfo[MI->getParent()->getNumber()].Size -= TII->GetInstSizeInBytes(*MI); + BBInfo[MI->getParent()->getNumber()].Size -= TII->getInstSizeInBytes(*MI); MI->eraseFromParent(); adjustBBOffsetsAfter(MBB); return true; Index: llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp +++ llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp @@ -602,7 +602,7 @@ // Get instruction with delay slot. MachineBasicBlock::instr_iterator DSI = I.getInstrIterator(); - if (InMicroMipsMode && TII->GetInstSizeInBytes(*std::next(DSI)) == 2 && + if (InMicroMipsMode && TII->getInstSizeInBytes(*std::next(DSI)) == 2 && DSI->isCall()) { // If instruction in delay slot is 16b change opcode to // corresponding instruction with short delay slot. @@ -692,7 +692,7 @@ bool InMicroMipsMode = STI.inMicroMipsMode(); const MipsInstrInfo *TII = STI.getInstrInfo(); unsigned Opcode = (*Slot).getOpcode(); - if (InMicroMipsMode && TII->GetInstSizeInBytes(*CurrI) == 2 && + if (InMicroMipsMode && TII->getInstSizeInBytes(*CurrI) == 2 && (Opcode == Mips::JR || Opcode == Mips::PseudoIndirectBranch || Opcode == Mips::PseudoReturn)) continue; Index: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h =================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h @@ -92,7 +92,7 @@ virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0; /// Return the number of bytes of code the specified instruction may be. - unsigned GetInstSizeInBytes(const MachineInstr &MI) const; + unsigned getInstSizeInBytes(const MachineInstr &MI) const; void storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Index: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp @@ -398,7 +398,7 @@ } /// Return the number of bytes of code the specified instruction may be. -unsigned MipsInstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const { +unsigned MipsInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { switch (MI.getOpcode()) { default: return MI.getDesc().getSize(); Index: llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp +++ llvm/trunk/lib/Target/Mips/MipsLongBranch.cpp @@ -179,7 +179,7 @@ // Compute size of MBB. for (MachineBasicBlock::instr_iterator MI = MBB->instr_begin(); MI != MBB->instr_end(); ++MI) - MBBInfos[I].Size += TII->GetInstSizeInBytes(*MI); + MBBInfos[I].Size += TII->getInstSizeInBytes(*MI); // Search for MBB's branch instruction. ReverseIter End = MBB->rend(); Index: llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp =================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp +++ llvm/trunk/lib/Target/PowerPC/PPCBranchSelector.cpp @@ -108,7 +108,7 @@ unsigned BlockSize = 0; for (MachineInstr &MI : *MBB) - BlockSize += TII->GetInstSizeInBytes(MI); + BlockSize += TII->getInstSizeInBytes(MI); BlockSizes[MBB->getNumber()] = BlockSize; FuncSize += BlockSize; @@ -155,7 +155,7 @@ Dest = I->getOperand(0).getMBB(); if (!Dest) { - MBBStartOffset += TII->GetInstSizeInBytes(*I); + MBBStartOffset += TII->getInstSizeInBytes(*I); continue; } Index: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp =================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp +++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp @@ -11243,7 +11243,7 @@ uint64_t LoopSize = 0; for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I) for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J) { - LoopSize += TII->GetInstSizeInBytes(*J); + LoopSize += TII->getInstSizeInBytes(*J); if (LoopSize > 32) break; } Index: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h =================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h @@ -256,7 +256,7 @@ /// GetInstSize - Return the number of bytes of code the specified /// instruction may be. This returns the maximum number of bytes. /// - unsigned GetInstSizeInBytes(const MachineInstr &MI) const; + unsigned getInstSizeInBytes(const MachineInstr &MI) const; void getNoopForMachoTarget(MCInst &NopInst) const override; Index: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -1808,7 +1808,7 @@ /// GetInstSize - Return the number of bytes of code the specified /// instruction may be. This returns the maximum number of bytes. /// -unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr &MI) const { +unsigned PPCInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const { unsigned Opcode = MI.getOpcode(); if (Opcode == PPC::INLINEASM) {