Index: include/llvm/IR/IntrinsicsAMDGPU.td =================================================================== --- include/llvm/IR/IntrinsicsAMDGPU.td +++ include/llvm/IR/IntrinsicsAMDGPU.td @@ -203,6 +203,7 @@ def int_amdgcn_image_load : AMDGPUImageLoad; def int_amdgcn_image_load_mip : AMDGPUImageLoad; +def int_amdgcn_image_getresinfo : AMDGPUImageLoad; class AMDGPUImageStore : Intrinsic < [], @@ -214,11 +215,110 @@ llvm_i1_ty, // da(imm) llvm_i1_ty, // glc(imm) llvm_i1_ty], // slc(imm) - []>; + [IntrWriteMem]>; def int_amdgcn_image_store : AMDGPUImageStore; def int_amdgcn_image_store_mip : AMDGPUImageStore; +class AMDGPUImageSample : Intrinsic < + [llvm_v4f32_ty], // vdata(VGPR) + [llvm_anyfloat_ty, // vaddr(VGPR) + llvm_v8i32_ty, // rsrc(SGPR) + llvm_v4i32_ty, // sampler(SGPR) + llvm_i32_ty, // dmask(imm) + llvm_i1_ty, // unorm(imm) + llvm_i1_ty, // glc(imm) + llvm_i1_ty, // slc(imm) + llvm_i1_ty, // r128(imm) + llvm_i1_ty, // tfe(imm) + llvm_i1_ty, // lwe(imm) + llvm_i1_ty], // da(imm) + [IntrReadMem]>; + +// Basic sample +def int_amdgcn_image_sample : AMDGPUImageSample; +def int_amdgcn_image_sample_cl : AMDGPUImageSample; +def int_amdgcn_image_sample_d : AMDGPUImageSample; +def int_amdgcn_image_sample_d_cl : AMDGPUImageSample; +def int_amdgcn_image_sample_l : AMDGPUImageSample; +def int_amdgcn_image_sample_b : AMDGPUImageSample; +def int_amdgcn_image_sample_b_cl : AMDGPUImageSample; +def int_amdgcn_image_sample_lz : AMDGPUImageSample; +def int_amdgcn_image_sample_cd : AMDGPUImageSample; +def int_amdgcn_image_sample_cd_cl : AMDGPUImageSample; + +// Sample with comparison +def int_amdgcn_image_sample_c : AMDGPUImageSample; +def int_amdgcn_image_sample_c_cl : AMDGPUImageSample; +def int_amdgcn_image_sample_c_d : AMDGPUImageSample; +def int_amdgcn_image_sample_c_d_cl : AMDGPUImageSample; +def int_amdgcn_image_sample_c_l : AMDGPUImageSample; +def int_amdgcn_image_sample_c_b : AMDGPUImageSample; +def int_amdgcn_image_sample_c_b_cl : AMDGPUImageSample; +def int_amdgcn_image_sample_c_lz : AMDGPUImageSample; +def int_amdgcn_image_sample_c_cd : AMDGPUImageSample; +def int_amdgcn_image_sample_c_cd_cl : AMDGPUImageSample; + +// Sample with offsets +def int_amdgcn_image_sample_o : AMDGPUImageSample; +def int_amdgcn_image_sample_cl_o : AMDGPUImageSample; +def int_amdgcn_image_sample_d_o : AMDGPUImageSample; +def int_amdgcn_image_sample_d_cl_o : AMDGPUImageSample; +def int_amdgcn_image_sample_l_o : AMDGPUImageSample; +def int_amdgcn_image_sample_b_o : AMDGPUImageSample; +def int_amdgcn_image_sample_b_cl_o : AMDGPUImageSample; +def int_amdgcn_image_sample_lz_o : AMDGPUImageSample; +def int_amdgcn_image_sample_cd_o : AMDGPUImageSample; +def int_amdgcn_image_sample_cd_cl_o : AMDGPUImageSample; + +// Sample with comparison and offsets +def int_amdgcn_image_sample_c_o : AMDGPUImageSample; +def int_amdgcn_image_sample_c_cl_o : AMDGPUImageSample; +def int_amdgcn_image_sample_c_d_o : AMDGPUImageSample; +def int_amdgcn_image_sample_c_d_cl_o : AMDGPUImageSample; +def int_amdgcn_image_sample_c_l_o : AMDGPUImageSample; +def int_amdgcn_image_sample_c_b_o : AMDGPUImageSample; +def int_amdgcn_image_sample_c_b_cl_o : AMDGPUImageSample; +def int_amdgcn_image_sample_c_lz_o : AMDGPUImageSample; +def int_amdgcn_image_sample_c_cd_o : AMDGPUImageSample; +def int_amdgcn_image_sample_c_cd_cl_o : AMDGPUImageSample; + +// Basic gather4 +def int_amdgcn_image_gather4 : AMDGPUImageSample; +def int_amdgcn_image_gather4_cl : AMDGPUImageSample; +def int_amdgcn_image_gather4_l : AMDGPUImageSample; +def int_amdgcn_image_gather4_b : AMDGPUImageSample; +def int_amdgcn_image_gather4_b_cl : AMDGPUImageSample; +def int_amdgcn_image_gather4_lz : AMDGPUImageSample; + +// Gather4 with comparison +def int_amdgcn_image_gather4_c : AMDGPUImageSample; +def int_amdgcn_image_gather4_c_cl : AMDGPUImageSample; +def int_amdgcn_image_gather4_c_l : AMDGPUImageSample; +def int_amdgcn_image_gather4_c_b : AMDGPUImageSample; +def int_amdgcn_image_gather4_c_b_cl : AMDGPUImageSample; +def int_amdgcn_image_gather4_c_lz : AMDGPUImageSample; + +// Gather4 with offsets +def int_amdgcn_image_gather4_o : AMDGPUImageSample; +def int_amdgcn_image_gather4_cl_o : AMDGPUImageSample; +def int_amdgcn_image_gather4_l_o : AMDGPUImageSample; +def int_amdgcn_image_gather4_b_o : AMDGPUImageSample; +def int_amdgcn_image_gather4_b_cl_o : AMDGPUImageSample; +def int_amdgcn_image_gather4_lz_o : AMDGPUImageSample; + +// Gather4 with comparison and offsets +def int_amdgcn_image_gather4_c_o : AMDGPUImageSample; +def int_amdgcn_image_gather4_c_cl_o : AMDGPUImageSample; +def int_amdgcn_image_gather4_c_l_o : AMDGPUImageSample; +def int_amdgcn_image_gather4_c_b_o : AMDGPUImageSample; +def int_amdgcn_image_gather4_c_b_cl_o : AMDGPUImageSample; +def int_amdgcn_image_gather4_c_lz_o : AMDGPUImageSample; + +def int_amdgcn_image_getlod : AMDGPUImageSample; + + + class AMDGPUImageAtomic : Intrinsic < [llvm_i32_ty], [llvm_i32_ty, // vdata(VGPR) Index: lib/Target/AMDGPU/SIInstructions.td =================================================================== --- lib/Target/AMDGPU/SIInstructions.td +++ lib/Target/AMDGPU/SIInstructions.td @@ -2536,6 +2536,25 @@ def : SampleRawPattern(opcode # _V4_V16), v16i32>; } + +// Image + sampler for amdgcn +class AMDGCNSamplePattern : Pat < + (name vt:$addr, v8i32:$rsrc, v4i32:$sampler, i32:$dmask, i1:$unorm, i1:$glc, + i1:$slc, i1:$r128, i1:$tfe, i1:$lwe, i1:$da), + (opcode $addr, $rsrc, $sampler, + (as_i32imm $dmask), (as_i1imm $unorm), (as_i1imm $glc), (as_i1imm $slc), + (as_i1imm $r128), (as_i1imm $tfe), (as_i1imm $lwe), (as_i1imm $da)) +>; + +multiclass AMDGCNSamplePatterns { + def : AMDGCNSamplePattern(opcode # _V4_V1), f32>; + def : AMDGCNSamplePattern(opcode # _V4_V2), v2f32>; + def : AMDGCNSamplePattern(opcode # _V4_V4), v4f32>; + def : AMDGCNSamplePattern(opcode # _V4_V8), v8f32>; + def : AMDGCNSamplePattern(opcode # _V4_V16), v16f32>; +} + + // Image only class ImagePattern : Pat < (name vt:$addr, v8i32:$rsrc, imm:$dmask, imm:$unorm, @@ -2599,6 +2618,13 @@ sub0) >; +// ======= SI Image Intrinsics ================ + +// Image load +defm : ImagePatterns; +defm : ImagePatterns; +def : ImagePattern; + // Basic sample defm : SampleRawPatterns; defm : SampleRawPatterns; @@ -2692,13 +2718,112 @@ def : SampleRawPattern; def : SampleRawPattern; -def : ImagePattern; -defm : ImagePatterns; -defm : ImagePatterns; + +// ======= amdgcn Image Intrinsics ============== + +// Image load defm : ImageLoadPatterns; defm : ImageLoadPatterns; +def : ImageLoadPattern; + +// Image store defm : ImageStorePatterns; defm : ImageStorePatterns; + +// Basic sample +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; + +// Sample with comparison +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; + +// Sample with offsets +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; + +// Sample with comparison and offsets +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; +defm : AMDGCNSamplePatterns; + +// Gather opcodes +// Only the variants which make sense are defined. +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; + +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; + +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; + +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; + +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; +def : AMDGCNSamplePattern; + +// Image atomics defm : ImageAtomicPatterns; def : ImageAtomicCmpSwapPattern; def : ImageAtomicCmpSwapPattern; Index: test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.ll =================================================================== --- /dev/null +++ test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.ll @@ -0,0 +1,364 @@ +; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s + +; GCN-LABEL: {{^}}gather4_v2: +; GCN: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_v2(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.v2f32(<2 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4: +; GCN: image_gather4 {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_cl: +; GCN: image_gather4_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_cl(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.cl.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_l: +; GCN: image_gather4_l {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_l(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.l.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_b: +; GCN: image_gather4_b {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_b(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.b.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_b_cl: +; GCN: image_gather4_b_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_b_cl(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.b.cl.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_b_cl_v8: +; GCN: image_gather4_b_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_b_cl_v8(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.b.cl.v8f32(<8 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_lz_v2: +; GCN: image_gather4_lz {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_lz_v2(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.lz.v2f32(<2 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_lz: +; GCN: image_gather4_lz {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_lz(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.lz.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + + + +; GCN-LABEL: {{^}}gather4_o: +; GCN: image_gather4_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_o(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_cl_o: +; GCN: image_gather4_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_cl_o(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.cl.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_cl_o_v8: +; GCN: image_gather4_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_cl_o_v8(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.cl.o.v8f32(<8 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_l_o: +; GCN: image_gather4_l_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_l_o(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.l.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_l_o_v8: +; GCN: image_gather4_l_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_l_o_v8(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.l.o.v8f32(<8 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_b_o: +; GCN: image_gather4_b_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_b_o(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.b.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_b_o_v8: +; GCN: image_gather4_b_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_b_o_v8(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.b.o.v8f32(<8 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_b_cl_o: +; GCN: image_gather4_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_b_cl_o(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.b.cl.o.v8f32(<8 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_lz_o: +; GCN: image_gather4_lz_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_lz_o(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.lz.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + + +; GCN-LABEL: {{^}}gather4_c: +; GCN: image_gather4_c {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_c(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.c.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_c_cl: +; GCN: image_gather4_c_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_c_cl(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.c.cl.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_c_cl_v8: +; GCN: image_gather4_c_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_c_cl_v8(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.c.cl.v8f32(<8 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_c_l: +; GCN: image_gather4_c_l {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_c_l(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.c.l.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_c_l_v8: +; GCN: image_gather4_c_l {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_c_l_v8(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.c.l.v8f32(<8 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_c_b: +; GCN: image_gather4_c_b {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_c_b(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.c.b.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_c_b_v8: +; GCN: image_gather4_c_b {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_c_b_v8(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.c.b.v8f32(<8 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_c_b_cl: +; GCN: image_gather4_c_b_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_c_b_cl(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.v8f32(<8 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_c_lz: +; GCN: image_gather4_c_lz {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_c_lz(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.c.lz.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + + +; GCN-LABEL: {{^}}gather4_c_o: +; GCN: image_gather4_c_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_c_o(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.c.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_c_o_v8: +; GCN: image_gather4_c_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_c_o_v8(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.c.o.v8f32(<8 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_c_cl_o: +; GCN: image_gather4_c_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_c_cl_o(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.c.cl.o.v8f32(<8 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_c_l_o: +; GCN: image_gather4_c_l_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_c_l_o(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.c.l.o.v8f32(<8 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_c_b_o: +; GCN: image_gather4_c_b_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_c_b_o(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.c.b.o.v8f32(<8 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_c_b_cl_o: +; GCN: image_gather4_c_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_c_b_cl_o(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.o.v8f32(<8 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_c_lz_o: +; GCN: image_gather4_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_c_lz_o(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.c.lz.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}gather4_c_lz_o_v8: +; GCN: image_gather4_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0x1 da +define void @gather4_c_lz_o_v8(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.gather4.c.lz.o.v8f32(<8 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 1, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + + +declare <4 x float> @llvm.amdgcn.image.gather4.v2f32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.cl.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.l.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.b.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.b.cl.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.b.cl.v8f32(<8 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.lz.v2f32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.lz.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 + +declare <4 x float> @llvm.amdgcn.image.gather4.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.cl.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.cl.o.v8f32(<8 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.l.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.l.o.v8f32(<8 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.b.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.b.o.v8f32(<8 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.b.cl.o.v8f32(<8 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.lz.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 + +declare <4 x float> @llvm.amdgcn.image.gather4.c.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.c.cl.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.c.cl.v8f32(<8 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.c.l.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.c.l.v8f32(<8 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.c.b.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.c.b.v8f32(<8 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.v8f32(<8 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.c.lz.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 + +declare <4 x float> @llvm.amdgcn.image.gather4.c.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.c.o.v8f32(<8 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.c.cl.o.v8f32(<8 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.c.l.o.v8f32(<8 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.c.b.o.v8f32(<8 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.c.b.cl.o.v8f32(<8 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.c.lz.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.gather4.c.lz.o.v8f32(<8 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 + + +attributes #0 = { nounwind readnone } Index: test/CodeGen/AMDGPU/llvm.amdgcn.image.getlod.ll =================================================================== --- /dev/null +++ test/CodeGen/AMDGPU/llvm.amdgcn.image.getlod.ll @@ -0,0 +1,37 @@ +; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s + +; GCN-LABEL: {{^}}getlod: +; GCN: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf da +define void @getlod(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.getlod.f32(float undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}getlod_v2: +; GCN: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf da +define void @getlod_v2(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.getlod.v2f32(<2 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}getlod_v4: +; GCN: image_get_lod {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf da +define void @getlod_v4(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.getlod.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 1) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + + +declare <4 x float> @llvm.amdgcn.image.getlod.f32(float, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.getlod.v2f32(<2 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.getlod.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 + + +attributes #0 = { nounwind readnone } Index: test/CodeGen/AMDGPU/llvm.amdgcn.image.ll =================================================================== --- test/CodeGen/AMDGPU/llvm.amdgcn.image.ll +++ test/CodeGen/AMDGPU/llvm.amdgcn.image.ll @@ -96,6 +96,20 @@ ret void } +;CHECK-LABEL: {{^}}getresinfo: +;CHECK: image_get_resinfo {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define amdgpu_ps void @getresinfo() { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.getresinfo.i32(i32 undef, <8 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0) + %r0 = extractelement <4 x float> %r, i32 0 + %r1 = extractelement <4 x float> %r, i32 1 + %r2 = extractelement <4 x float> %r, i32 2 + %r3 = extractelement <4 x float> %r, i32 3 + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %r0, float %r1, float %r2, float %r3) + ret void +} + + declare void @llvm.amdgcn.image.store.i32(<4 x float>, i32, <8 x i32>, i32, i1, i1, i1, i1) #0 declare void @llvm.amdgcn.image.store.v2i32(<4 x float>, <2 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #0 declare void @llvm.amdgcn.image.store.v4i32(<4 x float>, <4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #0 @@ -106,5 +120,8 @@ declare <4 x float> @llvm.amdgcn.image.load.v4i32(<4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #1 declare <4 x float> @llvm.amdgcn.image.load.mip.v4i32(<4 x i32>, <8 x i32>, i32, i1, i1, i1, i1) #1 +declare <4 x float> @llvm.amdgcn.image.getresinfo.i32(i32, <8 x i32>, i32, i1, i1, i1, i1) #1 +declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) + attributes #0 = { nounwind } attributes #1 = { nounwind readonly } Index: test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.ll =================================================================== --- /dev/null +++ test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.ll @@ -0,0 +1,208 @@ +; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s + +; GCN-LABEL: {{^}}sample: +; GCN: image_sample {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_cl: +; GCN: image_sample_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_cl(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.cl.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_d: +; GCN: image_sample_d {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_d(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.d.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_d_cl: +; GCN: image_sample_d_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_d_cl(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.d.cl.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_l: +; GCN: image_sample_l {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_l(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.l.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_b: +; GCN: image_sample_b {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_b(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.b.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_b_cl: +; GCN: image_sample_b_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_b_cl(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.b.cl.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_lz: +; GCN: image_sample_lz {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_lz(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.lz.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_cd: +; GCN: image_sample_cd {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_cd(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.cd.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_cd_cl: +; GCN: image_sample_cd_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_cd_cl(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_c: +; GCN: image_sample_c {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_c(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.c.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_c_cl: +; GCN: image_sample_c_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_c_cl(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.c.cl.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_c_d: +; GCN: image_sample_c_d {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_c_d(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.c.d.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_c_d_cl: +; GCN: image_sample_c_d_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_c_d_cl(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_c_l: +; GCN: image_sample_c_l {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_c_l(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.c.l.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_c_b: +; GCN: image_sample_c_b {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_c_b(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.c.b.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_c_b_cl: +; GCN: image_sample_c_b_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_c_b_cl(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_c_lz: +; GCN: image_sample_c_lz {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_c_lz(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.c.lz.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_c_cd: +; GCN: image_sample_c_cd {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_c_cd(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.c.cd.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_c_cd_cl: +; GCN: image_sample_c_cd_cl {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_c_cd_cl(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + + +declare <4 x float> @llvm.amdgcn.image.sample.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.cl.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.d.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.d.cl.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.l.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.b.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.b.cl.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.lz.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.cd.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 + +declare <4 x float> @llvm.amdgcn.image.sample.c.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.c.cl.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.c.d.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.c.l.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.c.b.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.c.b.cl.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.c.lz.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.c.cd.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 + + +attributes #0 = { nounwind readnone } Index: test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.o.ll =================================================================== --- /dev/null +++ test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.o.ll @@ -0,0 +1,208 @@ +; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s +; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s + +; GCN-LABEL: {{^}}sample: +; GCN: image_sample_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_cl: +; GCN: image_sample_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_cl(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.cl.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_d: +; GCN: image_sample_d_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_d(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.d.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_d_cl: +; GCN: image_sample_d_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_d_cl(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.d.cl.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_l: +; GCN: image_sample_l_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_l(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.l.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_b: +; GCN: image_sample_b_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_b(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.b.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_b_cl: +; GCN: image_sample_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_b_cl(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.b.cl.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_lz: +; GCN: image_sample_lz_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_lz(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.lz.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_cd: +; GCN: image_sample_cd_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_cd(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.cd.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_cd_cl: +; GCN: image_sample_cd_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_cd_cl(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.cd.cl.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_c: +; GCN: image_sample_c_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_c(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.c.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_c_cl: +; GCN: image_sample_c_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_c_cl(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.c.cl.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_c_d: +; GCN: image_sample_c_d_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_c_d(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.c.d.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_c_d_cl: +; GCN: image_sample_c_d_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_c_d_cl(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.c.d.cl.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_c_l: +; GCN: image_sample_c_l_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_c_l(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.c.l.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_c_b: +; GCN: image_sample_c_b_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_c_b(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.c.b.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_c_b_cl: +; GCN: image_sample_c_b_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_c_b_cl(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.c.b.cl.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_c_lz: +; GCN: image_sample_c_lz_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_c_lz(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.c.lz.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_c_cd: +; GCN: image_sample_c_cd_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_c_cd(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.c.cd.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + +; GCN-LABEL: {{^}}sample_c_cd_cl: +; GCN: image_sample_c_cd_cl_o {{v\[[0-9]+:[0-9]+\]}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}} dmask:0xf +define void @sample_c_cd_cl(<4 x float> addrspace(1)* %out) { +main_body: + %r = call <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.o.v4f32(<4 x float> undef, <8 x i32> undef, <4 x i32> undef, i32 15, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0) + store <4 x float> %r, <4 x float> addrspace(1)* %out + ret void +} + + +declare <4 x float> @llvm.amdgcn.image.sample.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.cl.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.d.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.d.cl.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.l.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.b.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.b.cl.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.lz.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.cd.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.cd.cl.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 + +declare <4 x float> @llvm.amdgcn.image.sample.c.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.c.cl.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.c.d.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.c.d.cl.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.c.l.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.c.b.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.c.b.cl.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.c.lz.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.c.cd.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 +declare <4 x float> @llvm.amdgcn.image.sample.c.cd.cl.o.v4f32(<4 x float>, <8 x i32>, <4 x i32>, i32, i1, i1, i1, i1, i1, i1, i1) #0 + + +attributes #0 = { nounwind readnone }