Index: include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
===================================================================
--- include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -23,6 +23,33 @@
 
 namespace llvm {
 
+namespace MIB {
+  struct Def {
+    unsigned Reg;
+    explicit Def(unsigned Reg) : Reg(Reg) {}
+  };
+
+  struct Use {
+    unsigned Reg;
+    explicit Use(unsigned Reg) : Reg(Reg) {}
+  };
+
+  struct FI {
+    int Idx;
+    explicit FI(int Idx) : Idx(Idx) {}
+  };
+
+  struct Imm {
+    int64_t Val;
+    explicit Imm(int64_t Val) : Val(Val) {}
+  };
+
+  struct MBB {
+    MachineBasicBlock &BB;
+    explicit MBB(MachineBasicBlock &BB) : BB(BB) {}
+  };
+}
+
 // Forward declarations.
 class MachineFunction;
 class MachineInstr;
@@ -52,15 +79,42 @@
     return *TII;
   }
 
-  static void addRegs(MachineInstrBuilder &MIB) {}
+  static void addOperands(MachineInstrBuilder &MIB) {}
 
-  template <typename... MoreRegs>
-  static void addRegs(MachineInstrBuilder &MIB, unsigned Reg,
-                      MoreRegs... Regs) {
-    MIB.addReg(Reg);
-    addRegs(MIB, Regs...);
+  template <typename... MoreOps>
+  static void addOperands(MachineInstrBuilder &MIB, MIB::Def Reg,
+                          MoreOps... Ops) {
+    MIB.addReg(Reg.Reg, RegState::Define);
+    addOperands(MIB, Ops...);
   }
 
+  template <typename... MoreOps>
+  static void addOperands(MachineInstrBuilder &MIB, MIB::Use Reg,
+                          MoreOps... Ops) {
+    MIB.addReg(Reg.Reg);
+    addOperands(MIB, Ops...);
+  }
+
+  template <typename... MoreOps>
+  static void addOperands(MachineInstrBuilder &MIB, MIB::Imm Imm,
+                          MoreOps... Ops) {
+    MIB.addImm(Imm.Val);
+    addOperands(MIB, Ops...);
+  }
+
+  template <typename... MoreOps>
+  static void addOperands(MachineInstrBuilder &MIB, MIB::FI Idx,
+                          MoreOps... Ops) {
+    MIB.addImm(Idx.Idx);
+    addOperands(MIB, Ops...);
+  }
+
+  template <typename... MoreOps>
+  static void addOperands(MachineInstrBuilder &MIB, MIB::MBB MBB,
+                          MoreOps... Ops) {
+    MIB.addMBB(&MBB.BB);
+    addOperands(MIB, Ops...);
+  }
 
 public:
   /// Getter for the function we currently build.
@@ -121,25 +175,19 @@
   /// \pre Ty == LLT{} or isPreISelGenericOpcode(Opcode)
   ///
   /// \return The newly created instruction.
-  template <typename... MoreRegs>
-  MachineInstr *buildInstr(unsigned Opcode, ArrayRef<LLT> Tys, unsigned Res,
-                           MoreRegs... Uses) {
+  template <typename... MoreOps>
+  MachineInstr *buildInstr(unsigned Opcode, ArrayRef<LLT> Tys,
+                           MoreOps... Ops) {
     MachineInstr *NewMI = buildInstr(Opcode, Tys);
     MachineInstrBuilder MIB{getMF(), NewMI};
-    MIB.addReg(Res, RegState::Define);
-    addRegs(MIB, Uses...);
-
+    addOperands(MIB, Ops...);
     return NewMI;
   }
 
-  /// Build and insert <empty> = \p Opcode <empty>.
-  ///
-  /// \pre setBasicBlock or setMI must have been called.
-  /// \pre not isPreISelGenericOpcode(\p Opcode)
-  ///
-  /// \return The newly created instruction.
-  MachineInstr *buildInstr(unsigned Opcode) {
-    return buildInstr(Opcode, ArrayRef<LLT>());
+  template <typename... MoreOps>
+  MachineInstr *buildInstr(unsigned Opcode, LLT Ty,
+                           MoreOps... Ops) {
+    return buildInstr(Opcode, ArrayRef<LLT>(Ty), Ops...);
   }
 
   /// Build and insert \p Res = \p Opcode \p Uses....
@@ -149,9 +197,9 @@
   /// \pre setBasicBlock or setMI must have been called.
   ///
   /// \return The newly created instruction.
-  template <typename... MoreRegs>
-  MachineInstr *buildInstr(unsigned Opcode, unsigned Res, MoreRegs... Uses) {
-    return buildInstr(Opcode, ArrayRef<LLT>(), Res, Uses...);
+  template <typename... MoreOps>
+  MachineInstr *buildInstr(unsigned Opcode, MoreOps... Ops) {
+    return buildInstr(Opcode, ArrayRef<LLT>(), Ops...);
   }
 
   /// Build and insert \p Res<def> = G_FRAME_INDEX \p Ty \p Idx
Index: lib/CodeGen/GlobalISel/IRTranslator.cpp
===================================================================
--- lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -70,7 +70,8 @@
   unsigned Op0 = getOrCreateVReg(*Inst.getOperand(0));
   unsigned Op1 = getOrCreateVReg(*Inst.getOperand(1));
   unsigned Res = getOrCreateVReg(Inst);
-  MIRBuilder.buildInstr(Opcode, LLT{*Inst.getType()}, Res, Op0, Op1);
+  MIRBuilder.buildInstr(Opcode, LLT{*Inst.getType()}, MIB::Def(Res),
+                        MIB::Use(Op0), MIB::Use(Op1));
   return true;
 }
 
@@ -113,7 +114,7 @@
   unsigned Op = getOrCreateVReg(*CI.getOperand(0));
   unsigned Res = getOrCreateVReg(CI);
   MIRBuilder.buildInstr(Opcode, {LLT{*CI.getDestTy()}, LLT{*CI.getSrcTy()}},
-                        Res, Op);
+                        MIB::Def(Res), MIB::Use(Op));
   return true;
 }
 
Index: lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
===================================================================
--- lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
+++ lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
@@ -72,26 +72,22 @@
 }
 
 MachineInstr *MachineIRBuilder::buildFrameIndex(LLT Ty, unsigned Res, int Idx) {
-  MachineInstr *NewMI = buildInstr(TargetOpcode::G_FRAME_INDEX, Ty);
-  auto MIB = MachineInstrBuilder(getMF(), NewMI);
-  MIB.addReg(Res, RegState::Define);
-  MIB.addImm(Idx);
-  return NewMI;
+  return buildInstr(TargetOpcode::G_FRAME_INDEX, Ty, MIB::Def{Res},
+                    MIB::FI{Idx});
 }
 
 MachineInstr *MachineIRBuilder::buildAdd(LLT Ty, unsigned Res, unsigned Op0,
                                          unsigned Op1) {
-  return buildInstr(TargetOpcode::G_ADD, Ty, Res, Op0, Op1);
+  return buildInstr(TargetOpcode::G_ADD, Ty, MIB::Def(Res), MIB::Use(Op0),
+                    MIB::Use(Op1));
 }
 
 MachineInstr *MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
-  MachineInstr *NewMI = buildInstr(TargetOpcode::G_BR, LLT::unsized());
-  MachineInstrBuilder(getMF(), NewMI).addMBB(&Dest);
-  return NewMI;
+  return buildInstr(TargetOpcode::G_BR, LLT::unsized(), MIB::MBB(Dest));
 }
 
 MachineInstr *MachineIRBuilder::buildCopy(unsigned Res, unsigned Op) {
-  return buildInstr(TargetOpcode::COPY, Res, Op);
+  return buildInstr(TargetOpcode::COPY, MIB::Def(Res), MIB::Use(Op));
 }
 
 MachineInstr *MachineIRBuilder::buildExtract(LLT Ty, ArrayRef<unsigned> Results,
Index: lib/Target/AArch64/AArch64CallLowering.cpp
===================================================================
--- lib/Target/AArch64/AArch64CallLowering.cpp
+++ lib/Target/AArch64/AArch64CallLowering.cpp
@@ -45,8 +45,7 @@
     unsigned ResReg = (Size == 32) ? AArch64::W0 : AArch64::X0;
     // Set the insertion point to be right before Return.
     MIRBuilder.setInstr(*Return, /* Before */ true);
-    MachineInstr *Copy =
-        MIRBuilder.buildInstr(TargetOpcode::COPY, ResReg, VReg);
+    MachineInstr *Copy = MIRBuilder.buildCopy(ResReg, VReg);
     (void)Copy;
     assert(Copy->getNextNode() == Return &&
            "The insertion did not happen where we expected");
@@ -85,7 +84,7 @@
     assert(VA.isRegLoc() && "Not yet implemented");
     // Transform the arguments in physical registers into virtual ones.
     MIRBuilder.getMBB().addLiveIn(VA.getLocReg());
-    MIRBuilder.buildInstr(TargetOpcode::COPY, VRegs[i], VA.getLocReg());
+    MIRBuilder.buildCopy(VRegs[i], VA.getLocReg());
 
     switch (VA.getLocInfo()) {
     default: