Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4825,13 +4825,19 @@
   }
 
   // fold (srl (shl x, c), c) -> (and x, cst2)
-  if (N1C && N0.getOpcode() == ISD::SHL && N0.getOperand(1) == N1) {
-    unsigned BitSize = N0.getScalarValueSizeInBits();
-    if (BitSize <= 64) {
-      uint64_t ShAmt = N1C->getZExtValue() + 64 - BitSize;
-      SDLoc DL(N);
-      return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0),
-                         DAG.getConstant(~0ULL >> ShAmt, DL, VT));
+  if (N1C && N0.getOpcode() == ISD::SHL &&
+      isa<ConstantSDNode>(N0.getOperand(1))) {
+    APInt c1 = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue();
+    APInt c0 = N1C->getAPIntValue();
+    ZeroExtendToMatch(c1, c0);
+    if (c1.eq(c0)) {
+      unsigned BitSize = N0.getScalarValueSizeInBits();
+      if (BitSize <= 64) {
+        uint64_t ShAmt = N1C->getZExtValue() + 64 - BitSize;
+        SDLoc DL(N);
+        return DAG.getNode(ISD::AND, DL, VT, N0.getOperand(0),
+                           DAG.getConstant(~0ULL >> ShAmt, DL, VT));
+      }
     }
   }
 
Index: test/CodeGen/X86/cmp-zext-combine.ll
===================================================================
--- /dev/null
+++ test/CodeGen/X86/cmp-zext-combine.ll
@@ -0,0 +1,14 @@
+; RUN: llc -march=x86-64 < %s | FileCheck %s
+
+define i32 @nonzero(i32) {
+; CHECK-LABEL: nonzero:
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    testl %edi, %edi
+; CHECK-NEXT:    setne %al
+; CHECK-NEXT:    retq
+  %b = zext i32 %0 to i64
+  %c = shl i64 %b, 32
+  %d = icmp ugt i64 %c, 4294967295
+  %rv = zext i1 %d to i32
+  ret i32 %rv
+}