Index: include/llvm/CodeGen/MIRYamlMapping.h =================================================================== --- include/llvm/CodeGen/MIRYamlMapping.h +++ include/llvm/CodeGen/MIRYamlMapping.h @@ -383,7 +383,6 @@ bool ExposesReturnsTwice = false; bool HasInlineAsm = false; // Register information - bool IsSSA = false; bool TracksRegLiveness = false; bool TracksSubRegLiveness = false; std::vector VirtualRegisters; @@ -405,7 +404,6 @@ YamlIO.mapOptional("alignment", MF.Alignment); YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice); YamlIO.mapOptional("hasInlineAsm", MF.HasInlineAsm); - YamlIO.mapOptional("isSSA", MF.IsSSA); YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness); YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness); YamlIO.mapOptional("registers", MF.VirtualRegisters); Index: lib/CodeGen/MIRParser/MIRParser.cpp =================================================================== --- lib/CodeGen/MIRParser/MIRParser.cpp +++ lib/CodeGen/MIRParser/MIRParser.cpp @@ -291,8 +291,23 @@ } } } + MachineFunctionProperties &Properties = MF.getProperties(); if (NoPHIs) - MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs); + Properties.set(MachineFunctionProperties::Property::NoPHIs); + + bool IsSSA = true; + const MachineRegisterInfo &MRI = MF.getRegInfo(); + for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) { + unsigned Reg = TargetRegisterInfo::index2VirtReg(I); + if (!MRI.hasOneDef(Reg) && !MRI.def_empty(Reg)) { + IsSSA = false; + break; + } + } + if (IsSSA) + Properties.set(MachineFunctionProperties::Property::IsSSA); + else + Properties.clear(MachineFunctionProperties::Property::IsSSA); } bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) { @@ -372,9 +387,6 @@ const yaml::MachineFunction &YamlMF) { MachineFunction &MF = PFS.MF; MachineRegisterInfo &RegInfo = MF.getRegInfo(); - assert(RegInfo.isSSA()); - if (!YamlMF.IsSSA) - RegInfo.leaveSSA(); assert(RegInfo.tracksLiveness()); if (!YamlMF.TracksRegLiveness) RegInfo.invalidateLiveness(); Index: lib/CodeGen/MIRPrinter.cpp =================================================================== --- lib/CodeGen/MIRPrinter.cpp +++ lib/CodeGen/MIRPrinter.cpp @@ -201,7 +201,6 @@ void MIRPrinter::convert(yaml::MachineFunction &MF, const MachineRegisterInfo &RegInfo, const TargetRegisterInfo *TRI) { - MF.IsSSA = RegInfo.isSSA(); MF.TracksRegLiveness = RegInfo.tracksLiveness(); MF.TracksSubRegLiveness = RegInfo.subRegLivenessEnabled(); Index: lib/CodeGen/MachineVerifier.cpp =================================================================== --- lib/CodeGen/MachineVerifier.cpp +++ lib/CodeGen/MachineVerifier.cpp @@ -555,7 +555,8 @@ MachineVerifier::visitMachineBasicBlockBefore(const MachineBasicBlock *MBB) { FirstTerminator = nullptr; - if (MRI->isSSA()) { + if (!MF->getProperties().hasProperty( + MachineFunctionProperties::Property::NoPHIs)) { // If this block has allocatable physical registers live-in, check that // it is an entry block or landing pad. for (const auto &LI : MBB->liveins()) { Index: test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir +++ test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir @@ -60,7 +60,6 @@ # Check that we assign a relevant register bank for %0. # Based on the type i32, this should be gpr. name: defaultMapping -isSSA: true # CHECK: registers: # CHECK-NEXT: - { id: 0, class: gpr } registers: @@ -77,7 +76,6 @@ # Based on the type <2 x i32>, this should be fpr. # FPR is used for both floating point and vector registers. name: defaultMappingVector -isSSA: true # CHECK: registers: # CHECK-NEXT: - { id: 0, class: fpr } registers: @@ -94,7 +92,6 @@ # Indeed based on the source of the copy it should live # in FPR, but at the use, it should be GPR. name: defaultMapping1Repair -isSSA: true # CHECK: registers: # CHECK-NEXT: - { id: 0, class: fpr } # CHECK-NEXT: - { id: 1, class: gpr } @@ -114,7 +111,6 @@ # Check that we repair the assignment for %0 differently for both uses. name: defaultMapping2Repairs -isSSA: true # CHECK: registers: # CHECK-NEXT: - { id: 0, class: fpr } # CHECK-NEXT: - { id: 1, class: gpr } @@ -140,7 +136,6 @@ # requires that it lives in GPR. Make sure regbankselect # fixes that. name: defaultMappingDefRepair -isSSA: true # CHECK: registers: # CHECK-NEXT: - { id: 0, class: gpr } # CHECK-NEXT: - { id: 1, class: fpr } @@ -161,7 +156,6 @@ --- # Check that we are able to propagate register banks from phis. name: phiPropagation -isSSA: true tracksRegLiveness: true # CHECK: registers: # CHECK-NEXT: - { id: 0, class: gpr32 } @@ -198,7 +192,6 @@ --- # Make sure we can repair physical register uses as well. name: defaultMappingUseRepairPhysReg -isSSA: true # CHECK: registers: # CHECK-NEXT: - { id: 0, class: gpr } # CHECK-NEXT: - { id: 1, class: gpr } @@ -219,7 +212,6 @@ --- # Make sure we can repair physical register defs. name: defaultMappingDefRepairPhysReg -isSSA: true # CHECK: registers: # CHECK-NEXT: - { id: 0, class: gpr } # CHECK-NEXT: - { id: 1, class: gpr } @@ -239,7 +231,6 @@ # Check that the greedy mode is able to switch the # G_OR instruction from fpr to gpr. name: greedyMappingOr -isSSA: true # CHECK: registers: # CHECK-NEXT: - { id: 0, class: gpr } # CHECK-NEXT: - { id: 1, class: gpr } @@ -285,7 +276,6 @@ # G_OR instruction from fpr to gpr, while still honoring # %2 constraint. name: greedyMappingOrWithConstraints -isSSA: true # CHECK: registers: # CHECK-NEXT: - { id: 0, class: gpr } # CHECK-NEXT: - { id: 1, class: gpr } Index: test/CodeGen/AArch64/GlobalISel/legalize-add.mir =================================================================== --- test/CodeGen/AArch64/GlobalISel/legalize-add.mir +++ test/CodeGen/AArch64/GlobalISel/legalize-add.mir @@ -12,7 +12,6 @@ --- name: test_vector_add -isSSA: true registers: - { id: 0, class: _ } - { id: 1, class: _ } Index: test/CodeGen/AArch64/ldst-opt-dbg-limit.mir =================================================================== --- test/CodeGen/AArch64/ldst-opt-dbg-limit.mir +++ test/CodeGen/AArch64/ldst-opt-dbg-limit.mir @@ -29,7 +29,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -isSSA: false tracksRegLiveness: false tracksSubRegLiveness: false liveins: @@ -86,7 +85,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -isSSA: false tracksRegLiveness: false tracksSubRegLiveness: false liveins: Index: test/CodeGen/AArch64/movimm-wzr.mir =================================================================== --- test/CodeGen/AArch64/movimm-wzr.mir +++ test/CodeGen/AArch64/movimm-wzr.mir @@ -16,7 +16,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -isSSA: false tracksRegLiveness: false tracksSubRegLiveness: false frameInfo: Index: test/CodeGen/AMDGPU/detect-dead-lanes.mir =================================================================== --- test/CodeGen/AMDGPU/detect-dead-lanes.mir +++ test/CodeGen/AMDGPU/detect-dead-lanes.mir @@ -26,7 +26,6 @@ # CHECK: S_NOP 0, implicit %4:sub1 # CHECK: S_NOP 0, implicit undef %5:sub0 name: test0 -isSSA: true registers: - { id: 0, class: sreg_32 } - { id: 1, class: sreg_32 } @@ -84,7 +83,6 @@ # CHECK: %10 = EXTRACT_SUBREG undef %0, {{[0-9]+}} # CHECK: S_NOP 0, implicit undef %10 name: test1 -isSSA: true registers: - { id: 0, class: sreg_128 } - { id: 1, class: sreg_128 } @@ -163,7 +161,6 @@ # CHECK: S_NOP 0, implicit %16:sub1 name: test2 -isSSA: true registers: - { id: 0, class: sreg_32 } - { id: 1, class: sreg_32 } @@ -221,7 +218,6 @@ # CHECK: %1 = COPY %vcc # CHECK: S_NOP 0, implicit %1 name: test3 -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: sreg_64 } @@ -242,7 +238,6 @@ # CHECK: %1 = IMPLICIT_DEF # CHECK: S_NOP 0, implicit undef %1 name: test4 -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: sreg_64 } @@ -263,7 +258,6 @@ # CHECK: %1 = REG_SEQUENCE undef %0, {{[0-9]+}}, %0, {{[0-9]+}} # CHECK: S_NOP 0, implicit %1:sub1 name: test5 -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: sreg_32 } @@ -290,7 +284,6 @@ # CHECK: S_NOP 0, implicit %4:sub0 # CHECK: S_NOP 0, implicit undef %4:sub3 name: loop0 -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: sreg_32 } @@ -344,7 +337,6 @@ # CHECK: bb.2: # CHECK: S_NOP 0, implicit %6:sub3 name: loop1 -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: sreg_32 } @@ -396,7 +388,6 @@ # CHECK: S_NOP 0, implicit %2:sub2 # CHECK: S_NOP 0, implicit %2:sub3 name: loop2 -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: sreg_32 } Index: test/CodeGen/AMDGPU/rename-independent-subregs.mir =================================================================== --- test/CodeGen/AMDGPU/rename-independent-subregs.mir +++ test/CodeGen/AMDGPU/rename-independent-subregs.mir @@ -15,7 +15,6 @@ # CHECK: S_NOP 0, implicit-def %0:sub1 # CHECK: S_NOP 0, implicit %0 name: test0 -isSSA: true registers: - { id: 0, class: sreg_128 } body: | Index: test/CodeGen/ARM/ARMLoadStoreDBG.mir =================================================================== --- test/CodeGen/ARM/ARMLoadStoreDBG.mir +++ test/CodeGen/ARM/ARMLoadStoreDBG.mir @@ -80,7 +80,6 @@ alignment: 1 exposesReturnsTwice: false hasInlineAsm: false -isSSA: false tracksRegLiveness: true tracksSubRegLiveness: false liveins: Index: test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir =================================================================== --- test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir +++ test/CodeGen/MIR/AArch64/generic-virtual-registers-error.mir @@ -10,7 +10,6 @@ --- name: baz -isSSA: true registers: - { id: 0, class: _ } body: | Index: test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir =================================================================== --- test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir +++ test/CodeGen/MIR/AArch64/generic-virtual-registers-with-regbank-error.mir @@ -11,7 +11,6 @@ --- name: bar -isSSA: true registers: - { id: 0, class: gpr } body: | Index: test/CodeGen/MIR/AArch64/machine-scheduler.mir =================================================================== --- test/CodeGen/MIR/AArch64/machine-scheduler.mir +++ test/CodeGen/MIR/AArch64/machine-scheduler.mir @@ -22,7 +22,6 @@ # CHECK: LDRWui %x0, 1 # CHECK: STRWui %w1, %x0, 2 name: load_imp-def -isSSA: true body: | bb.0.entry: liveins: %w1, %x0 Index: test/CodeGen/MIR/AArch64/stack-object-local-offset.mir =================================================================== --- test/CodeGen/MIR/AArch64/stack-object-local-offset.mir +++ test/CodeGen/MIR/AArch64/stack-object-local-offset.mir @@ -15,7 +15,6 @@ ... --- name: stack_local -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: gpr64common } Index: test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir =================================================================== --- test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir +++ test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir @@ -91,7 +91,6 @@ alignment: 1 exposesReturnsTwice: false hasInlineAsm: false -isSSA: false tracksRegLiveness: true tracksSubRegLiveness: false liveins: Index: test/CodeGen/MIR/Generic/frame-info.mir =================================================================== --- test/CodeGen/MIR/Generic/frame-info.mir +++ test/CodeGen/MIR/Generic/frame-info.mir @@ -23,7 +23,6 @@ ... --- name: test -isSSA: true tracksRegLiveness: true # CHECK: frameInfo: @@ -49,7 +48,6 @@ ... --- name: test2 -isSSA: true tracksRegLiveness: true # CHECK: test2 Index: test/CodeGen/MIR/Generic/register-info.mir =================================================================== --- test/CodeGen/MIR/Generic/register-info.mir +++ test/CodeGen/MIR/Generic/register-info.mir @@ -17,8 +17,7 @@ ... --- # CHECK: name: foo -# CHECK: isSSA: false -# CHECK-NEXT: tracksRegLiveness: false +# CHECK: tracksRegLiveness: false # CHECK-NEXT: tracksSubRegLiveness: false # CHECK: ... name: foo @@ -27,12 +26,10 @@ ... --- # CHECK: name: bar -# CHECK: isSSA: false -# CHECK-NEXT: tracksRegLiveness: true +# CHECK: tracksRegLiveness: true # CHECK-NEXT: tracksSubRegLiveness: true # CHECK: ... name: bar -isSSA: false tracksRegLiveness: true tracksSubRegLiveness: true body: | Index: test/CodeGen/MIR/Lanai/peephole-compare.mir =================================================================== --- test/CodeGen/MIR/Lanai/peephole-compare.mir +++ test/CodeGen/MIR/Lanai/peephole-compare.mir @@ -176,7 +176,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -isSSA: true tracksRegLiveness: true tracksSubRegLiveness: false registers: @@ -223,7 +222,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -isSSA: true tracksRegLiveness: true tracksSubRegLiveness: false registers: @@ -268,7 +266,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -isSSA: true tracksRegLiveness: true tracksSubRegLiveness: false registers: @@ -317,7 +314,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -isSSA: true tracksRegLiveness: true tracksSubRegLiveness: false registers: @@ -366,7 +362,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -isSSA: true tracksRegLiveness: true tracksSubRegLiveness: false registers: @@ -415,7 +410,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -isSSA: true tracksRegLiveness: true tracksSubRegLiveness: false registers: @@ -464,7 +458,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -isSSA: true tracksRegLiveness: true tracksSubRegLiveness: false registers: @@ -513,7 +506,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -isSSA: true tracksRegLiveness: true tracksSubRegLiveness: false registers: @@ -626,7 +618,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -isSSA: true tracksRegLiveness: true tracksSubRegLiveness: false registers: Index: test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir =================================================================== --- test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir +++ test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir @@ -20,7 +20,6 @@ ... --- name: main -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: g8rc_and_g8rc_nox0 } Index: test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir =================================================================== --- test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir +++ test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir @@ -39,7 +39,6 @@ ... --- name: test -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: gr32 } Index: test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir =================================================================== --- test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir +++ test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir @@ -39,7 +39,6 @@ ... --- name: test -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: gr32 } Index: test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir =================================================================== --- test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir +++ test/CodeGen/MIR/X86/expected-named-register-in-functions-livein.mir @@ -10,7 +10,6 @@ ... --- name: test -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: gr32 } Index: test/CodeGen/MIR/X86/expected-subregister-after-colon.mir =================================================================== --- test/CodeGen/MIR/X86/expected-subregister-after-colon.mir +++ test/CodeGen/MIR/X86/expected-subregister-after-colon.mir @@ -10,7 +10,6 @@ ... --- name: t -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: gr32 } Index: test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir =================================================================== --- test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir +++ test/CodeGen/MIR/X86/expected-virtual-register-in-functions-livein.mir @@ -10,7 +10,6 @@ ... --- name: test -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: gr32 } Index: test/CodeGen/MIR/X86/function-liveins.mir =================================================================== --- test/CodeGen/MIR/X86/function-liveins.mir +++ test/CodeGen/MIR/X86/function-liveins.mir @@ -13,7 +13,6 @@ ... --- name: test -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: gr32 } Index: test/CodeGen/MIR/X86/generic-instr-type-error.mir =================================================================== --- test/CodeGen/MIR/X86/generic-instr-type-error.mir +++ test/CodeGen/MIR/X86/generic-instr-type-error.mir @@ -4,7 +4,6 @@ --- name: bar -isSSA: true registers: - { id: 0, class: gr32 } body: | Index: test/CodeGen/MIR/X86/generic-virtual-registers.mir =================================================================== --- test/CodeGen/MIR/X86/generic-virtual-registers.mir +++ test/CodeGen/MIR/X86/generic-virtual-registers.mir @@ -17,7 +17,6 @@ --- name: bar -isSSA: true # CHECK: registers: # CHECK-NEXT: - { id: 0, class: _ } # CHECK-NEXT: - { id: 1, class: _ } Index: test/CodeGen/MIR/X86/instructions-debug-location.mir =================================================================== --- test/CodeGen/MIR/X86/instructions-debug-location.mir +++ test/CodeGen/MIR/X86/instructions-debug-location.mir @@ -50,7 +50,6 @@ ... --- name: test -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: gr32 } @@ -72,7 +71,6 @@ ... --- name: test_typed_immediates -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: gr32 } Index: test/CodeGen/MIR/X86/invalid-metadata-node-type.mir =================================================================== --- test/CodeGen/MIR/X86/invalid-metadata-node-type.mir +++ test/CodeGen/MIR/X86/invalid-metadata-node-type.mir @@ -34,7 +34,6 @@ ... --- name: foo -isSSA: true tracksRegLiveness: true frameInfo: maxAlignment: 16 Index: test/CodeGen/MIR/X86/metadata-operands.mir =================================================================== --- test/CodeGen/MIR/X86/metadata-operands.mir +++ test/CodeGen/MIR/X86/metadata-operands.mir @@ -41,7 +41,6 @@ ... --- name: test -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: gr32 } Index: test/CodeGen/MIR/X86/stack-object-debug-info.mir =================================================================== --- test/CodeGen/MIR/X86/stack-object-debug-info.mir +++ test/CodeGen/MIR/X86/stack-object-debug-info.mir @@ -46,7 +46,6 @@ ... --- name: foo -isSSA: true tracksRegLiveness: true frameInfo: maxAlignment: 16 Index: test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir =================================================================== --- test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir +++ test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir @@ -15,7 +15,6 @@ ... --- name: test -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: gr32 } Index: test/CodeGen/MIR/X86/stack-object-operands.mir =================================================================== --- test/CodeGen/MIR/X86/stack-object-operands.mir +++ test/CodeGen/MIR/X86/stack-object-operands.mir @@ -17,7 +17,6 @@ ... --- name: test -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: gr32 } Index: test/CodeGen/MIR/X86/standalone-register-error.mir =================================================================== --- test/CodeGen/MIR/X86/standalone-register-error.mir +++ test/CodeGen/MIR/X86/standalone-register-error.mir @@ -7,7 +7,6 @@ ... --- name: test -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: gr32 } Index: test/CodeGen/MIR/X86/subregister-index-operands.mir =================================================================== --- test/CodeGen/MIR/X86/subregister-index-operands.mir +++ test/CodeGen/MIR/X86/subregister-index-operands.mir @@ -16,7 +16,6 @@ # CHECK: %1 = EXTRACT_SUBREG %eax, {{[0-9]+}} # CHECK: %ax = REG_SEQUENCE %1, {{[0-9]+}}, %1, {{[0-9]+}} name: t -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: gr32 } Index: test/CodeGen/MIR/X86/subregister-operands.mir =================================================================== --- test/CodeGen/MIR/X86/subregister-operands.mir +++ test/CodeGen/MIR/X86/subregister-operands.mir @@ -12,7 +12,6 @@ ... --- name: t -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: gr32 } Index: test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir =================================================================== --- test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir +++ test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir @@ -14,7 +14,6 @@ ... --- name: test -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: gr32 } Index: test/CodeGen/MIR/X86/undefined-register-class.mir =================================================================== --- test/CodeGen/MIR/X86/undefined-register-class.mir +++ test/CodeGen/MIR/X86/undefined-register-class.mir @@ -12,7 +12,6 @@ ... --- name: test -isSSA: true tracksRegLiveness: true registers: # CHECK: [[@LINE+1]]:20: use of undefined register class or register bank 'gr3200' Index: test/CodeGen/MIR/X86/undefined-stack-object.mir =================================================================== --- test/CodeGen/MIR/X86/undefined-stack-object.mir +++ test/CodeGen/MIR/X86/undefined-stack-object.mir @@ -12,7 +12,6 @@ ... --- name: test -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: gr32 } Index: test/CodeGen/MIR/X86/undefined-virtual-register.mir =================================================================== --- test/CodeGen/MIR/X86/undefined-virtual-register.mir +++ test/CodeGen/MIR/X86/undefined-virtual-register.mir @@ -12,7 +12,6 @@ ... --- name: test -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: gr32 } Index: test/CodeGen/MIR/X86/unexpected-size-non-generic-register-phys.mir =================================================================== --- test/CodeGen/MIR/X86/unexpected-size-non-generic-register-phys.mir +++ test/CodeGen/MIR/X86/unexpected-size-non-generic-register-phys.mir @@ -4,7 +4,6 @@ --- name: test_size_physreg -isSSA: true registers: body: | bb.0.entry: Index: test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir =================================================================== --- test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir +++ test/CodeGen/MIR/X86/unexpected-size-non-generic-register.mir @@ -4,7 +4,6 @@ --- name: test_size_regclass -isSSA: true registers: - { id: 0, class: gr32 } body: | Index: test/CodeGen/MIR/X86/unknown-metadata-node.mir =================================================================== --- test/CodeGen/MIR/X86/unknown-metadata-node.mir +++ test/CodeGen/MIR/X86/unknown-metadata-node.mir @@ -39,7 +39,6 @@ ... --- name: test -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: gr32 } Index: test/CodeGen/MIR/X86/unknown-subregister-index-op.mir =================================================================== --- test/CodeGen/MIR/X86/unknown-subregister-index-op.mir +++ test/CodeGen/MIR/X86/unknown-subregister-index-op.mir @@ -12,7 +12,6 @@ ... --- name: t -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: gr32 } Index: test/CodeGen/MIR/X86/unknown-subregister-index.mir =================================================================== --- test/CodeGen/MIR/X86/unknown-subregister-index.mir +++ test/CodeGen/MIR/X86/unknown-subregister-index.mir @@ -12,7 +12,6 @@ ... --- name: t -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: gr32 } Index: test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir =================================================================== --- test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir +++ test/CodeGen/MIR/X86/virtual-register-redefinition-error.mir @@ -10,7 +10,6 @@ ... --- name: test -isSSA: true tracksRegLiveness: true registers: - { id: 0, class: gr32 } Index: test/CodeGen/MIR/X86/virtual-registers.mir =================================================================== --- test/CodeGen/MIR/X86/virtual-registers.mir +++ test/CodeGen/MIR/X86/virtual-registers.mir @@ -31,7 +31,6 @@ ... --- name: bar -isSSA: true tracksRegLiveness: true # CHECK: registers: # CHECK-NEXT: - { id: 0, class: gr32 } @@ -65,7 +64,6 @@ ... --- name: foo -isSSA: true tracksRegLiveness: true # CHECK: name: foo # CHECK: registers: Index: test/CodeGen/PowerPC/aantidep-def-ec.mir =================================================================== --- test/CodeGen/PowerPC/aantidep-def-ec.mir +++ test/CodeGen/PowerPC/aantidep-def-ec.mir @@ -45,7 +45,6 @@ alignment: 4 exposesReturnsTwice: false hasInlineAsm: true -isSSA: false tracksRegLiveness: true tracksSubRegLiveness: false liveins: Index: test/CodeGen/PowerPC/addisdtprelha-nonr3.mir =================================================================== --- test/CodeGen/PowerPC/addisdtprelha-nonr3.mir +++ test/CodeGen/PowerPC/addisdtprelha-nonr3.mir @@ -27,7 +27,6 @@ alignment: 4 exposesReturnsTwice: false hasInlineAsm: false -isSSA: false tracksRegLiveness: true tracksSubRegLiveness: false frameInfo: Index: test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir =================================================================== --- test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir +++ test/CodeGen/PowerPC/no-rlwimi-trivial-commute.mir @@ -40,7 +40,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -isSSA: true tracksRegLiveness: true tracksSubRegLiveness: false registers: Index: test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir =================================================================== --- test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir +++ test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir @@ -33,7 +33,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -isSSA: true tracksRegLiveness: true tracksSubRegLiveness: false registers: Index: test/CodeGen/X86/eflags-copy-expansion.mir =================================================================== --- test/CodeGen/X86/eflags-copy-expansion.mir +++ test/CodeGen/X86/eflags-copy-expansion.mir @@ -19,7 +19,6 @@ --- name: foo -isSSA: false tracksRegLiveness: true liveins: - { reg: '%edi' } Index: test/CodeGen/X86/fixup-bw-copy.mir =================================================================== --- test/CodeGen/X86/fixup-bw-copy.mir +++ test/CodeGen/X86/fixup-bw-copy.mir @@ -38,7 +38,6 @@ --- name: test_movb_killed -isSSA: false tracksRegLiveness: true liveins: - { reg: '%edi' } @@ -54,7 +53,6 @@ --- name: test_movb_impuse -isSSA: false tracksRegLiveness: true liveins: - { reg: '%edi' } @@ -70,7 +68,6 @@ --- name: test_movb_impdef_gr64 -isSSA: false tracksRegLiveness: true liveins: - { reg: '%edi' } @@ -86,7 +83,6 @@ --- name: test_movb_impdef_gr32 -isSSA: false tracksRegLiveness: true liveins: - { reg: '%edi' } @@ -102,7 +98,6 @@ --- name: test_movb_impdef_gr16 -isSSA: false tracksRegLiveness: true liveins: - { reg: '%edi' } @@ -118,7 +113,6 @@ --- name: test_movw_impdef_gr32 -isSSA: false tracksRegLiveness: true liveins: - { reg: '%edi' } @@ -134,7 +128,6 @@ --- name: test_movw_impdef_gr64 -isSSA: false tracksRegLiveness: true liveins: - { reg: '%edi' } Index: test/CodeGen/X86/implicit-null-checks.mir =================================================================== --- test/CodeGen/X86/implicit-null-checks.mir +++ test/CodeGen/X86/implicit-null-checks.mir @@ -128,7 +128,6 @@ --- name: imp_null_check_with_bitwise_op_1 alignment: 4 -isSSA: false tracksRegLiveness: true tracksSubRegLiveness: false liveins: Index: test/DebugInfo/MIR/X86/live-debug-values-3preds.mir =================================================================== --- test/DebugInfo/MIR/X86/live-debug-values-3preds.mir +++ test/DebugInfo/MIR/X86/live-debug-values-3preds.mir @@ -158,7 +158,6 @@ alignment: 4 exposesReturnsTwice: false hasInlineAsm: false -isSSA: false tracksRegLiveness: true tracksSubRegLiveness: false liveins: Index: test/DebugInfo/MIR/X86/live-debug-values.mir =================================================================== --- test/DebugInfo/MIR/X86/live-debug-values.mir +++ test/DebugInfo/MIR/X86/live-debug-values.mir @@ -160,7 +160,6 @@ alignment: 4 exposesReturnsTwice: false hasInlineAsm: false -isSSA: false tracksRegLiveness: true tracksSubRegLiveness: false liveins: