Index: include/llvm/CodeGen/MachineFunction.h
===================================================================
--- include/llvm/CodeGen/MachineFunction.h
+++ include/llvm/CodeGen/MachineFunction.h
@@ -107,6 +107,7 @@
   // Property descriptions:
   // IsSSA: True when the machine function is in SSA form and virtual registers
   //  have a single def.
+  // NoPHIs: True if the machine function does not contain any PHI instruction.
   // TracksLiveness: True when tracking register liveness accurately.
   //  While this property is set, register liveness information in basic block
   //  live-in lists and machine instruction operands (e.g. kill flags, implicit
@@ -116,6 +117,7 @@
   //  When this property is clear, liveness is no longer reliable.
   enum class Property : unsigned {
     IsSSA,
+    NoPHIs,
     TracksLiveness,
     LastProperty,
   };
Index: lib/CodeGen/MIRParser/MIRParser.cpp
===================================================================
--- lib/CodeGen/MIRParser/MIRParser.cpp
+++ lib/CodeGen/MIRParser/MIRParser.cpp
@@ -160,6 +160,8 @@
   ///
   /// Return null if the name isn't a register bank.
   const RegisterBank *getRegBank(const MachineFunction &MF, StringRef Name);
+
+  void computeFunctionProperties(MachineFunction &MF);
 };
 
 } // end namespace llvm
@@ -279,6 +281,20 @@
   new UnreachableInst(Context, BB);
 }
 
+void MIRParserImpl::computeFunctionProperties(MachineFunction &MF) {
+  bool NoPHIs = true;
+  for (const MachineBasicBlock &MBB : MF) {
+    for (const MachineInstr &MI : MBB) {
+      if (MI.isPHI()) {
+        NoPHIs = false;
+        break;
+      }
+    }
+  }
+  if (NoPHIs)
+    MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);
+}
+
 bool MIRParserImpl::initializeMachineFunction(MachineFunction &MF) {
   auto It = Functions.find(MF.getName());
   if (It == Functions.end())
@@ -342,6 +358,9 @@
   PFS.SM = &SM;
 
   inferRegisterInfo(PFS, YamlMF);
+
+  computeFunctionProperties(MF);
+
   // FIXME: This is a temporary workaround until the reserved registers can be
   // serialized.
   MF.getRegInfo().freezeReservedRegs(MF);
Index: lib/CodeGen/MachineFunction.cpp
===================================================================
--- lib/CodeGen/MachineFunction.cpp
+++ lib/CodeGen/MachineFunction.cpp
@@ -63,8 +63,10 @@
       continue;
     switch(static_cast<Property>(i)) {
       case Property::IsSSA:
-        ROS << (HasProperty ? "SSA, " : "Post SSA, ");
+        ROS << (HasProperty ? "SSA, " : "");
         break;
+      case Property::NoPHIs:
+        ROS << (HasProperty ? "No PHIs, " : "");
       case Property::TracksLiveness:
         ROS << (HasProperty ? "" : "not ") << "tracking liveness, ";
         break;
Index: lib/CodeGen/MachineVerifier.cpp
===================================================================
--- lib/CodeGen/MachineVerifier.cpp
+++ lib/CodeGen/MachineVerifier.cpp
@@ -834,6 +834,11 @@
         << MI->getNumOperands() << " given.\n";
   }
 
+  if (MI->isPHI() && MF->getProperties().hasProperty(
+          MachineFunctionProperties::Property::NoPHIs)) {
+    report("Found PHI instruction with NoPHIs property set", MI);
+  }
+
   // Check the tied operands.
   if (MI->isInlineAsm())
     verifyInlineAsm(MI);
Index: lib/CodeGen/PHIElimination.cpp
===================================================================
--- lib/CodeGen/PHIElimination.cpp
+++ lib/CodeGen/PHIElimination.cpp
@@ -175,6 +175,8 @@
   ImpDefs.clear();
   VRegPHIUseCount.clear();
 
+  MF.getProperties().set(MachineFunctionProperties::Property::NoPHIs);
+
   return Changed;
 }
 
Index: lib/CodeGen/RegAllocBase.cpp
===================================================================
--- lib/CodeGen/RegAllocBase.cpp
+++ lib/CodeGen/RegAllocBase.cpp
@@ -59,8 +59,12 @@
   VRM = &vrm;
   LIS = &lis;
   Matrix = &mat;
-  MRI->freezeReservedRegs(vrm.getMachineFunction());
-  RegClassInfo.runOnMachineFunction(vrm.getMachineFunction());
+  const MachineFunction &MF = vrm.getMachineFunction();
+  assert(MF.getProperties().hasProperty(
+             MachineFunctionProperties::Property::NoPHIs)
+         && "PHI instructions not supported");
+  MRI->freezeReservedRegs(MF);
+  RegClassInfo.runOnMachineFunction(MF);
 }
 
 // Visit all the live registers. If they are already assigned to a physical
Index: lib/CodeGen/RegAllocFast.cpp
===================================================================
--- lib/CodeGen/RegAllocFast.cpp
+++ lib/CodeGen/RegAllocFast.cpp
@@ -1088,7 +1088,9 @@
   UsedInInstr.clear();
   UsedInInstr.setUniverse(TRI->getNumRegUnits());
 
-  assert(!MRI->isSSA() && "regalloc requires leaving SSA");
+  assert(Fn.getProperties().hasProperty(
+             MachineFunctionProperties::Property::NoPHIs)
+         && "PHI instructions not supported");
 
   // initialize the virtual->physical register map to have a 'null'
   // mapping for all virtual registers
Index: lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
===================================================================
--- lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
+++ lib/Target/AMDGPU/SILoadStoreOptimizer.cpp
@@ -424,7 +424,9 @@
 
   DEBUG(dbgs() << "Running SILoadStoreOptimizer\n");
 
-  assert(!MRI->isSSA());
+  assert(MF.getProperties().hasProperty(
+             MachineFunctionProperties::Property::NoPHIs) &&
+         "PHI instructions not supported");
 
   bool Modified = false;
 
Index: test/CodeGen/AArch64/arm64-misched-multimmo.ll
===================================================================
--- test/CodeGen/AArch64/arm64-misched-multimmo.ll
+++ test/CodeGen/AArch64/arm64-misched-multimmo.ll
@@ -7,7 +7,7 @@
 
 ; Check that no scheduling dependencies are created between the paired loads and the store during post-RA MI scheduling.
 ;
-; CHECK-LABEL: # Machine code for function foo: Properties: <Post SSA
+; CHECK-LABEL: # Machine code for function foo:
 ; CHECK: SU(2):   %W{{[0-9]+}}<def>, %W{{[0-9]+}}<def> = LDPWi
 ; CHECK: Successors:
 ; CHECK-NOT: ch SU(4)