Index: include/llvm/CodeGen/MIRYamlMapping.h =================================================================== --- include/llvm/CodeGen/MIRYamlMapping.h +++ include/llvm/CodeGen/MIRYamlMapping.h @@ -382,8 +382,6 @@ unsigned Alignment = 0; bool ExposesReturnsTwice = false; bool HasInlineAsm = false; - // MachineFunctionProperties - bool AllVRegsAllocated = false; // Register information bool IsSSA = false; bool TracksRegLiveness = false; @@ -407,7 +405,6 @@ YamlIO.mapOptional("alignment", MF.Alignment); YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice); YamlIO.mapOptional("hasInlineAsm", MF.HasInlineAsm); - YamlIO.mapOptional("allVRegsAllocated", MF.AllVRegsAllocated); YamlIO.mapOptional("isSSA", MF.IsSSA); YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness); YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness); Index: include/llvm/CodeGen/MachineFunction.h =================================================================== --- include/llvm/CodeGen/MachineFunction.h +++ include/llvm/CodeGen/MachineFunction.h @@ -94,7 +94,6 @@ /// Each of these has checking code in the MachineVerifier, and passes can /// require that a property be set. class MachineFunctionProperties { - // TODO: Add MachineVerifier checks for AllVRegsAllocated // TODO: Add a way to print the properties and make more useful error messages // Possible TODO: Allow targets to extend this (perhaps by allowing the // constructor to specify the size of the bit vector) @@ -115,12 +114,9 @@ // that affect the values in registers, for example by the register // scavenger. // When this property is clear, liveness is no longer reliable. - // AllVRegsAllocated: All virtual registers have been allocated; i.e. all - // register operands are physical registers. enum class Property : unsigned { IsSSA, TracksLiveness, - AllVRegsAllocated, LastProperty, }; @@ -349,6 +345,9 @@ const MachineFunctionProperties &getProperties() const { return Properties; } MachineFunctionProperties &getProperties() { return Properties; } + /// Returns true if any virtual register is used or defined. + bool hasVirtRegs() const; + /// getInfo - Keep track of various per-function pieces of information for /// backends that would like to do so. /// Index: lib/CodeGen/ExecutionDepsFix.cpp =================================================================== --- lib/CodeGen/ExecutionDepsFix.cpp +++ lib/CodeGen/ExecutionDepsFix.cpp @@ -168,11 +168,6 @@ bool runOnMachineFunction(MachineFunction &MF) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - const char *getPassName() const override { return "Execution dependency fix"; } @@ -724,6 +719,7 @@ } bool ExeDepsFix::runOnMachineFunction(MachineFunction &mf) { + assert(!mf.hasVirtRegs() && "Registers Allocated"); if (skipFunction(*mf.getFunction())) return false; MF = &mf; Index: lib/CodeGen/FuncletLayout.cpp =================================================================== --- lib/CodeGen/FuncletLayout.cpp +++ lib/CodeGen/FuncletLayout.cpp @@ -28,10 +28,6 @@ } bool runOnMachineFunction(MachineFunction &F) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } }; } @@ -41,6 +37,7 @@ "Contiguously Lay Out Funclets", false, false) bool FuncletLayout::runOnMachineFunction(MachineFunction &F) { + assert(!F.hasVirtRegs() && "Registers Allocated"); DenseMap FuncletMembership = getFuncletMembership(F); if (FuncletMembership.empty()) Index: lib/CodeGen/IfConversion.cpp =================================================================== --- lib/CodeGen/IfConversion.cpp +++ lib/CodeGen/IfConversion.cpp @@ -189,11 +189,6 @@ bool runOnMachineFunction(MachineFunction &MF) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - private: bool ReverseBranchCondition(BBInfo &BBI); bool ValidSimple(BBInfo &TrueBBI, unsigned &Dups, Index: lib/CodeGen/ImplicitNullChecks.cpp =================================================================== --- lib/CodeGen/ImplicitNullChecks.cpp +++ lib/CodeGen/ImplicitNullChecks.cpp @@ -126,11 +126,6 @@ AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); } - - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } }; /// \brief Detect re-ordering hazards and dependencies. @@ -290,6 +285,7 @@ } bool ImplicitNullChecks::runOnMachineFunction(MachineFunction &MF) { + assert(!MF.hasVirtRegs() && "Registers Allocated"); TII = MF.getSubtarget().getInstrInfo(); TRI = MF.getRegInfo().getTargetRegisterInfo(); MMI = &MF.getMMI(); Index: lib/CodeGen/LiveDebugValues.cpp =================================================================== --- lib/CodeGen/LiveDebugValues.cpp +++ lib/CodeGen/LiveDebugValues.cpp @@ -215,11 +215,6 @@ /// information we preserve. void getAnalysisUsage(AnalysisUsage &AU) const override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - /// Print to ostream with a message. void printVarLocInMBB(const MachineFunction &MF, const VarLocInMBB &V, const VarLocMap &VarLocIDs, const char *msg, @@ -505,6 +500,7 @@ } bool LiveDebugValues::runOnMachineFunction(MachineFunction &MF) { + assert(!MF.hasVirtRegs() && "Registers Allocated"); TRI = MF.getSubtarget().getRegisterInfo(); TII = MF.getSubtarget().getInstrInfo(); Index: lib/CodeGen/MIRParser/MIRParser.cpp =================================================================== --- lib/CodeGen/MIRParser/MIRParser.cpp +++ lib/CodeGen/MIRParser/MIRParser.cpp @@ -290,8 +290,6 @@ MF.setAlignment(YamlMF.Alignment); MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice); MF.setHasInlineAsm(YamlMF.HasInlineAsm); - if (YamlMF.AllVRegsAllocated) - MF.getProperties().set(MachineFunctionProperties::Property::AllVRegsAllocated); PerFunctionMIParsingState PFS(MF, SM, IRSlots); if (initializeRegisterInfo(PFS, YamlMF)) return true; Index: lib/CodeGen/MIRPrinter.cpp =================================================================== --- lib/CodeGen/MIRPrinter.cpp +++ lib/CodeGen/MIRPrinter.cpp @@ -173,8 +173,6 @@ YamlMF.Alignment = MF.getAlignment(); YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice(); YamlMF.HasInlineAsm = MF.hasInlineAsm(); - YamlMF.AllVRegsAllocated = MF.getProperties().hasProperty( - MachineFunctionProperties::Property::AllVRegsAllocated); convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo()); ModuleSlotTracker MST(MF.getFunction()->getParent()); Index: lib/CodeGen/MachineCopyPropagation.cpp =================================================================== --- lib/CodeGen/MachineCopyPropagation.cpp +++ lib/CodeGen/MachineCopyPropagation.cpp @@ -54,11 +54,6 @@ bool runOnMachineFunction(MachineFunction &MF) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - private: void ClobberRegister(unsigned Reg); void CopyPropagateBlock(MachineBasicBlock &MBB); @@ -354,6 +349,7 @@ } bool MachineCopyPropagation::runOnMachineFunction(MachineFunction &MF) { + assert(!MF.hasVirtRegs() && "Registers Allocated"); if (skipFunction(*MF.getFunction())) return false; Index: lib/CodeGen/MachineFunction.cpp =================================================================== --- lib/CodeGen/MachineFunction.cpp +++ lib/CodeGen/MachineFunction.cpp @@ -68,9 +68,6 @@ case Property::TracksLiveness: ROS << (HasProperty ? "" : "not ") << "tracking liveness, "; break; - case Property::AllVRegsAllocated: - ROS << (HasProperty ? "AllVRegsAllocated" : "HasVRegs"); - break; default: break; } @@ -404,6 +401,10 @@ return getFunction()->getName(); } +bool MachineFunction::hasVirtRegs() const { + return getRegInfo().getNumVirtRegs() > 0; +} + void MachineFunction::print(raw_ostream &OS, const SlotIndexes *Indexes) const { OS << "# Machine code for function " << getName() << ": "; OS << "Properties: <"; Index: lib/CodeGen/MachineVerifier.cpp =================================================================== --- lib/CodeGen/MachineVerifier.cpp +++ lib/CodeGen/MachineVerifier.cpp @@ -251,7 +251,6 @@ void verifyStackFrame(); void verifySlotIndexes() const; - void verifyProperties(const MachineFunction &MF); }; struct MachineVerifierPass : public MachineFunctionPass { @@ -308,19 +307,6 @@ } } -void MachineVerifier::verifyProperties(const MachineFunction &MF) { - // If a pass has introduced virtual registers without clearing the - // AllVRegsAllocated property (or set it without allocating the vregs) - // then report an error. - if (MF.getProperties().hasProperty( - MachineFunctionProperties::Property::AllVRegsAllocated) && - MRI->getNumVirtRegs()) { - report( - "Function has AllVRegsAllocated property but there are VReg operands", - &MF); - } -} - unsigned MachineVerifier::verify(MachineFunction &MF) { foundErrors = 0; @@ -345,8 +331,6 @@ verifySlotIndexes(); - verifyProperties(MF); - visitMachineFunctionBefore(); for (MachineFunction::const_iterator MFI = MF.begin(), MFE = MF.end(); MFI!=MFE; ++MFI) { Index: lib/CodeGen/PatchableFunction.cpp =================================================================== --- lib/CodeGen/PatchableFunction.cpp +++ lib/CodeGen/PatchableFunction.cpp @@ -30,10 +30,6 @@ } bool runOnMachineFunction(MachineFunction &F) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } }; } @@ -54,6 +50,7 @@ } bool PatchableFunction::runOnMachineFunction(MachineFunction &MF) { + assert(!MF.hasVirtRegs() && "Registers Allocated"); if (!MF.getFunction()->hasFnAttribute("patchable-function")) return false; Index: lib/CodeGen/PostRASchedulerList.cpp =================================================================== --- lib/CodeGen/PostRASchedulerList.cpp +++ lib/CodeGen/PostRASchedulerList.cpp @@ -96,11 +96,6 @@ MachineFunctionPass::getAnalysisUsage(AU); } - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - bool runOnMachineFunction(MachineFunction &Fn) override; private: @@ -280,6 +275,7 @@ } bool PostRAScheduler::runOnMachineFunction(MachineFunction &Fn) { + assert(!Fn.hasVirtRegs() && "Registers Allocated"); if (skipFunction(*Fn.getFunction())) return false; Index: lib/CodeGen/PrologEpilogInserter.cpp =================================================================== --- lib/CodeGen/PrologEpilogInserter.cpp +++ lib/CodeGen/PrologEpilogInserter.cpp @@ -77,13 +77,6 @@ void getAnalysisUsage(AnalysisUsage &AU) const override; - MachineFunctionProperties getRequiredProperties() const override { - MachineFunctionProperties MFP; - if (UsesCalleeSaves) - MFP.set(MachineFunctionProperties::Property::AllVRegsAllocated); - return MFP; - } - /// runOnMachineFunction - Insert prolog/epilog code and replace abstract /// frame indexes with appropriate references. /// @@ -170,6 +163,7 @@ /// frame indexes with appropriate references. /// bool PEI::runOnMachineFunction(MachineFunction &Fn) { + assert(!UsesCalleeSaves || !Fn.hasVirtRegs() && "Registers Allocated"); const Function* F = Fn.getFunction(); const TargetRegisterInfo *TRI = Fn.getSubtarget().getRegisterInfo(); const TargetFrameLowering *TFI = Fn.getSubtarget().getFrameLowering(); Index: lib/CodeGen/RegAllocFast.cpp =================================================================== --- lib/CodeGen/RegAllocFast.cpp +++ lib/CodeGen/RegAllocFast.cpp @@ -158,11 +158,6 @@ MachineFunctionPass::getAnalysisUsage(AU); } - MachineFunctionProperties getSetProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - private: bool runOnMachineFunction(MachineFunction &Fn) override; void AllocateBasicBlock(); Index: lib/CodeGen/StackMapLivenessAnalysis.cpp =================================================================== --- lib/CodeGen/StackMapLivenessAnalysis.cpp +++ lib/CodeGen/StackMapLivenessAnalysis.cpp @@ -62,11 +62,6 @@ /// information we preserve. void getAnalysisUsage(AnalysisUsage &AU) const override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - /// \brief Calculate the liveness information for the given machine function. bool runOnMachineFunction(MachineFunction &MF) override; @@ -104,6 +99,7 @@ /// Calculate the liveness information for the given machine function. bool StackMapLiveness::runOnMachineFunction(MachineFunction &MF) { + assert(!MF.hasVirtRegs() && "Registers Allocated"); if (!EnablePatchPointLiveness) return false; Index: lib/CodeGen/VirtRegMap.cpp =================================================================== --- lib/CodeGen/VirtRegMap.cpp +++ lib/CodeGen/VirtRegMap.cpp @@ -175,10 +175,6 @@ void getAnalysisUsage(AnalysisUsage &AU) const override; bool runOnMachineFunction(MachineFunction&) override; - MachineFunctionProperties getSetProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } }; } // end anonymous namespace Index: lib/Target/AArch64/AArch64A53Fix835769.cpp =================================================================== --- lib/Target/AArch64/AArch64A53Fix835769.cpp +++ lib/Target/AArch64/AArch64A53Fix835769.cpp @@ -86,11 +86,6 @@ bool runOnMachineFunction(MachineFunction &F) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - const char *getPassName() const override { return "Workaround A53 erratum 835769 pass"; } @@ -111,6 +106,7 @@ bool AArch64A53Fix835769::runOnMachineFunction(MachineFunction &F) { + assert(!F.hasVirtRegs() && "Registers Allocated"); DEBUG(dbgs() << "***** AArch64A53Fix835769 *****\n"); bool Changed = false; TII = F.getSubtarget().getInstrInfo(); Index: lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp =================================================================== --- lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp +++ lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp @@ -124,11 +124,6 @@ bool runOnMachineFunction(MachineFunction &F) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - const char *getPassName() const override { return "A57 FP Anti-dependency breaker"; } @@ -312,6 +307,7 @@ //===----------------------------------------------------------------------===// bool AArch64A57FPLoadBalancing::runOnMachineFunction(MachineFunction &F) { + assert(!F.hasVirtRegs() && "Registers Allocated"); if (skipFunction(*F.getFunction())) return false; Index: lib/Target/AArch64/AArch64CollectLOH.cpp =================================================================== --- lib/Target/AArch64/AArch64CollectLOH.cpp +++ lib/Target/AArch64/AArch64CollectLOH.cpp @@ -179,11 +179,6 @@ bool runOnMachineFunction(MachineFunction &MF) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - const char *getPassName() const override { return AARCH64_COLLECT_LOH_NAME; } @@ -1034,6 +1029,7 @@ } bool AArch64CollectLOH::runOnMachineFunction(MachineFunction &MF) { + assert(!MF.hasVirtRegs() && "Registers Allocated"); if (skipFunction(*MF.getFunction())) return false; Index: lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp =================================================================== --- lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp +++ lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp @@ -48,11 +48,6 @@ bool runOnMachineFunction(MachineFunction &F) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - const char *getPassName() const override { return AARCH64_DEAD_REG_DEF_NAME; } void getAnalysisUsage(AnalysisUsage &AU) const override { @@ -145,6 +140,7 @@ // Scan the function for instructions that have a dead definition of a // register. Replace that register with the zero register when possible. bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) { + assert(!MF.hasVirtRegs() && "Registers Allocated"); TRI = MF.getSubtarget().getRegisterInfo(); bool Changed = false; DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n"); Index: lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp =================================================================== --- lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp +++ lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp @@ -160,11 +160,6 @@ bool runOnMachineFunction(MachineFunction &Fn) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - const char *getPassName() const override { return AARCH64_LOAD_STORE_OPT_NAME; } @@ -1908,6 +1903,7 @@ } bool AArch64LoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) { + assert(!Fn.hasVirtRegs() && "Registers Allocated"); if (skipFunction(*Fn.getFunction())) return false; Index: lib/Target/AArch64/AArch64RedundantCopyElimination.cpp =================================================================== --- lib/Target/AArch64/AArch64RedundantCopyElimination.cpp +++ lib/Target/AArch64/AArch64RedundantCopyElimination.cpp @@ -53,10 +53,6 @@ AArch64RedundantCopyElimination() : MachineFunctionPass(ID) {} bool optimizeCopy(MachineBasicBlock *MBB); bool runOnMachineFunction(MachineFunction &MF) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } const char *getPassName() const override { return "AArch64 Redundant Copy Elimination"; } @@ -167,6 +163,7 @@ bool AArch64RedundantCopyElimination::runOnMachineFunction( MachineFunction &MF) { + assert(!MF.hasVirtRegs() && "Registers Allocated"); if (skipFunction(*MF.getFunction())) return false; TRI = MF.getSubtarget().getRegisterInfo(); Index: lib/Target/ARM/ARMConstantIslandPass.cpp =================================================================== --- lib/Target/ARM/ARMConstantIslandPass.cpp +++ lib/Target/ARM/ARMConstantIslandPass.cpp @@ -195,11 +195,6 @@ bool runOnMachineFunction(MachineFunction &MF) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - const char *getPassName() const override { return "ARM constant island placement and branch shortening pass"; } @@ -311,6 +306,7 @@ } bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) { + assert(!mf.hasVirtRegs() && "Registers Allocated"); MF = &mf; MCP = mf.getConstantPool(); Index: lib/Target/ARM/ARMExpandPseudoInsts.cpp =================================================================== --- lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -51,11 +51,6 @@ bool runOnMachineFunction(MachineFunction &Fn) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - const char *getPassName() const override { return "ARM pseudo instruction expansion pass"; } @@ -1665,6 +1660,7 @@ } bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) { + assert(!MF.hasVirtRegs() && "Registers Allocated"); STI = &static_cast(MF.getSubtarget()); TII = STI->getInstrInfo(); TRI = STI->getRegisterInfo(); Index: lib/Target/ARM/ARMLoadStoreOptimizer.cpp =================================================================== --- lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -93,11 +93,6 @@ bool runOnMachineFunction(MachineFunction &Fn) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - const char *getPassName() const override { return ARM_LOAD_STORE_OPT_NAME; } @@ -1905,6 +1900,7 @@ } bool ARMLoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) { + assert(!Fn.hasVirtRegs() && "Registers Allocated"); if (skipFunction(*Fn.getFunction())) return false; Index: lib/Target/ARM/ARMOptimizeBarriersPass.cpp =================================================================== --- lib/Target/ARM/ARMOptimizeBarriersPass.cpp +++ lib/Target/ARM/ARMOptimizeBarriersPass.cpp @@ -27,11 +27,6 @@ bool runOnMachineFunction(MachineFunction &Fn) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - const char *getPassName() const override { return "optimise barriers pass"; } @@ -51,6 +46,7 @@ } bool ARMOptimizeBarriersPass::runOnMachineFunction(MachineFunction &MF) { + assert(!MF.hasVirtRegs() && "Registers Allocated"); if (skipFunction(*MF.getFunction())) return false; Index: lib/Target/ARM/Thumb2ITBlockPass.cpp =================================================================== --- lib/Target/ARM/Thumb2ITBlockPass.cpp +++ lib/Target/ARM/Thumb2ITBlockPass.cpp @@ -36,11 +36,6 @@ bool runOnMachineFunction(MachineFunction &Fn) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - const char *getPassName() const override { return "Thumb IT blocks insertion pass"; } @@ -272,6 +267,7 @@ } bool Thumb2ITBlockPass::runOnMachineFunction(MachineFunction &Fn) { + assert(!Fn.hasVirtRegs() && "Registers Allocated"); const ARMSubtarget &STI = static_cast(Fn.getSubtarget()); if (!STI.isThumb2()) Index: lib/Target/ARM/Thumb2SizeReduction.cpp =================================================================== --- lib/Target/ARM/Thumb2SizeReduction.cpp +++ lib/Target/ARM/Thumb2SizeReduction.cpp @@ -146,11 +146,6 @@ bool runOnMachineFunction(MachineFunction &MF) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - const char *getPassName() const override { return "Thumb2 instruction size reduction pass"; } @@ -1068,6 +1063,7 @@ } bool Thumb2SizeReduce::runOnMachineFunction(MachineFunction &MF) { + assert(!MF.hasVirtRegs() && "Registers Allocated"); if (PredicateFtor && !PredicateFtor(*MF.getFunction())) return false; Index: lib/Target/Hexagon/HexagonCFGOptimizer.cpp =================================================================== --- lib/Target/Hexagon/HexagonCFGOptimizer.cpp +++ lib/Target/Hexagon/HexagonCFGOptimizer.cpp @@ -49,10 +49,6 @@ return "Hexagon CFG Optimizer"; } bool runOnMachineFunction(MachineFunction &Fn) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } }; @@ -100,6 +96,7 @@ bool HexagonCFGOptimizer::runOnMachineFunction(MachineFunction &Fn) { + assert(!Fn.hasVirtRegs() && "Registers Allocated"); if (skipFunction(*Fn.getFunction())) return false; Index: lib/Target/Hexagon/HexagonCopyToCombine.cpp =================================================================== --- lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -86,11 +86,6 @@ bool runOnMachineFunction(MachineFunction &Fn) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - private: MachineInstr *findPairable(MachineInstr &I1, bool &DoInsertAtI1, bool AllowC64); @@ -440,6 +435,7 @@ } bool HexagonCopyToCombine::runOnMachineFunction(MachineFunction &MF) { + assert(!MF.hasVirtRegs() && "Registers Allocated"); if (IsCombinesDisabled) return false; Index: lib/Target/Hexagon/HexagonFixupHwLoops.cpp =================================================================== --- lib/Target/Hexagon/HexagonFixupHwLoops.cpp +++ lib/Target/Hexagon/HexagonFixupHwLoops.cpp @@ -45,11 +45,6 @@ bool runOnMachineFunction(MachineFunction &MF) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - const char *getPassName() const override { return "Hexagon Hardware Loop Fixup"; } @@ -90,6 +85,7 @@ } bool HexagonFixupHwLoops::runOnMachineFunction(MachineFunction &MF) { + assert(!MF.hasVirtRegs() && "Registers Allocated"); if (skipFunction(*MF.getFunction())) return false; return fixupLoopInstrs(MF); Index: lib/Target/Hexagon/HexagonFrameLowering.cpp =================================================================== --- lib/Target/Hexagon/HexagonFrameLowering.cpp +++ lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -170,16 +170,13 @@ initializeHexagonCallFrameInformationPass(PR); } bool runOnMachineFunction(MachineFunction &MF) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } }; char HexagonCallFrameInformation::ID = 0; } bool HexagonCallFrameInformation::runOnMachineFunction(MachineFunction &MF) { + assert(!MF.hasVirtRegs() && "Registers Allocated"); auto &HFI = *MF.getSubtarget().getFrameLowering(); bool NeedCFI = MF.getMMI().hasDebugInfo() || MF.getFunction()->needsUnwindTableEntry(); Index: lib/Target/Hexagon/HexagonGenMux.cpp =================================================================== --- lib/Target/Hexagon/HexagonGenMux.cpp +++ lib/Target/Hexagon/HexagonGenMux.cpp @@ -49,10 +49,6 @@ MachineFunctionPass::getAnalysisUsage(AU); } bool runOnMachineFunction(MachineFunction &MF) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } private: const HexagonInstrInfo *HII; @@ -309,6 +305,7 @@ } bool HexagonGenMux::runOnMachineFunction(MachineFunction &MF) { + assert(!MF.hasVirtRegs() && "Registers Allocated"); if (skipFunction(*MF.getFunction())) return false; HII = MF.getSubtarget().getInstrInfo(); Index: lib/Target/Hexagon/HexagonNewValueJump.cpp =================================================================== --- lib/Target/Hexagon/HexagonNewValueJump.cpp +++ lib/Target/Hexagon/HexagonNewValueJump.cpp @@ -84,10 +84,6 @@ } bool runOnMachineFunction(MachineFunction &Fn) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } private: /// \brief A handle to the branch probability pass. @@ -388,6 +384,7 @@ bool HexagonNewValueJump::runOnMachineFunction(MachineFunction &MF) { + assert(!MF.hasVirtRegs() && "Regisers Allocated"); DEBUG(dbgs() << "********** Hexagon New Value Jump **********\n" << "********** Function: " Index: lib/Target/Hexagon/HexagonRDFOpt.cpp =================================================================== --- lib/Target/Hexagon/HexagonRDFOpt.cpp +++ lib/Target/Hexagon/HexagonRDFOpt.cpp @@ -55,11 +55,6 @@ } bool runOnMachineFunction(MachineFunction &MF) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - static char ID; private: @@ -267,6 +262,7 @@ bool HexagonRDFOpt::runOnMachineFunction(MachineFunction &MF) { + assert(!MF.hasVirtRegs() && "Registers Allocated"); if (skipFunction(*MF.getFunction())) return false; Index: lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp =================================================================== --- lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp +++ lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp @@ -57,10 +57,6 @@ return "Hexagon Split Const32s and Const64s"; } bool runOnMachineFunction(MachineFunction &Fn) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } }; @@ -68,6 +64,7 @@ bool HexagonSplitConst32AndConst64::runOnMachineFunction(MachineFunction &Fn) { + assert(!Fn.hasVirtRegs() && "Registers Allocated"); const HexagonTargetObjectFile &TLOF = *static_cast( Index: lib/Target/Hexagon/HexagonVLIWPacketizer.cpp =================================================================== --- lib/Target/Hexagon/HexagonVLIWPacketizer.cpp +++ lib/Target/Hexagon/HexagonVLIWPacketizer.cpp @@ -79,10 +79,6 @@ return "Hexagon Packetizer"; } bool runOnMachineFunction(MachineFunction &Fn) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } private: const HexagonInstrInfo *HII; @@ -173,6 +169,7 @@ bool HexagonPacketizer::runOnMachineFunction(MachineFunction &MF) { + assert(!MF.hasVirtRegs() && "Registers Allocated"); if (DisablePacketizer || skipFunction(*MF.getFunction())) return false; Index: lib/Target/Lanai/LanaiDelaySlotFiller.cpp =================================================================== --- lib/Target/Lanai/LanaiDelaySlotFiller.cpp +++ lib/Target/Lanai/LanaiDelaySlotFiller.cpp @@ -47,6 +47,7 @@ bool runOnMachineBasicBlock(MachineBasicBlock &MBB); bool runOnMachineFunction(MachineFunction &MF) override { + assert(!MF.hasVirtRegs() && "Registers Allocated"); const LanaiSubtarget &Subtarget = MF.getSubtarget(); TII = Subtarget.getInstrInfo(); TRI = Subtarget.getRegisterInfo(); @@ -58,11 +59,6 @@ return Changed; } - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - void insertDefsUses(MachineBasicBlock::instr_iterator MI, SmallSet &RegDefs, SmallSet &RegUses); Index: lib/Target/Lanai/LanaiMemAluCombiner.cpp =================================================================== --- lib/Target/Lanai/LanaiMemAluCombiner.cpp +++ lib/Target/Lanai/LanaiMemAluCombiner.cpp @@ -67,11 +67,6 @@ bool runOnMachineFunction(MachineFunction &F) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - private: MbbIterator findClosestSuitableAluInstr(MachineBasicBlock *BB, const MbbIterator &MemInstr, @@ -405,6 +400,7 @@ // Driver function that iterates over the machine basic building blocks of a // machine function bool LanaiMemAluCombiner::runOnMachineFunction(MachineFunction &MF) { + assert(!MF.hasVirtRegs() && "Registers Allocated"); if (DisableMemAluCombiner) return false; Index: lib/Target/MSP430/MSP430BranchSelector.cpp =================================================================== --- lib/Target/MSP430/MSP430BranchSelector.cpp +++ lib/Target/MSP430/MSP430BranchSelector.cpp @@ -39,11 +39,6 @@ bool runOnMachineFunction(MachineFunction &Fn) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - const char *getPassName() const override { return "MSP430 Branch Selector"; } @@ -59,6 +54,7 @@ } bool MSP430BSel::runOnMachineFunction(MachineFunction &Fn) { + assert(!Fn.hasVirtRegs() && "Registers Allocated"); const MSP430InstrInfo *TII = static_cast(Fn.getSubtarget().getInstrInfo()); // Give the blocks of the function a dense, in-order, numbering. Index: lib/Target/Mips/MipsConstantIslandPass.cpp =================================================================== --- lib/Target/Mips/MipsConstantIslandPass.cpp +++ lib/Target/Mips/MipsConstantIslandPass.cpp @@ -362,11 +362,6 @@ bool runOnMachineFunction(MachineFunction &F) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - void doInitialPlacement(std::vector &CPEMIs); CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI); unsigned getCPELogAlign(const MachineInstr &CPEMI); @@ -435,6 +430,7 @@ } bool MipsConstantIslands::runOnMachineFunction(MachineFunction &mf) { + assert(!mf.hasVirtRegs() && "Registers Allocated"); // The intention is for this to be a mips16 only pass for now // FIXME: MF = &mf; Index: lib/Target/Mips/MipsDelaySlotFiller.cpp =================================================================== --- lib/Target/Mips/MipsDelaySlotFiller.cpp +++ lib/Target/Mips/MipsDelaySlotFiller.cpp @@ -197,6 +197,7 @@ } bool runOnMachineFunction(MachineFunction &F) override { + assert(!F.hasVirtRegs() && "Registers Allocated"); bool Changed = false; for (MachineFunction::iterator FI = F.begin(), FE = F.end(); FI != FE; ++FI) @@ -211,11 +212,6 @@ return Changed; } - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - void getAnalysisUsage(AnalysisUsage &AU) const override { AU.addRequired(); MachineFunctionPass::getAnalysisUsage(AU); Index: lib/Target/Mips/MipsHazardSchedule.cpp =================================================================== --- lib/Target/Mips/MipsHazardSchedule.cpp +++ lib/Target/Mips/MipsHazardSchedule.cpp @@ -74,11 +74,6 @@ bool runOnMachineFunction(MachineFunction &F) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - private: static char ID; }; @@ -100,7 +95,7 @@ } bool MipsHazardSchedule::runOnMachineFunction(MachineFunction &MF) { - + assert(!MF.hasVirtRegs() && "Registers Allocated"); const MipsSubtarget *STI = &static_cast(MF.getSubtarget()); Index: lib/Target/Mips/MipsLongBranch.cpp =================================================================== --- lib/Target/Mips/MipsLongBranch.cpp +++ lib/Target/Mips/MipsLongBranch.cpp @@ -72,11 +72,6 @@ bool runOnMachineFunction(MachineFunction &F) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - private: void splitMBB(MachineBasicBlock *MBB); void initMBBInfo(); @@ -459,6 +454,7 @@ } bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) { + assert(!F.hasVirtRegs() && "Registers Allocated"); const MipsSubtarget &STI = static_cast(F.getSubtarget()); const MipsInstrInfo *TII = Index: lib/Target/PowerPC/PPCBranchSelector.cpp =================================================================== --- lib/Target/PowerPC/PPCBranchSelector.cpp +++ lib/Target/PowerPC/PPCBranchSelector.cpp @@ -46,11 +46,6 @@ bool runOnMachineFunction(MachineFunction &Fn) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - const char *getPassName() const override { return "PowerPC Branch Selector"; } @@ -69,6 +64,7 @@ } bool PPCBSel::runOnMachineFunction(MachineFunction &Fn) { + assert(!Fn.hasVirtRegs() && "Registers Allocated"); const PPCInstrInfo *TII = static_cast(Fn.getSubtarget().getInstrInfo()); // Give the blocks of the function a dense, in-order, numbering. Index: lib/Target/PowerPC/PPCEarlyReturn.cpp =================================================================== --- lib/Target/PowerPC/PPCEarlyReturn.cpp +++ lib/Target/PowerPC/PPCEarlyReturn.cpp @@ -173,6 +173,7 @@ public: bool runOnMachineFunction(MachineFunction &MF) override { + assert(!MF.hasVirtRegs() && "Registers Allocated"); if (skipFunction(*MF.getFunction())) return false; @@ -194,11 +195,6 @@ return Changed; } - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - void getAnalysisUsage(AnalysisUsage &AU) const override { MachineFunctionPass::getAnalysisUsage(AU); } Index: lib/Target/Sparc/DelaySlotFiller.cpp =================================================================== --- lib/Target/Sparc/DelaySlotFiller.cpp +++ lib/Target/Sparc/DelaySlotFiller.cpp @@ -49,6 +49,7 @@ bool runOnMachineBasicBlock(MachineBasicBlock &MBB); bool runOnMachineFunction(MachineFunction &F) override { + assert(!F.hasVirtRegs() && "Registers Allocated"); bool Changed = false; Subtarget = &F.getSubtarget(); @@ -62,11 +63,6 @@ return Changed; } - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - void insertCallDefsUses(MachineBasicBlock::iterator MI, SmallSet& RegDefs, SmallSet& RegUses); Index: lib/Target/SystemZ/SystemZElimCompare.cpp =================================================================== --- lib/Target/SystemZ/SystemZElimCompare.cpp +++ lib/Target/SystemZ/SystemZElimCompare.cpp @@ -64,10 +64,6 @@ bool processBlock(MachineBasicBlock &MBB); bool runOnMachineFunction(MachineFunction &F) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } private: Reference getRegReferences(MachineInstr &MI, unsigned Reg); @@ -497,6 +493,7 @@ } bool SystemZElimCompare::runOnMachineFunction(MachineFunction &F) { + assert(!F.hasVirtRegs() && "Registers Allocated"); if (skipFunction(*F.getFunction())) return false; Index: lib/Target/SystemZ/SystemZLongBranch.cpp =================================================================== --- lib/Target/SystemZ/SystemZLongBranch.cpp +++ lib/Target/SystemZ/SystemZLongBranch.cpp @@ -138,10 +138,6 @@ } bool runOnMachineFunction(MachineFunction &F) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } private: void skipNonTerminators(BlockPosition &Position, MBBInfo &Block); @@ -451,6 +447,7 @@ } bool SystemZLongBranch::runOnMachineFunction(MachineFunction &F) { + assert(!F.hasVirtRegs() && "Registers Allocated"); TII = static_cast(F.getSubtarget().getInstrInfo()); MF = &F; uint64_t Size = initMBBInfo(); Index: lib/Target/SystemZ/SystemZShortenInst.cpp =================================================================== --- lib/Target/SystemZ/SystemZShortenInst.cpp +++ lib/Target/SystemZ/SystemZShortenInst.cpp @@ -35,10 +35,6 @@ bool processBlock(MachineBasicBlock &MBB); bool runOnMachineFunction(MachineFunction &F) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } private: bool shortenIIF(MachineInstr &MI, unsigned LLIxL, unsigned LLIxH); @@ -269,6 +265,7 @@ } bool SystemZShortenInst::runOnMachineFunction(MachineFunction &F) { + assert(!F.hasVirtRegs() && "Registers Allocated"); if (skipFunction(*F.getFunction())) return false; Index: lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp =================================================================== --- lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp +++ lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp @@ -175,7 +175,7 @@ // Has no asserts of its own, but was not written to handle virtual regs. disablePass(&ShrinkWrapID); - // These functions all require the AllVRegsAllocated property. + // These passes do not support virtual registers. disablePass(&MachineCopyPropagationID); disablePass(&PostRASchedulerID); disablePass(&FuncletLayoutID); Index: lib/Target/X86/X86ExpandPseudo.cpp =================================================================== --- lib/Target/X86/X86ExpandPseudo.cpp +++ lib/Target/X86/X86ExpandPseudo.cpp @@ -49,11 +49,6 @@ bool runOnMachineFunction(MachineFunction &Fn) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - const char *getPassName() const override { return "X86 pseudo instruction expansion pass"; } @@ -252,6 +247,7 @@ } bool X86ExpandPseudo::runOnMachineFunction(MachineFunction &MF) { + assert(!MF.hasVirtRegs() && "Registers Allocated"); STI = &static_cast(MF.getSubtarget()); TII = STI->getInstrInfo(); TRI = STI->getRegisterInfo(); Index: lib/Target/X86/X86FixupBWInsts.cpp =================================================================== --- lib/Target/X86/X86FixupBWInsts.cpp +++ lib/Target/X86/X86FixupBWInsts.cpp @@ -123,11 +123,6 @@ /// improved. bool runOnMachineFunction(MachineFunction &MF) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - private: MachineFunction *MF; @@ -151,6 +146,7 @@ FunctionPass *llvm::createX86FixupBWInsts() { return new FixupBWInstPass(); } bool FixupBWInstPass::runOnMachineFunction(MachineFunction &MF) { + assert(!MF.hasVirtRegs() && "Registers Allocated"); if (!FixupBWInsts || skipFunction(*MF.getFunction())) return false; Index: lib/Target/X86/X86FixupLEAs.cpp =================================================================== --- lib/Target/X86/X86FixupLEAs.cpp +++ lib/Target/X86/X86FixupLEAs.cpp @@ -92,12 +92,6 @@ /// if needed and when possible. bool runOnMachineFunction(MachineFunction &MF) override; - // This pass runs after regalloc and doesn't support VReg operands. - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - private: MachineFunction *MF; const X86InstrInfo *TII; // Machine instruction info. @@ -162,6 +156,7 @@ FunctionPass *llvm::createX86FixupLEAs() { return new FixupLEAPass(); } bool FixupLEAPass::runOnMachineFunction(MachineFunction &Func) { + assert(!Func.hasVirtRegs() && "Registers Allocated"); if (skipFunction(*Func.getFunction())) return false; Index: lib/Target/X86/X86FloatingPoint.cpp =================================================================== --- lib/Target/X86/X86FloatingPoint.cpp +++ lib/Target/X86/X86FloatingPoint.cpp @@ -76,11 +76,6 @@ bool runOnMachineFunction(MachineFunction &MF) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - const char *getPassName() const override { return "X86 FP Stackifier"; } private: @@ -301,6 +296,7 @@ /// register references into FP stack references. /// bool FPS::runOnMachineFunction(MachineFunction &MF) { + assert(!MF.hasVirtRegs() && "Registers Allocated"); // We only need to run this pass if there are any FP registers used in this // function. If it is all integer, there is nothing for us to do! bool FPIsUsed = false; Index: lib/Target/X86/X86PadShortFunction.cpp =================================================================== --- lib/Target/X86/X86PadShortFunction.cpp +++ lib/Target/X86/X86PadShortFunction.cpp @@ -55,11 +55,6 @@ bool runOnMachineFunction(MachineFunction &MF) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } - const char *getPassName() const override { return "X86 Atom pad short functions"; } @@ -98,6 +93,7 @@ /// runOnMachineFunction - Loop over all of the basic blocks, inserting /// NOOP instructions before early exits. bool PadShortFunc::runOnMachineFunction(MachineFunction &MF) { + assert(!MF.hasVirtRegs() && "Registers Allocated"); if (skipFunction(*MF.getFunction())) return false; Index: lib/Target/X86/X86VZeroUpper.cpp =================================================================== --- lib/Target/X86/X86VZeroUpper.cpp +++ lib/Target/X86/X86VZeroUpper.cpp @@ -38,10 +38,6 @@ VZeroUpperInserter() : MachineFunctionPass(ID) {} bool runOnMachineFunction(MachineFunction &MF) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } const char *getPassName() const override {return "X86 vzeroupper inserter";} private: @@ -256,6 +252,7 @@ /// Loop over all of the basic blocks, inserting vzeroupper instructions before /// function calls. bool VZeroUpperInserter::runOnMachineFunction(MachineFunction &MF) { + assert(!MF.hasVirtRegs() && "Registers Allocated"); const X86Subtarget &ST = MF.getSubtarget(); if (!ST.hasAVX() || ST.hasAVX512() || ST.hasFastPartialYMMWrite()) return false; Index: lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp =================================================================== --- lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp +++ lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp @@ -27,10 +27,6 @@ XCoreFTAOElim() : MachineFunctionPass(ID) {} bool runOnMachineFunction(MachineFunction &Fn) override; - MachineFunctionProperties getRequiredProperties() const override { - return MachineFunctionProperties().set( - MachineFunctionProperties::Property::AllVRegsAllocated); - } const char *getPassName() const override { return "XCore FRAME_TO_ARGS_OFFSET Elimination"; @@ -46,6 +42,7 @@ } bool XCoreFTAOElim::runOnMachineFunction(MachineFunction &MF) { + assert(!MF.hasVirtRegs() && "Registers Allocated"); const XCoreInstrInfo &TII = *static_cast(MF.getSubtarget().getInstrInfo()); unsigned StackSize = MF.getFrameInfo()->getStackSize(); Index: test/CodeGen/AArch64/movimm-wzr.mir =================================================================== --- test/CodeGen/AArch64/movimm-wzr.mir +++ test/CodeGen/AArch64/movimm-wzr.mir @@ -16,7 +16,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: true isSSA: false tracksRegLiveness: false tracksSubRegLiveness: false Index: test/CodeGen/ARM/ARMLoadStoreDBG.mir =================================================================== --- test/CodeGen/ARM/ARMLoadStoreDBG.mir +++ test/CodeGen/ARM/ARMLoadStoreDBG.mir @@ -80,7 +80,6 @@ alignment: 1 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: true isSSA: false tracksRegLiveness: true tracksSubRegLiveness: false Index: test/CodeGen/MIR/AArch64/machine-dead-copy.mir =================================================================== --- test/CodeGen/MIR/AArch64/machine-dead-copy.mir +++ test/CodeGen/MIR/AArch64/machine-dead-copy.mir @@ -14,7 +14,6 @@ # CHECK: bb.0: # CHECK-NOT: %w20 = COPY name: copyprop1 -allVRegsAllocated: true body: | bb.0: liveins: %w0, %w1 @@ -29,7 +28,6 @@ # CHECK: bb.0: # CHECK: %w20 = COPY name: copyprop2 -allVRegsAllocated: true body: | bb.0: liveins: %w0, %w1 @@ -44,7 +42,6 @@ # CHECK: bb.0: # CHECK-NOT: COPY name: copyprop3 -allVRegsAllocated: true body: | bb.0: liveins: %w0, %w1 @@ -59,7 +56,6 @@ # CHECK: bb.0: # CHECK-NOT: COPY name: copyprop4 -allVRegsAllocated: true body: | bb.0: liveins: %w0, %w1 Index: test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir =================================================================== --- test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir +++ test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir @@ -91,7 +91,6 @@ alignment: 1 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: true isSSA: false tracksRegLiveness: true tracksSubRegLiveness: false Index: test/CodeGen/MIR/Hexagon/anti-dep-partial.mir =================================================================== --- test/CodeGen/MIR/Hexagon/anti-dep-partial.mir +++ test/CodeGen/MIR/Hexagon/anti-dep-partial.mir @@ -10,7 +10,6 @@ --- name: foo tracksRegLiveness: true -allVRegsAllocated: true body: | bb.0: successors: Index: test/CodeGen/MIR/Lanai/peephole-compare.mir =================================================================== --- test/CodeGen/MIR/Lanai/peephole-compare.mir +++ test/CodeGen/MIR/Lanai/peephole-compare.mir @@ -176,7 +176,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: false isSSA: true tracksRegLiveness: true tracksSubRegLiveness: false @@ -224,7 +223,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: false isSSA: true tracksRegLiveness: true tracksSubRegLiveness: false @@ -270,7 +268,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: false isSSA: true tracksRegLiveness: true tracksSubRegLiveness: false @@ -320,7 +317,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: false isSSA: true tracksRegLiveness: true tracksSubRegLiveness: false @@ -370,7 +366,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: false isSSA: true tracksRegLiveness: true tracksSubRegLiveness: false @@ -420,7 +415,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: false isSSA: true tracksRegLiveness: true tracksSubRegLiveness: false @@ -470,7 +464,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: false isSSA: true tracksRegLiveness: true tracksSubRegLiveness: false @@ -520,7 +513,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: false isSSA: true tracksRegLiveness: true tracksSubRegLiveness: false @@ -634,7 +626,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: false isSSA: true tracksRegLiveness: true tracksSubRegLiveness: false Index: test/CodeGen/PowerPC/aantidep-def-ec.mir =================================================================== --- test/CodeGen/PowerPC/aantidep-def-ec.mir +++ test/CodeGen/PowerPC/aantidep-def-ec.mir @@ -45,7 +45,6 @@ alignment: 4 exposesReturnsTwice: false hasInlineAsm: true -allVRegsAllocated: true isSSA: false tracksRegLiveness: true tracksSubRegLiveness: false Index: test/CodeGen/PowerPC/addisdtprelha-nonr3.mir =================================================================== --- test/CodeGen/PowerPC/addisdtprelha-nonr3.mir +++ test/CodeGen/PowerPC/addisdtprelha-nonr3.mir @@ -27,7 +27,6 @@ alignment: 4 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: true isSSA: false tracksRegLiveness: true tracksSubRegLiveness: false Index: test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir =================================================================== --- test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir +++ test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir @@ -33,7 +33,6 @@ alignment: 2 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: false isSSA: true tracksRegLiveness: true tracksSubRegLiveness: false Index: test/CodeGen/X86/eflags-copy-expansion.mir =================================================================== --- test/CodeGen/X86/eflags-copy-expansion.mir +++ test/CodeGen/X86/eflags-copy-expansion.mir @@ -19,7 +19,6 @@ --- name: foo -allVRegsAllocated: true isSSA: false tracksRegLiveness: true liveins: Index: test/CodeGen/X86/fixup-bw-copy.mir =================================================================== --- test/CodeGen/X86/fixup-bw-copy.mir +++ test/CodeGen/X86/fixup-bw-copy.mir @@ -38,7 +38,6 @@ --- name: test_movb_killed -allVRegsAllocated: true isSSA: false tracksRegLiveness: true liveins: @@ -55,7 +54,6 @@ --- name: test_movb_impuse -allVRegsAllocated: true isSSA: false tracksRegLiveness: true liveins: @@ -72,7 +70,6 @@ --- name: test_movb_impdef_gr64 -allVRegsAllocated: true isSSA: false tracksRegLiveness: true liveins: @@ -89,7 +86,6 @@ --- name: test_movb_impdef_gr32 -allVRegsAllocated: true isSSA: false tracksRegLiveness: true liveins: @@ -106,7 +102,6 @@ --- name: test_movb_impdef_gr16 -allVRegsAllocated: true isSSA: false tracksRegLiveness: true liveins: @@ -123,7 +118,6 @@ --- name: test_movw_impdef_gr32 -allVRegsAllocated: true isSSA: false tracksRegLiveness: true liveins: @@ -140,7 +134,6 @@ --- name: test_movw_impdef_gr64 -allVRegsAllocated: true isSSA: false tracksRegLiveness: true liveins: Index: test/CodeGen/X86/implicit-null-checks.mir =================================================================== --- test/CodeGen/X86/implicit-null-checks.mir +++ test/CodeGen/X86/implicit-null-checks.mir @@ -85,7 +85,6 @@ name: imp_null_check_with_bitwise_op_0 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_0 alignment: 4 -allVRegsAllocated: true tracksRegLiveness: true tracksSubRegLiveness: false liveins: @@ -129,7 +128,6 @@ --- name: imp_null_check_with_bitwise_op_1 alignment: 4 -allVRegsAllocated: true isSSA: false tracksRegLiveness: true tracksSubRegLiveness: false @@ -179,7 +177,6 @@ name: imp_null_check_with_bitwise_op_2 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_2 alignment: 4 -allVRegsAllocated: true tracksRegLiveness: true tracksSubRegLiveness: false liveins: @@ -224,7 +221,6 @@ name: imp_null_check_with_bitwise_op_3 # CHECK-LABEL: name: imp_null_check_with_bitwise_op_3 alignment: 4 -allVRegsAllocated: true tracksRegLiveness: true tracksSubRegLiveness: false liveins: Index: test/CodeGen/X86/machine-copy-prop.mir =================================================================== --- test/CodeGen/X86/machine-copy-prop.mir +++ test/CodeGen/X86/machine-copy-prop.mir @@ -25,7 +25,6 @@ # CHECK-NOT: COPY # CHECK-NEXT: NOOP implicit %rax, implicit %rdi name: copyprop_remove_kill0 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rdi @@ -43,7 +42,6 @@ # CHECK-NOT: COPY # CHECK-NEXT: NOOP implicit %rax, implicit %rdi name: copyprop_remove_kill1 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rdi @@ -61,7 +59,6 @@ # CHECK-NOT: COPY # CHECK-NEXT: NOOP implicit %rax, implicit %rdi name: copyprop_remove_kill2 -allVRegsAllocated: true body: | bb.0: %ax = COPY %di @@ -79,7 +76,6 @@ # CHECK-NOT: COPY # CHECK-NEXT: NOOP implicit %rax, implicit %rdi name: copyprop0 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rdi @@ -96,7 +92,6 @@ # CHECK-NEXT: NOOP implicit %rax # CHECK-NEXT: NOOP implicit %rax, implicit %rdi name: copyprop1 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rdi @@ -113,7 +108,6 @@ # CHECK-NOT: %rax = COPY %rdi # CHECK-NEXT: NOOP implicit %rax, implicit %rdi name: copyprop2 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rdi @@ -132,7 +126,6 @@ # CHECK-NEXT: %rbp = COPY %rax # CHECK-NEXT: NOOP implicit %rax, implicit %rbp name: nocopyprop0 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rbp @@ -150,7 +143,6 @@ # CHECK-NEXT: %rax = COPY %rbp # CHECK-NEXT: NOOP implicit %rax, implicit %rbp name: nocopyprop1 -allVRegsAllocated: true body: | bb.0: %rbp = COPY %rax @@ -168,7 +160,6 @@ # CHECK-NEXT: %rax = COPY %rbp # CHECK-NEXT: NOOP implicit %rax, implicit %rbp name: nocopyprop2 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rbp @@ -186,7 +177,6 @@ # CHECK-NEXT: %rbp = COPY %rax # CHECK-NEXT: NOOP implicit %rax, implicit %rbp name: nocopyprop3 -allVRegsAllocated: true body: | bb.0: %rbp = COPY %rax @@ -203,7 +193,6 @@ # CHECK-NEXT: %rax = COPY %rip # CHECK-NEXT: NOOP implicit %rax name: nocopyprop4 -allVRegsAllocated: true body: | bb.0: %rax = COPY %rip @@ -219,7 +208,6 @@ # CHECK-NEXT: %rip = COPY %rax # CHECK-NEXT: %rip = COPY %rax name: nocopyprop5 -allVRegsAllocated: true body: | bb.0: %rip = COPY %rax Index: test/CodeGen/X86/pr27681.mir =================================================================== --- test/CodeGen/X86/pr27681.mir +++ test/CodeGen/X86/pr27681.mir @@ -11,7 +11,6 @@ --- # CHECK-LABEL: main name: main -allVRegsAllocated: true tracksRegLiveness: true frameInfo: stackSize: 52 Index: test/DebugInfo/MIR/X86/live-debug-values-3preds.mir =================================================================== --- test/DebugInfo/MIR/X86/live-debug-values-3preds.mir +++ test/DebugInfo/MIR/X86/live-debug-values-3preds.mir @@ -158,7 +158,6 @@ alignment: 4 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: true isSSA: false tracksRegLiveness: true tracksSubRegLiveness: false Index: test/DebugInfo/MIR/X86/live-debug-values.mir =================================================================== --- test/DebugInfo/MIR/X86/live-debug-values.mir +++ test/DebugInfo/MIR/X86/live-debug-values.mir @@ -160,7 +160,6 @@ alignment: 4 exposesReturnsTwice: false hasInlineAsm: false -allVRegsAllocated: true isSSA: false tracksRegLiveness: true tracksSubRegLiveness: false