Index: lib/Target/Mips/AsmParser/MipsAsmParser.cpp =================================================================== --- lib/Target/Mips/AsmParser/MipsAsmParser.cpp +++ lib/Target/Mips/AsmParser/MipsAsmParser.cpp @@ -3714,21 +3714,21 @@ // The compact branches that branch iff the signed addition of two registers // would overflow must have rs >= rt. That can be handled like beqc/bnec with // operand swapping. They do not have restriction of using the zero register. - case Mips::BLEZC: - case Mips::BGEZC: - case Mips::BGTZC: - case Mips::BLTZC: - case Mips::BEQZC: - case Mips::BNEZC: + case Mips::BLEZC: case Mips::BLEZC_MMR6: + case Mips::BGEZC: case Mips::BGEZC_MMR6: + case Mips::BGTZC: case Mips::BGTZC_MMR6: + case Mips::BLTZC: case Mips::BLTZC_MMR6: + case Mips::BEQZC: case Mips::BEQZC_MMR6: + case Mips::BNEZC: case Mips::BNEZC_MMR6: if (Inst.getOperand(0).getReg() == Mips::ZERO) return Match_RequiresNoZeroRegister; return Match_Success; - case Mips::BGEC: - case Mips::BLTC: - case Mips::BGEUC: - case Mips::BLTUC: - case Mips::BEQC: - case Mips::BNEC: + case Mips::BGEC: case Mips::BGEC_MMR6: + case Mips::BLTC: case Mips::BLTC_MMR6: + case Mips::BGEUC: case Mips::BGEUC_MMR6: + case Mips::BLTUC: case Mips::BLTUC_MMR6: + case Mips::BEQC: case Mips::BEQC_MMR6: + case Mips::BNEC: case Mips::BNEC_MMR6: if (Inst.getOperand(0).getReg() == Mips::ZERO) return Match_RequiresNoZeroRegister; if (Inst.getOperand(1).getReg() == Mips::ZERO) Index: lib/Target/Mips/Disassembler/MipsDisassembler.cpp =================================================================== --- lib/Target/Mips/Disassembler/MipsDisassembler.cpp +++ lib/Target/Mips/Disassembler/MipsDisassembler.cpp @@ -460,6 +460,16 @@ template static DecodeStatus +DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, + const void *Decoder); + +template +static DecodeStatus +DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, uint64_t Address, + const void *Decoder); + +template +static DecodeStatus DecodeBlezlGroupBranch(MCInst &MI, InsnType insn, uint64_t Address, const void *Decoder); @@ -630,7 +640,7 @@ const void *Decoder) { InsnType Rt = fieldFromInstruction(insn, 21, 5); InsnType Rs = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; + int64_t Imm = 0; if (Rs >= Rt) { MI.setOpcode(Mips::BOVC_MMR6); @@ -638,16 +648,19 @@ Rt))); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; } else if (Rs != 0 && Rs < Rt) { MI.setOpcode(Mips::BEQC_MMR6); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; } else { MI.setOpcode(Mips::BEQZALC_MMR6); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; } MI.addOperand(MCOperand::createImm(Imm)); @@ -700,7 +713,7 @@ const void *Decoder) { InsnType Rt = fieldFromInstruction(insn, 21, 5); InsnType Rs = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; + int64_t Imm = 0; if (Rs >= Rt) { MI.setOpcode(Mips::BNVC_MMR6); @@ -708,18 +721,100 @@ Rt))); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; } else if (Rs != 0 && Rs < Rt) { MI.setOpcode(Mips::BNEC_MMR6); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rs))); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; } else { MI.setOpcode(Mips::BNEZALC_MMR6); MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, Rt))); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; + } + + MI.addOperand(MCOperand::createImm(Imm)); + + return MCDisassembler::Success; +} + +template +static DecodeStatus DecodePOP65GroupBranchMMR6(MCInst &MI, InsnType insn, + uint64_t Address, + const void *Decoder) { + // We have: + // 0b110101 ttttt sssss iiiiiiiiiiiiiiii + // Invalid if rt == 0 + // BGTZC_MMR6 if rs == 0 && rt != 0 + // BLTZC_MMR6 if rs == rt && rt != 0 + // BLTC_MMR6 if rs != rt && rs != 0 && rt != 0 + + bool HasRs = false; + + InsnType Rt = fieldFromInstruction(insn, 21, 5); + InsnType Rs = fieldFromInstruction(insn, 16, 5); + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + + if (Rt == 0) + return MCDisassembler::Fail; + else if (Rs == 0) + MI.setOpcode(Mips::BGTZC_MMR6); + else if (Rs == Rt) + MI.setOpcode(Mips::BLTZC_MMR6); + else { + MI.setOpcode(Mips::BLTC_MMR6); + HasRs = true; + } + + if (HasRs) + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, + Rs))); + + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, + Rt))); + + MI.addOperand(MCOperand::createImm(Imm)); + + return MCDisassembler::Success; +} + +template +static DecodeStatus DecodePOP75GroupBranchMMR6(MCInst &MI, InsnType insn, + uint64_t Address, + const void *Decoder) { + // We have: + // 0b111101 ttttt sssss iiiiiiiiiiiiiiii + // Invalid if rt == 0 + // BLEZC_MMR6 if rs == 0 && rt != 0 + // BGEZC_MMR6 if rs == rt && rt != 0 + // BGEC_MMR6 if rs != rt && rs != 0 && rt != 0 + + InsnType Rt = fieldFromInstruction(insn, 21, 5); + InsnType Rs = fieldFromInstruction(insn, 16, 5); + int64_t Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; + bool HasRs = false; + + if (Rt == 0) + return MCDisassembler::Fail; + else if (Rs == 0) + MI.setOpcode(Mips::BLEZC_MMR6); + else if (Rs == Rt) + MI.setOpcode(Mips::BGEZC_MMR6); + else { + HasRs = true; + MI.setOpcode(Mips::BGEC_MMR6); } + if (HasRs) + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, + Rs))); + + MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, + Rt))); + MI.addOperand(MCOperand::createImm(Imm)); return MCDisassembler::Success; @@ -2008,7 +2103,7 @@ unsigned Offset, uint64_t Address, const void *Decoder) { - int32_t BranchOffset = SignExtend32<21>(Offset) << 1; + int32_t BranchOffset = SignExtend32<21>(Offset) * 4 + 4; Inst.addOperand(MCOperand::createImm(BranchOffset)); return MCDisassembler::Success; @@ -2285,7 +2380,7 @@ InsnType Rt = fieldFromInstruction(insn, 21, 5); InsnType Rs = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; + InsnType Imm = 0; bool HasRs = false; bool HasRt = false; @@ -2294,15 +2389,18 @@ else if (Rs == 0) { MI.setOpcode(Mips::BGTZALC_MMR6); HasRt = true; + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; } else if (Rs == Rt) { MI.setOpcode(Mips::BLTZALC_MMR6); HasRs = true; + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; } else { MI.setOpcode(Mips::BLTUC_MMR6); HasRs = true; HasRt = true; + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; } if (HasRs) @@ -2331,18 +2429,23 @@ InsnType Rt = fieldFromInstruction(insn, 21, 5); InsnType Rs = fieldFromInstruction(insn, 16, 5); - InsnType Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; + InsnType Imm = 0; bool HasRs = false; if (Rt == 0) return MCDisassembler::Fail; - else if (Rs == 0) + else if (Rs == 0) { MI.setOpcode(Mips::BLEZALC_MMR6); - else if (Rs == Rt) + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; + } + else if (Rs == Rt) { MI.setOpcode(Mips::BGEZALC_MMR6); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 2; + } else { HasRs = true; MI.setOpcode(Mips::BGEUC_MMR6); + Imm = SignExtend64(fieldFromInstruction(insn, 0, 16), 16) * 4 + 4; } if (HasRs) Index: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h +++ lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.h @@ -116,6 +116,13 @@ SmallVectorImpl &Fixups, const MCSubtargetInfo &STI) const; + // getBranchTargetOpValueLsl2MMR6 - Return binary encoding of the branch + // target operand. If the machine operand requires relocation, + // record the relocation and return zero. + unsigned getBranchTargetOpValueLsl2MMR6(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const; + // getBranchTarget7OpValue - Return binary encoding of the microMIPS branch // target operand. If the machine operand requires relocation, // record the relocation and return zero. Index: lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp =================================================================== --- lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp +++ lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp @@ -332,6 +332,30 @@ return 0; } +/// getBranchTargetOpValueLsl2MMR6 - Return binary encoding of the branch +/// target operand. If the machine operand requires relocation, +/// record the relocation and return zero. +unsigned MipsMCCodeEmitter:: +getBranchTargetOpValueLsl2MMR6(const MCInst &MI, unsigned OpNo, + SmallVectorImpl &Fixups, + const MCSubtargetInfo &STI) const { + + const MCOperand &MO = MI.getOperand(OpNo); + + // If the destination is an immediate, divide by 4. + if (MO.isImm()) + return MO.getImm() >> 2; + + assert(MO.isExpr() && + "getBranchTargetOpValueLsl2MMR6 expects only expressions or immediates"); + + const MCExpr *FixupExpression = MCBinaryExpr::createAdd( + MO.getExpr(), MCConstantExpr::create(-4, Ctx), Ctx); + Fixups.push_back(MCFixup::create(0, FixupExpression, + MCFixupKind(Mips::fixup_Mips_PC16))); + return 0; +} + /// getBranchTarget7OpValueMM - Return binary encoding of the microMIPS branch /// target operand. If the machine operand requires relocation, /// record the relocation and return zero. @@ -432,8 +456,8 @@ const MCOperand &MO = MI.getOperand(OpNo); - // If the destination is an immediate, divide by 2. - if (MO.isImm()) return MO.getImm() >> 1; + // If the destination is an immediate, divide by 4. + if (MO.isImm()) return MO.getImm() >> 2; assert(MO.isExpr() && "getBranchTarget21OpValueMM expects only expressions or immediates"); Index: lib/Target/Mips/MicroMips32r6InstrInfo.td =================================================================== --- lib/Target/Mips/MicroMips32r6InstrInfo.td +++ lib/Target/Mips/MicroMips32r6InstrInfo.td @@ -32,6 +32,15 @@ let ParserMatchClass = MipsJumpTargetAsmOperand; } +def brtarget_lsl2_mm : Operand { + let EncoderMethod = "getBranchTargetOpValueLsl2MMR6"; + let OperandType = "OPERAND_PCREL"; + // Instructions that use this operand have their decoder method + // set with DecodeDisambiguates + let DecoderMethod = ""; + let ParserMatchClass = MipsJumpTargetAsmOperand; +} + //===----------------------------------------------------------------------===// // // Instruction Encodings @@ -56,16 +65,28 @@ class BRK_MMR6_ENC : BREAK_MMR6_ENC<"break">; class BEQZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"beqzc", 0b100000>; class BNEZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"bnezc", 0b101000>; -class BGEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgec", 0b111001>; +class BGEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgec", 0b111101>, + DecodeDisambiguates<"POP75GroupBranchMMR6">; class BGEUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bgeuc", 0b110000>, DecodeDisambiguates<"BlezGroupBranchMMR6">; -class BLTC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltc", 0b110001>; +class BLTC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltc", 0b110101>, + DecodeDisambiguates<"POP65GroupBranchMMR6">; class BLTUC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bltuc", 0b111000>, DecodeDisambiguates<"BgtzGroupBranchMMR6">; class BEQC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"beqc", 0b011101>; class BNEC_MMR6_ENC : CMP_BRANCH_2R_OFF16_FM_MMR6<"bnec", 0b011111>; -class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"beqzalc", 0b011101>; -class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bnezalc", 0b011111>; +class BLTZC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bltzc", 0b110101>, + DecodeDisambiguates<"POP65GroupBranchMMR6">; +class BLEZC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"blezc", 0b111101>, + DecodeDisambiguates<"POP75GroupBranchMMR6">; +class BGEZC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bgezc", 0b111101>, + DecodeDisambiguates<"POP75GroupBranchMMR6">; +class BGTZC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bgtzc", 0b110101>, + DecodeDisambiguates<"POP65GroupBranchMMR6">; +class BEQZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"beqzalc", 0b011101>, + DecodeDisambiguates<"POP35GroupBranchMMR6">; +class BNEZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bnezalc", 0b011111>, + DecodeDisambiguates<"POP37GroupBranchMMR6">; class BGTZALC_MMR6_ENC : CMP_BRANCH_1R_RT_OFF16_FM_MMR6<"bgtzalc", 0b111000>, MMDecodeDisambiguatedBy<"BgtzGroupBranchMMR6">; class BLTZALC_MMR6_ENC : CMP_BRANCH_1R_BOTH_OFF16_FM_MMR6<"bltzalc", 0b111000>, @@ -230,6 +251,49 @@ class LWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"lwc2", 0b0000>; class SWC2_MMR6_ENC : POOL32B_LDWC2_SDWC2_FM_MMR6<"swc2", 0b1000>; +/// Floating Point Instructions +class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>; +class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>; +class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>; +class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>; +class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>; +class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>; +class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>; +class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>; +class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>; +class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>; +class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>; +class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>; +class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>; +class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>; +class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>; +class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>; +class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>; +class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>; +class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>; +class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>; +class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>; +class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>; +class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>; +class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>; + +class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>; +class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>; +class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>; +class CVT_W_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.d", 1, 0b00100100>; +class CVT_D_S_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.s", 0, 0b1001101>; +class CVT_D_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.w", 1, 0b1001101>; +class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>; +class CVT_S_D_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.d", 0, 0b1101101>; +class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>; +class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>; + +//===----------------------------------------------------------------------===// +// +// Instruction Descriptions +// +//===----------------------------------------------------------------------===// + class CMP_CBR_RT_Z_MMR6_DESC_BASE : BRANCH_DESC_BASE { @@ -269,6 +333,15 @@ list Defs = [RA]; } +class BLTZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bltzc", brtarget_lsl2_mm, + GPR32Opnd>; +class BLEZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"blezc", brtarget_lsl2_mm, + GPR32Opnd>; +class BGEZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgezc", brtarget_lsl2_mm, + GPR32Opnd>; +class BGTZC_MMR6_DESC : CMP_CBR_RT_Z_MMR6_DESC_BASE<"bgtzc", brtarget_lsl2_mm, + GPR32Opnd>; + class CMP_CBR_2R_MMR6_DESC_BASE : BRANCH_DESC_BASE { dag InOperandList = (ins GPROpnd:$rs, GPROpnd:$rt, opnd:$offset); @@ -277,62 +350,19 @@ list Defs = [AT]; } -class BGEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgec", brtarget_mm, +class BGEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgec", brtarget_lsl2_mm, GPR32Opnd>; -class BGEUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgeuc", brtarget_mm, +class BGEUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bgeuc", brtarget_lsl2_mm, GPR32Opnd>; -class BLTC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltc", brtarget_mm, +class BLTC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltc", brtarget_lsl2_mm, GPR32Opnd>; -class BLTUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltuc", brtarget_mm, +class BLTUC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bltuc", brtarget_lsl2_mm, GPR32Opnd>; -class BEQC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"beqc", brtarget_mm, +class BEQC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"beqc", brtarget_lsl2_mm, GPR32Opnd>; -class BNEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bnec", brtarget_mm, +class BNEC_MMR6_DESC : CMP_CBR_2R_MMR6_DESC_BASE<"bnec", brtarget_lsl2_mm, GPR32Opnd>; -/// Floating Point Instructions -class FADD_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.s", 0, 0b00110000>; -class FADD_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"add.d", 1, 0b00110000>; -class FSUB_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.s", 0, 0b01110000>; -class FSUB_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"sub.d", 1, 0b01110000>; -class FMUL_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.s", 0, 0b10110000>; -class FMUL_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"mul.d", 1, 0b10110000>; -class FDIV_S_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.s", 0, 0b11110000>; -class FDIV_D_MMR6_ENC : POOL32F_ARITH_FM_MMR6<"div.d", 1, 0b11110000>; -class MADDF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.s", 0, 0b110111000>; -class MADDF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"maddf.d", 1, 0b110111000>; -class MSUBF_S_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.s", 0, 0b111111000>; -class MSUBF_D_MMR6_ENC : POOL32F_ARITHF_FM_MMR6<"msubf.d", 1, 0b111111000>; -class FMOV_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.s", 0, 0b0000001>; -class FMOV_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"mov.d", 1, 0b0000001>; -class FNEG_S_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.s", 0, 0b0101101>; -class FNEG_D_MMR6_ENC : POOL32F_MOV_NEG_FM_MMR6<"neg.d", 1, 0b0101101>; -class MAX_S_MMR6_ENC : POOL32F_MINMAX_FM<"max.s", 0, 0b000001011>; -class MAX_D_MMR6_ENC : POOL32F_MINMAX_FM<"max.d", 1, 0b000001011>; -class MAXA_S_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.s", 0, 0b000101011>; -class MAXA_D_MMR6_ENC : POOL32F_MINMAX_FM<"maxa.d", 1, 0b000101011>; -class MIN_S_MMR6_ENC : POOL32F_MINMAX_FM<"min.s", 0, 0b000000011>; -class MIN_D_MMR6_ENC : POOL32F_MINMAX_FM<"min.d", 1, 0b000000011>; -class MINA_S_MMR6_ENC : POOL32F_MINMAX_FM<"mina.s", 0, 0b000100011>; -class MINA_D_MMR6_ENC : POOL32F_MINMAX_FM<"mina.d", 1, 0b000100011>; - -class CVT_L_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.s", 0, 0b00000100>; -class CVT_L_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.l.d", 1, 0b00000100>; -class CVT_W_S_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.s", 0, 0b00100100>; -class CVT_W_D_MMR6_ENC : POOL32F_CVT_LW_FM<"cvt.w.d", 1, 0b00100100>; -class CVT_D_S_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.s", 0, 0b1001101>; -class CVT_D_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.w", 1, 0b1001101>; -class CVT_D_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.d.l", 2, 0b1001101>; -class CVT_S_D_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.d", 0, 0b1101101>; -class CVT_S_W_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.w", 1, 0b1101101>; -class CVT_S_L_MMR6_ENC : POOL32F_CVT_DS_FM<"cvt.s.l", 2, 0b1101101>; - -//===----------------------------------------------------------------------===// -// -// Instruction Descriptions -// -//===----------------------------------------------------------------------===// - class ADD_MMR6_DESC : ArithLogicR<"add", GPR32Opnd>; class ADDIU_MMR6_DESC : ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16, add>; class ADDU_MMR6_DESC : ArithLogicR<"addu", GPR32Opnd>; @@ -1661,6 +1691,10 @@ DecodeDisambiguates<"POP35GroupBranchMMR6">; def BNEC_MMR6 : R6MMR6Rel, BNEC_MMR6_ENC, BNEC_MMR6_DESC, ISA_MICROMIPS32R6, DecodeDisambiguates<"POP37GroupBranchMMR6">; +def BLTZC_MMR6 : R6MMR6Rel, BLTZC_MMR6_ENC, BLTZC_MMR6_DESC, ISA_MICROMIPS32R6; +def BLEZC_MMR6 : R6MMR6Rel, BLEZC_MMR6_ENC, BLEZC_MMR6_DESC, ISA_MICROMIPS32R6; +def BGEZC_MMR6 : R6MMR6Rel, BGEZC_MMR6_ENC, BGEZC_MMR6_DESC, ISA_MICROMIPS32R6; +def BGTZC_MMR6 : R6MMR6Rel, BGTZC_MMR6_ENC, BGTZC_MMR6_DESC, ISA_MICROMIPS32R6; def BGEZALC_MMR6 : R6MMR6Rel, BGEZALC_MMR6_ENC, BGEZALC_MMR6_DESC, ISA_MICROMIPS32R6; def BGTZALC_MMR6 : R6MMR6Rel, BGTZALC_MMR6_ENC, BGTZALC_MMR6_DESC, Index: lib/Target/Mips/MicroMipsInstrInfo.td =================================================================== --- lib/Target/Mips/MicroMipsInstrInfo.td +++ lib/Target/Mips/MicroMipsInstrInfo.td @@ -667,13 +667,15 @@ InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmOther, opstr>; -let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { +let DecoderNamespace = "MicroMips", Predicates = [InMicroMips, NotMips32r6, + NotMips64r6] in { /// Compact Branch Instructions def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>, COMPACT_BRANCH_FM_MM<0x7>; def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>, COMPACT_BRANCH_FM_MM<0x5>; - +} +let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { /// Arithmetic Instructions (ALU Immediate) def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>, ADDI_FM_MM<0xc>; Index: lib/Target/Mips/Mips32r6InstrInfo.td =================================================================== --- lib/Target/Mips/Mips32r6InstrInfo.td +++ lib/Target/Mips/Mips32r6InstrInfo.td @@ -760,16 +760,16 @@ def BGEC : R6MMR6Rel, BGEC_ENC, BGEC_DESC, ISA_MIPS32R6; def BGEUC : R6MMR6Rel, BGEUC_ENC, BGEUC_DESC, ISA_MIPS32R6; def BGEZALC : R6MMR6Rel, BGEZALC_ENC, BGEZALC_DESC, ISA_MIPS32R6; -def BGEZC : BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6; +def BGEZC : R6MMR6Rel, BGEZC_ENC, BGEZC_DESC, ISA_MIPS32R6; def BGTZALC : R6MMR6Rel, BGTZALC_ENC, BGTZALC_DESC, ISA_MIPS32R6; -def BGTZC : BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6; +def BGTZC : R6MMR6Rel, BGTZC_ENC, BGTZC_DESC, ISA_MIPS32R6; def BITSWAP : R6MMR6Rel, BITSWAP_ENC, BITSWAP_DESC, ISA_MIPS32R6; def BLEZALC : R6MMR6Rel, BLEZALC_ENC, BLEZALC_DESC, ISA_MIPS32R6; -def BLEZC : BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6; +def BLEZC : R6MMR6Rel, BLEZC_ENC, BLEZC_DESC, ISA_MIPS32R6; def BLTC : R6MMR6Rel, BLTC_ENC, BLTC_DESC, ISA_MIPS32R6; def BLTUC : R6MMR6Rel, BLTUC_ENC, BLTUC_DESC, ISA_MIPS32R6; def BLTZALC : R6MMR6Rel, BLTZALC_ENC, BLTZALC_DESC, ISA_MIPS32R6; -def BLTZC : BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6; +def BLTZC : R6MMR6Rel, BLTZC_ENC, BLTZC_DESC, ISA_MIPS32R6; def BNEC : R6MMR6Rel, BNEC_ENC, BNEC_DESC, ISA_MIPS32R6; def BNEZALC : R6MMR6Rel, BNEZALC_ENC, BNEZALC_DESC, ISA_MIPS32R6; def BNEZC : R6MMR6Rel, BNEZC_ENC, BNEZC_DESC, ISA_MIPS32R6; Index: test/MC/Disassembler/Mips/micromips32r6/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips32r6/valid.txt +++ test/MC/Disassembler/Mips/micromips32r6/valid.txt @@ -39,20 +39,20 @@ 0x00 0xa4 0x1a 0x50 # CHECK: and $3, $4, $5 0xd0 0x64 0x04 0xd2 # CHECK: andi $3, $4, 1234 0x10 0x62 0xff 0xe9 # CHECK: aui $3, $2, -23 -0x74 0x83 0x00 0x08 # CHECK: beqc $3, $4, 16 -0xe4 0x83 0x00 0x08 # CHECK: bgec $3, $4, 16 -0xc0 0x83 0x00 0x08 # CHECK: bgeuc $3, $4, 16 -0xc4 0x83 0x00 0x08 # CHECK: bltc $3, $4, 16 -0xe0 0x83 0x00 0x08 # CHECK: bltuc $3, $4, 16 -0x7c 0x83 0x00 0x08 # CHECK: bnec $3, $4, 16 +0x74 0x83 0x00 0x04 # CHECK: beqc $3, $4, 20 +0xf4 0x83 0x00 0x04 # CHECK: bgec $3, $4, 20 +0xc0 0x83 0x00 0x04 # CHECK: bgeuc $3, $4, 20 +0xd4 0x83 0x00 0x04 # CHECK: bltc $3, $4, 20 +0xe0 0x83 0x00 0x04 # CHECK: bltuc $3, $4, 20 +0x7c 0x83 0x00 0x04 # CHECK: bnec $3, $4, 20 0x74 0x40 0x02 0x9a # CHECK: beqzalc $2, 1332 0x7c 0x40 0x02 0x9a # CHECK: bnezalc $2, 1332 0xc0 0x42 0x02 0x9a # CHECK: bgezalc $2, 1332 0xe0 0x40 0x02 0x9a # CHECK: bgtzalc $2, 1332 0xe0 0x42 0x02 0x9a # CHECK: bltzalc $2, 1332 0xc0 0x40 0x02 0x9a # CHECK: blezalc $2, 1332 -0x80 0x60 0x00 0x20 # CHECK: beqzc $3, 64 -0xa0 0x60 0x00 0x20 # CHECK: bnezc $3, 64 +0x80 0x60 0x00 0x10 # CHECK: beqzc $3, 68 +0xa0 0x60 0x00 0x10 # CHECK: bnezc $3, 68 0xb4 0x37 0x96 0xb8 # CHECK: balc 7286128 0x94 0x37 0x96 0xb8 # CHECK: bc 7286128 0x00 0x44 0x0b 0x3c # CHECK: bitswap $4, $2 @@ -339,3 +339,7 @@ 0x20 0x50 0xa0 0x08 # CHECK: sdc2 $2, 8($16) 0x98 0xcd 0x01 0x71 # CHECK: swc1 $f6, 369($13) 0x20 0xf1 0x83 0x09 # CHECK: swc2 $7, 777($17) +0xd4 0xc6 0x00 0x20 # CHECK: bltzc $6, 132 +0xf4 0x40 0x00 0x40 # CHECK: blezc $2, 260 +0xf6 0x10 0x00 0x80 # CHECK: bgezc $16, 516 +0xd5 0x80 0x01 0x00 # CHECK: bgtzc $12, 1028 Index: test/MC/Disassembler/Mips/micromips64r6/valid.txt =================================================================== --- test/MC/Disassembler/Mips/micromips64r6/valid.txt +++ test/MC/Disassembler/Mips/micromips64r6/valid.txt @@ -306,3 +306,7 @@ 0x20 0x50 0xa0 0x08 # CHECK: sdc2 $2, 8($16) 0x98 0xcd 0x01 0x71 # CHECK: swc1 $f6, 369($13) 0x20 0xf1 0x83 0x09 # CHECK: swc2 $7, 777($17) +0xd4 0xc6 0x00 0x20 # CHECK: bltzc $6, 132 +0xf4 0x40 0x00 0x40 # CHECK: blezc $2, 260 +0xf6 0x10 0x00 0x80 # CHECK: bgezc $16, 516 +0xd5 0x80 0x01 0x00 # CHECK: bgtzc $12, 1028 Index: test/MC/Mips/micromips32r6/invalid.s =================================================================== --- test/MC/Mips/micromips32r6/invalid.s +++ test/MC/Mips/micromips32r6/invalid.s @@ -281,3 +281,21 @@ sdc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled swc2 $11, -1025($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled swc2 $11, 1024($12) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + bgec $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction + bltc $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction + bgeuc $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction + bltuc $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction + beqc $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction + bnec $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction + bgec $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different + bltc $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different + bgeuc $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different + bltuc $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different + beqc $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different + bnec $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different + blezc $0, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction + bgezc $0, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction + bgtzc $0, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction + bltzc $0, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction + beqzc $0, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction + bnezc $0, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction Index: test/MC/Mips/micromips32r6/valid.s =================================================================== --- test/MC/Mips/micromips32r6/valid.s +++ test/MC/Mips/micromips32r6/valid.s @@ -20,20 +20,20 @@ auipc $3, -1 # CHECK: auipc $3, -1 # encoding: [0x78,0x7e,0xff,0xff] align $4, $2, $3, 2 # CHECK: align $4, $2, $3, 2 # encoding: [0x00,0x43,0x24,0x1f] aui $3,$2,-23 # CHECK: aui $3, $2, -23 # encoding: [0x10,0x62,0xff,0xe9] - beqc $3,$4, 16 # CHECK: beqc $3, $4, 16 # encoding: [0x74,0x83,0x00,0x08] - bgec $3,$4, 16 # CHECK: bgec $3, $4, 16 # encoding: [0xe4,0x83,0x00,0x08] - bgeuc $3,$4, 16 # CHECK: bgeuc $3, $4, 16 # encoding: [0xc0,0x83,0x00,0x08] - bltc $3,$4, 16 # CHECK: bltc $3, $4, 16 # encoding: [0xc4,0x83,0x00,0x08] - bltuc $3,$4, 16 # CHECK: bltuc $3, $4, 16 # encoding: [0xe0,0x83,0x00,0x08] - bnec $3,$4, 16 # CHECK: bnec $3, $4, 16 # encoding: [0x7c,0x83,0x00,0x08] + beqc $3,$4, 16 # CHECK: beqc $3, $4, 16 # encoding: [0x74,0x83,0x00,0x04] + bgec $3,$4, 16 # CHECK: bgec $3, $4, 16 # encoding: [0xf4,0x83,0x00,0x04] + bgeuc $3,$4, 16 # CHECK: bgeuc $3, $4, 16 # encoding: [0xc0,0x83,0x00,0x04] + bltc $3,$4, 16 # CHECK: bltc $3, $4, 16 # encoding: [0xd4,0x83,0x00,0x04] + bltuc $3,$4, 16 # CHECK: bltuc $3, $4, 16 # encoding: [0xe0,0x83,0x00,0x04] + bnec $3,$4, 16 # CHECK: bnec $3, $4, 16 # encoding: [0x7c,0x83,0x00,0x04] beqzalc $2, 1332 # CHECK: beqzalc $2, 1332 # encoding: [0x74,0x40,0x02,0x9a] bnezalc $2, 1332 # CHECK: bnezalc $2, 1332 # encoding: [0x7c,0x40,0x02,0x9a] bgezalc $2, 1332 # CHECK: bgezalc $2, 1332 # encoding: [0xc0,0x42,0x02,0x9a] bgtzalc $2, 1332 # CHECK: bgtzalc $2, 1332 # encoding: [0xe0,0x40,0x02,0x9a] bltzalc $2, 1332 # CHECK: bltzalc $2, 1332 # encoding: [0xe0,0x42,0x02,0x9a] blezalc $2, 1332 # CHECK: blezalc $2, 1332 # encoding: [0xc0,0x40,0x02,0x9a] - beqzc $3, 64 # CHECK: beqzc $3, 64 # encoding: [0x80,0x60,0x00,0x20] - bnezc $3, 64 # CHECK: bnezc $3, 64 # encoding: [0xa0,0x60,0x00,0x20] + beqzc $3, 64 # CHECK: beqzc $3, 64 # encoding: [0x80,0x60,0x00,0x10] + bnezc $3, 64 # CHECK: bnezc $3, 64 # encoding: [0xa0,0x60,0x00,0x10] balc 7286128 # CHECK: balc 7286128 # encoding: [0xb4,0x37,0x96,0xb8] b 132 # CHECK: bc16 132 # encoding: [0xcc,0x42] bc 7286128 # CHECK: bc 7286128 # encoding: [0x94,0x37,0x96,0xb8] @@ -368,3 +368,7 @@ sdc2 $2, 8($16) # CHECK: sdc2 $2, 8($16) # encoding: [0x20,0x50,0xa0,0x08] swc1 $f6, 369($13) # CHECK: swc1 $f6, 369($13) # encoding: [0x98,0xcd,0x01,0x71] swc2 $7, 777($17) # CHECK: swc2 $7, 777($17) # encoding: [0x20,0xf1,0x83,0x09] + bltzc $6, 128 # CHECK: bltzc $6, 128 # encoding: [0xd4,0xc6,0x00,0x20] + blezc $2, 256 # CHECK: blezc $2, 256 # encoding: [0xf4,0x40,0x00,0x40] + bgezc $16, 512 # CHECK: bgezc $16, 512 # encoding: [0xf6,0x10,0x00,0x80] + bgtzc $12, 1024 # CHECK: bgtzc $12, 1024 # encoding: [0xd5,0x80,0x01,0x00] Index: test/MC/Mips/micromips64r6/invalid.s =================================================================== --- test/MC/Mips/micromips64r6/invalid.s +++ test/MC/Mips/micromips64r6/invalid.s @@ -325,3 +325,21 @@ sdc2 $32, 8($16) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction lwc2 $32, 16($4) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction swc2 $32, 777($17) # CHECK: :[[@LINE]]:8: error: invalid operand for instruction + bgec $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction + bltc $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction + bgeuc $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction + bltuc $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction + beqc $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction + bnec $0, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction + bgec $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different + bltc $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different + bgeuc $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different + bltuc $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different + beqc $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different + bnec $2, $2, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: registers must be different + blezc $0, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction + bgezc $0, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction + bgtzc $0, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction + bltzc $0, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction + beqzc $0, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction + bnezc $0, 12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand ($zero) for instruction Index: test/MC/Mips/micromips64r6/valid.s =================================================================== --- test/MC/Mips/micromips64r6/valid.s +++ test/MC/Mips/micromips64r6/valid.s @@ -317,5 +317,9 @@ sdc2 $2, 8($16) # CHECK: sdc2 $2, 8($16) # encoding: [0x20,0x50,0xa0,0x08] swc1 $f6, 369($13) # CHECK: swc1 $f6, 369($13) # encoding: [0x98,0xcd,0x01,0x71] swc2 $7, 777($17) # CHECK: swc2 $7, 777($17) # encoding: [0x20,0xf1,0x83,0x09] + bltzc $6, 128 # CHECK: bltzc $6, 128 # encoding: [0xd4,0xc6,0x00,0x20] + blezc $2, 256 # CHECK: blezc $2, 256 # encoding: [0xf4,0x40,0x00,0x40] + bgezc $16, 512 # CHECK: bgezc $16, 512 # encoding: [0xf6,0x10,0x00,0x80] + bgtzc $12, 1024 # CHECK: bgtzc $12, 1024 # encoding: [0xd5,0x80,0x01,0x00] 1: