Index: lib/Target/AMDGPU/SIRegisterInfo.td =================================================================== --- lib/Target/AMDGPU/SIRegisterInfo.td +++ lib/Target/AMDGPU/SIRegisterInfo.td @@ -248,11 +248,6 @@ // Register classes used as source and destination //===----------------------------------------------------------------------===// -class RegImmMatcher : AsmOperandClass { - let Name = name; - let RenderMethod = "addRegOrImmOperands"; -} - // Subset of SReg_32 without M0 for SMRD instructions and alike. // See comments in SIInstructions.td for more info. def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32], 32, @@ -344,6 +339,16 @@ let Size = 32; } +def VS_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VGPR_32, SReg_32)>; + +def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 32, (add VReg_64, SReg_64)> { + let CopyCost = 2; +} + +//===----------------------------------------------------------------------===// +// Register operands +//===----------------------------------------------------------------------===// + class RegImmOperand : RegisterOperand { let OperandNamespace = "AMDGPU"; let OperandType = "OPERAND_REG_IMM32"; @@ -354,6 +359,11 @@ let OperandType = "OPERAND_REG_INLINE_C"; } +class RegImmMatcher : AsmOperandClass { + let Name = name; + let RenderMethod = "addRegOrImmOperands"; +} + //===----------------------------------------------------------------------===// // SSrc_* Operands with an SGPR or a 32-bit immediate //===----------------------------------------------------------------------===// @@ -374,25 +384,19 @@ let ParserMatchClass = RegImmMatcher<"SCSrc32">; } +def SCSrc_64 : RegInlineOperand { + let ParserMatchClass = RegImmMatcher<"SCSrc64">; +} + //===----------------------------------------------------------------------===// // VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate //===----------------------------------------------------------------------===// -def VS_32 : RegisterClass<"AMDGPU", [i32, f32], 32, (add VGPR_32, SReg_32)>; - -def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 32, (add VReg_64, SReg_64)> { - let CopyCost = 2; -} - -def VSrc_32 : RegisterOperand { - let OperandNamespace = "AMDGPU"; - let OperandType = "OPERAND_REG_IMM32"; +def VSrc_32 : RegImmOperand { let ParserMatchClass = RegImmMatcher<"VSrc32">; } -def VSrc_64 : RegisterOperand { - let OperandNamespace = "AMDGPU"; - let OperandType = "OPERAND_REG_IMM32"; +def VSrc_64 : RegImmOperand { let ParserMatchClass = RegImmMatcher<"VSrc64">; } @@ -411,24 +415,10 @@ // VCSrc_* Operands with an SGPR, VGPR or an inline constant //===----------------------------------------------------------------------===// -def VCSrc_32 : RegisterOperand { - let OperandNamespace = "AMDGPU"; - let OperandType = "OPERAND_REG_INLINE_C"; +def VCSrc_32 : RegInlineOperand { let ParserMatchClass = RegImmMatcher<"VCSrc32">; } -def VCSrc_64 : RegisterOperand { - let OperandNamespace = "AMDGPU"; - let OperandType = "OPERAND_REG_INLINE_C"; +def VCSrc_64 : RegInlineOperand { let ParserMatchClass = RegImmMatcher<"VCSrc64">; } - -//===----------------------------------------------------------------------===// -// SCSrc_* Operands with an SGPR or an inline constant -//===----------------------------------------------------------------------===// - -def SCSrc_64 : RegisterOperand { - let OperandNamespace = "AMDGPU"; - let OperandType = "OPERAND_REG_INLINE_C"; - let ParserMatchClass = RegImmMatcher<"SCSrc64">; -}