Index: llvm/trunk/include/llvm/Target/TargetInstrInfo.h =================================================================== --- llvm/trunk/include/llvm/Target/TargetInstrInfo.h +++ llvm/trunk/include/llvm/Target/TargetInstrInfo.h @@ -466,7 +466,7 @@ /// /// The CFG information in MBB.Predecessors and MBB.Successors must be valid /// before calling this function. - virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, + virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify = false) const { @@ -512,7 +512,7 @@ /// If AllowModify is true, then this routine is allowed to modify the basic /// block (e.g. delete instructions after the unconditional branch). /// - virtual bool AnalyzeBranchPredicate(MachineBasicBlock &MBB, + virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify = false) const { return true; Index: llvm/trunk/lib/CodeGen/BranchFolding.cpp =================================================================== --- llvm/trunk/lib/CodeGen/BranchFolding.cpp +++ llvm/trunk/lib/CodeGen/BranchFolding.cpp @@ -222,7 +222,7 @@ for (MachineBasicBlock &MBB : MF) { MachineBasicBlock *TBB = nullptr, *FBB = nullptr; SmallVector Cond; - if (!TII->AnalyzeBranch(MBB, TBB, FBB, Cond, true)) + if (!TII->analyzeBranch(MBB, TBB, FBB, Cond, true)) MadeChange |= MBB.CorrectExtraCFGEdges(TBB, FBB, !Cond.empty()); MadeChange |= OptimizeImpDefsBlock(&MBB); } @@ -508,8 +508,7 @@ MachineBasicBlock *TBB = nullptr, *FBB = nullptr; SmallVector Cond; DebugLoc dl; // FIXME: this is nowhere - if (I != MF->end() && - !TII->AnalyzeBranch(*CurMBB, TBB, FBB, Cond, true)) { + if (I != MF->end() && !TII->analyzeBranch(*CurMBB, TBB, FBB, Cond, true)) { MachineBasicBlock *NextBB = &*I; if (TBB == NextBB && !Cond.empty() && !FBB) { if (!TII->ReverseBranchCondition(Cond)) { @@ -1029,7 +1028,7 @@ MachineBasicBlock *TBB = nullptr, *FBB = nullptr; SmallVector Cond; - if (!TII->AnalyzeBranch(*PBB, TBB, FBB, Cond, true)) { + if (!TII->analyzeBranch(*PBB, TBB, FBB, Cond, true)) { // Failing case: IBB is the target of a cbr, and we cannot reverse the // branch. SmallVector NewCond(Cond); @@ -1278,7 +1277,7 @@ MachineBasicBlock *PriorTBB = nullptr, *PriorFBB = nullptr; SmallVector PriorCond; bool PriorUnAnalyzable = - TII->AnalyzeBranch(PrevBB, PriorTBB, PriorFBB, PriorCond, true); + TII->analyzeBranch(PrevBB, PriorTBB, PriorFBB, PriorCond, true); if (!PriorUnAnalyzable) { // If the CFG for the prior block has extra edges, remove them. MadeChange |= PrevBB.CorrectExtraCFGEdges(PriorTBB, PriorFBB, @@ -1415,7 +1414,8 @@ // Analyze the branch in the current block. MachineBasicBlock *CurTBB = nullptr, *CurFBB = nullptr; SmallVector CurCond; - bool CurUnAnalyzable= TII->AnalyzeBranch(*MBB, CurTBB, CurFBB, CurCond, true); + bool CurUnAnalyzable = + TII->analyzeBranch(*MBB, CurTBB, CurFBB, CurCond, true); if (!CurUnAnalyzable) { // If the CFG for the prior block has extra edges, remove them. MadeChange |= MBB->CorrectExtraCFGEdges(CurTBB, CurFBB, !CurCond.empty()); @@ -1499,8 +1499,8 @@ // change this to an unconditional branch (and fix the CFG). MachineBasicBlock *NewCurTBB = nullptr, *NewCurFBB = nullptr; SmallVector NewCurCond; - bool NewCurUnAnalyzable = TII->AnalyzeBranch(*PMBB, NewCurTBB, - NewCurFBB, NewCurCond, true); + bool NewCurUnAnalyzable = TII->analyzeBranch( + *PMBB, NewCurTBB, NewCurFBB, NewCurCond, true); if (!NewCurUnAnalyzable && NewCurTBB && NewCurTBB == NewCurFBB) { DebugLoc pdl = getBranchDebugLoc(*PMBB); TII->RemoveBranch(*PMBB); @@ -1546,9 +1546,9 @@ MachineBasicBlock *PredTBB = nullptr, *PredFBB = nullptr; SmallVector PredCond; if (PredBB != MBB && !PredBB->canFallThrough() && - !TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true) - && (!CurFallsThru || !CurTBB || !CurFBB) - && (!CurFallsThru || MBB->getNumber() >= PredBB->getNumber())) { + !TII->analyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true) && + (!CurFallsThru || !CurTBB || !CurFBB) && + (!CurFallsThru || MBB->getNumber() >= PredBB->getNumber())) { // If the current block doesn't fall through, just move it. // If the current block can fall through and does not end with a // conditional branch, we need to append an unconditional jump to @@ -1604,7 +1604,7 @@ // Now check to see if the current block is sitting between PrevBB and // a block to which it could fall through. if (FallThrough != MF.end() && - !TII->AnalyzeBranch(PrevBB, PrevTBB, PrevFBB, PrevCond, true) && + !TII->analyzeBranch(PrevBB, PrevTBB, PrevFBB, PrevCond, true) && PrevBB.isSuccessor(&*FallThrough)) { MBB->moveAfter(&MF.back()); MadeChange = true; @@ -1763,7 +1763,7 @@ bool BranchFolder::HoistCommonCodeInSuccs(MachineBasicBlock *MBB) { MachineBasicBlock *TBB = nullptr, *FBB = nullptr; SmallVector Cond; - if (TII->AnalyzeBranch(*MBB, TBB, FBB, Cond, true) || !TBB || Cond.empty()) + if (TII->analyzeBranch(*MBB, TBB, FBB, Cond, true) || !TBB || Cond.empty()) return false; if (!FBB) FBB = findFalseBlock(MBB, TBB); Index: llvm/trunk/lib/CodeGen/EarlyIfConversion.cpp =================================================================== --- llvm/trunk/lib/CodeGen/EarlyIfConversion.cpp +++ llvm/trunk/lib/CodeGen/EarlyIfConversion.cpp @@ -386,7 +386,7 @@ // The branch we're looking to eliminate must be analyzable. Cond.clear(); - if (TII->AnalyzeBranch(*Head, TBB, FBB, Cond)) { + if (TII->analyzeBranch(*Head, TBB, FBB, Cond)) { DEBUG(dbgs() << "Branch not analyzable.\n"); return false; } Index: llvm/trunk/lib/CodeGen/IfConversion.cpp =================================================================== --- llvm/trunk/lib/CodeGen/IfConversion.cpp +++ llvm/trunk/lib/CodeGen/IfConversion.cpp @@ -87,7 +87,7 @@ /// BBInfo - One per MachineBasicBlock, this is used to cache the result /// if-conversion feasibility analysis. This includes results from - /// TargetInstrInfo::AnalyzeBranch() (i.e. TBB, FBB, and Cond), and its + /// TargetInstrInfo::analyzeBranch() (i.e. TBB, FBB, and Cond), and its /// classification, and common tail block of its successors (if it's a /// diamond shape), its size, whether it's predicable, and whether any /// instruction can clobber the 'would-be' predicate. @@ -96,7 +96,7 @@ /// IsBeingAnalyzed - True if BB is currently being analyzed. /// IsAnalyzed - True if BB has been analyzed (info is still valid). /// IsEnqueued - True if BB has been enqueued to be ifcvt'ed. - /// IsBrAnalyzable - True if AnalyzeBranch() returns false. + /// IsBrAnalyzable - True if analyzeBranch() returns false. /// HasFallThrough - True if BB may fallthrough to the following BB. /// IsUnpredicable - True if BB is known to be unpredicable. /// ClobbersPred - True if BB could modify predicates (e.g. has @@ -105,7 +105,7 @@ /// ExtraCost - Extra cost for multi-cycle instructions. /// ExtraCost2 - Some instructions are slower when predicated /// BB - Corresponding MachineBasicBlock. - /// TrueBB / FalseBB- See AnalyzeBranch(). + /// TrueBB / FalseBB- See analyzeBranch(). /// BrCond - Conditions for end of block conditional branches. /// Predicate - Predicate used in the BB. struct BBInfo { @@ -655,7 +655,7 @@ BBI.TrueBB = BBI.FalseBB = nullptr; BBI.BrCond.clear(); BBI.IsBrAnalyzable = - !TII->AnalyzeBranch(*BBI.BB, BBI.TrueBB, BBI.FalseBB, BBI.BrCond); + !TII->analyzeBranch(*BBI.BB, BBI.TrueBB, BBI.FalseBB, BBI.BrCond); BBI.HasFallThrough = BBI.IsBrAnalyzable && BBI.FalseBB == nullptr; if (BBI.BrCond.size()) { @@ -1041,7 +1041,7 @@ void IfConverter::RemoveExtraEdges(BBInfo &BBI) { MachineBasicBlock *TBB = nullptr, *FBB = nullptr; SmallVector Cond; - if (!TII->AnalyzeBranch(*BBI.BB, TBB, FBB, Cond)) + if (!TII->analyzeBranch(*BBI.BB, TBB, FBB, Cond)) BBI.BB->CorrectExtraCFGEdges(TBB, FBB, !Cond.empty()); } Index: llvm/trunk/lib/CodeGen/ImplicitNullChecks.cpp =================================================================== --- llvm/trunk/lib/CodeGen/ImplicitNullChecks.cpp +++ llvm/trunk/lib/CodeGen/ImplicitNullChecks.cpp @@ -332,7 +332,7 @@ MachineBranchPredicate MBP; - if (TII->AnalyzeBranchPredicate(MBB, MBP, true)) + if (TII->analyzeBranchPredicate(MBB, MBP, true)) return false; // Is the predicate comparing an integer to zero? Index: llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp =================================================================== --- llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp +++ llvm/trunk/lib/CodeGen/MachineBasicBlock.cpp @@ -410,7 +410,7 @@ MachineBasicBlock *TBB = nullptr, *FBB = nullptr; SmallVector Cond; DebugLoc DL; // FIXME: this is nowhere - bool B = TII->AnalyzeBranch(*this, TBB, FBB, Cond); + bool B = TII->analyzeBranch(*this, TBB, FBB, Cond); (void) B; assert(!B && "UpdateTerminators requires analyzable predecessors!"); if (Cond.empty()) { @@ -688,7 +688,7 @@ MachineBasicBlock *TBB = nullptr, *FBB = nullptr; SmallVector Cond; const TargetInstrInfo *TII = getParent()->getSubtarget().getInstrInfo(); - if (TII->AnalyzeBranch(*this, TBB, FBB, Cond)) { + if (TII->analyzeBranch(*this, TBB, FBB, Cond)) { // If we couldn't analyze the branch, examine the last instruction. // If the block doesn't end in a known control barrier, assume fallthrough // is possible. The isPredicated check is needed because this code can be @@ -973,7 +973,7 @@ MachineBasicBlock *TBB = nullptr, *FBB = nullptr; SmallVector Cond; // AnalyzeBanch should modify this, since we did not allow modification. - if (TII->AnalyzeBranch(*const_cast(this), TBB, FBB, Cond, + if (TII->analyzeBranch(*const_cast(this), TBB, FBB, Cond, /*AllowModify*/ false)) return false; Index: llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp =================================================================== --- llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp +++ llvm/trunk/lib/CodeGen/MachineBlockPlacement.cpp @@ -1418,7 +1418,7 @@ for (;;) { Cond.clear(); MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For AnalyzeBranch. - if (!TII->AnalyzeBranch(*BB, TBB, FBB, Cond) || !FI->canFallThrough()) + if (!TII->analyzeBranch(*BB, TBB, FBB, Cond) || !FI->canFallThrough()) break; MachineFunction::iterator NextFI = std::next(FI); @@ -1506,7 +1506,7 @@ // before layout, and no longer fall-through it after layout; or // o. just opposite. // - // AnalyzeBranch() may return erroneous value for FBB when these two + // analyzeBranch() may return erroneous value for FBB when these two // situations take place. For the first scenario FBB is mistakenly set NULL; // for the 2nd scenario, the FBB, which is expected to be NULL, is // mistakenly pointing to "*BI". @@ -1517,19 +1517,19 @@ // PrevBB->updateTerminator(); // Cond.clear(); // TBB = FBB = nullptr; - // if (TII->AnalyzeBranch(*PrevBB, TBB, FBB, Cond)) { + // if (TII->analyzeBranch(*PrevBB, TBB, FBB, Cond)) { // // FIXME: This should never take place. // TBB = FBB = nullptr; // } // } - if (!TII->AnalyzeBranch(*PrevBB, TBB, FBB, Cond)) + if (!TII->analyzeBranch(*PrevBB, TBB, FBB, Cond)) PrevBB->updateTerminator(); } // Fixup the last block. Cond.clear(); MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For AnalyzeBranch. - if (!TII->AnalyzeBranch(F->back(), TBB, FBB, Cond)) + if (!TII->analyzeBranch(F->back(), TBB, FBB, Cond)) F->back().updateTerminator(); BlockWorkList.clear(); @@ -1549,7 +1549,7 @@ for (MachineBasicBlock *ChainBB : FunctionChain) { Cond.clear(); MachineBasicBlock *TBB = nullptr, *FBB = nullptr; // For AnalyzeBranch. - if (!TII->AnalyzeBranch(*ChainBB, TBB, FBB, Cond, /*AllowModify*/ true)) { + if (!TII->analyzeBranch(*ChainBB, TBB, FBB, Cond, /*AllowModify*/ true)) { // If PrevBB has a two-way branch, try to re-order the branches // such that we branch to the successor with higher probability first. if (TBB && !Cond.empty() && FBB && Index: llvm/trunk/lib/CodeGen/MachineLICM.cpp =================================================================== --- llvm/trunk/lib/CodeGen/MachineLICM.cpp +++ llvm/trunk/lib/CodeGen/MachineLICM.cpp @@ -764,7 +764,7 @@ if (BB->pred_size() == 1) { MachineBasicBlock *TBB = nullptr, *FBB = nullptr; SmallVector Cond; - if (!TII->AnalyzeBranch(*BB, TBB, FBB, Cond, false) && Cond.empty()) + if (!TII->analyzeBranch(*BB, TBB, FBB, Cond, false) && Cond.empty()) InitRegPressure(*BB->pred_begin()); } Index: llvm/trunk/lib/CodeGen/MachineSink.cpp =================================================================== --- llvm/trunk/lib/CodeGen/MachineSink.cpp +++ llvm/trunk/lib/CodeGen/MachineSink.cpp @@ -704,7 +704,7 @@ return false; MachineBranchPredicate MBP; - if (TII->AnalyzeBranchPredicate(*PredMBB, MBP, false)) + if (TII->analyzeBranchPredicate(*PredMBB, MBP, false)) return false; return MBP.LHS.isReg() && MBP.RHS.isImm() && MBP.RHS.getImm() == 0 && Index: llvm/trunk/lib/CodeGen/MachineVerifier.cpp =================================================================== --- llvm/trunk/lib/CodeGen/MachineVerifier.cpp +++ llvm/trunk/lib/CodeGen/MachineVerifier.cpp @@ -622,8 +622,8 @@ // Call AnalyzeBranch. If it succeeds, there several more conditions to check. MachineBasicBlock *TBB = nullptr, *FBB = nullptr; SmallVector Cond; - if (!TII->AnalyzeBranch(*const_cast(MBB), - TBB, FBB, Cond)) { + if (!TII->analyzeBranch(*const_cast(MBB), TBB, FBB, + Cond)) { // Ok, AnalyzeBranch thinks it knows what's going on with this block. Let's // check whether its answers match up with reality. if (!TBB && !FBB) { Index: llvm/trunk/lib/CodeGen/TailDuplicator.cpp =================================================================== --- llvm/trunk/lib/CodeGen/TailDuplicator.cpp +++ llvm/trunk/lib/CodeGen/TailDuplicator.cpp @@ -631,7 +631,7 @@ MachineBasicBlock *PredTBB = nullptr, *PredFBB = nullptr; SmallVector PredCond; - if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true)) + if (TII->analyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true)) return false; if (!PredCond.empty()) @@ -662,7 +662,7 @@ MachineBasicBlock *PredTBB = nullptr, *PredFBB = nullptr; SmallVector PredCond; - if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true)) + if (TII->analyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true)) continue; Changed = true; @@ -750,7 +750,7 @@ MachineBasicBlock *PredTBB, *PredFBB; SmallVector PredCond; - if (TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true)) + if (TII->analyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true)) continue; if (!PredCond.empty()) continue; @@ -788,7 +788,7 @@ appendCopies(PredBB, CopyInfos, Copies); // Simplify - TII->AnalyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true); + TII->analyzeBranch(*PredBB, PredTBB, PredFBB, PredCond, true); NumTailDupAdded += TailBB->size() - 1; // subtract one for removed branch @@ -814,7 +814,7 @@ // This has to check PrevBB->succ_size() because EH edges are ignored by // AnalyzeBranch. if (PrevBB->succ_size() == 1 && - !TII->AnalyzeBranch(*PrevBB, PriorTBB, PriorFBB, PriorCond, true) && + !TII->analyzeBranch(*PrevBB, PriorTBB, PriorFBB, PriorCond, true) && PriorCond.empty() && !PriorTBB && TailBB->pred_size() == 1 && !TailBB->hasAddressTaken()) { DEBUG(dbgs() << "\nMerging into block: " << *PrevBB Index: llvm/trunk/lib/Target/AArch64/AArch64A53Fix835769.cpp =================================================================== --- llvm/trunk/lib/Target/AArch64/AArch64A53Fix835769.cpp +++ llvm/trunk/lib/Target/AArch64/AArch64A53Fix835769.cpp @@ -137,8 +137,8 @@ MachineBasicBlock *PrevBB = &*std::prev(MBBI); for (MachineBasicBlock *S : MBB->predecessors()) - if (S == PrevBB && !TII->AnalyzeBranch(*PrevBB, TBB, FBB, Cond) && - !TBB && !FBB) + if (S == PrevBB && !TII->analyzeBranch(*PrevBB, TBB, FBB, Cond) && !TBB && + !FBB) return S; return nullptr; Index: llvm/trunk/lib/Target/AArch64/AArch64BranchRelaxation.cpp =================================================================== --- llvm/trunk/lib/Target/AArch64/AArch64BranchRelaxation.cpp +++ llvm/trunk/lib/Target/AArch64/AArch64BranchRelaxation.cpp @@ -415,7 +415,7 @@ // Analyze the branch so we know how to update the successor lists. MachineBasicBlock *TBB, *FBB; SmallVector Cond; - TII->AnalyzeBranch(*MBB, TBB, FBB, Cond, false); + TII->analyzeBranch(*MBB, TBB, FBB, Cond, false); MachineBasicBlock *NewBB = splitBlockBeforeInstr(MI); // No need for the branch to the next block. We're adding an unconditional Index: llvm/trunk/lib/Target/AArch64/AArch64ConditionOptimizer.cpp =================================================================== --- llvm/trunk/lib/Target/AArch64/AArch64ConditionOptimizer.cpp +++ llvm/trunk/lib/Target/AArch64/AArch64ConditionOptimizer.cpp @@ -337,7 +337,7 @@ SmallVector HeadCond; MachineBasicBlock *TBB = nullptr, *FBB = nullptr; - if (TII->AnalyzeBranch(*HBB, TBB, FBB, HeadCond)) { + if (TII->analyzeBranch(*HBB, TBB, FBB, HeadCond)) { continue; } @@ -348,7 +348,7 @@ SmallVector TrueCond; MachineBasicBlock *TBB_TBB = nullptr, *TBB_FBB = nullptr; - if (TII->AnalyzeBranch(*TBB, TBB_TBB, TBB_FBB, TrueCond)) { + if (TII->analyzeBranch(*TBB, TBB_TBB, TBB_FBB, TrueCond)) { continue; } Index: llvm/trunk/lib/Target/AArch64/AArch64ConditionalCompares.cpp =================================================================== --- llvm/trunk/lib/Target/AArch64/AArch64ConditionalCompares.cpp +++ llvm/trunk/lib/Target/AArch64/AArch64ConditionalCompares.cpp @@ -493,7 +493,7 @@ // The branch we're looking to eliminate must be analyzable. HeadCond.clear(); MachineBasicBlock *TBB = nullptr, *FBB = nullptr; - if (TII->AnalyzeBranch(*Head, TBB, FBB, HeadCond)) { + if (TII->analyzeBranch(*Head, TBB, FBB, HeadCond)) { DEBUG(dbgs() << "Head branch not analyzable.\n"); ++NumHeadBranchRejs; return false; @@ -521,7 +521,7 @@ CmpBBCond.clear(); TBB = FBB = nullptr; - if (TII->AnalyzeBranch(*CmpBB, TBB, FBB, CmpBBCond)) { + if (TII->analyzeBranch(*CmpBB, TBB, FBB, CmpBBCond)) { DEBUG(dbgs() << "CmpBB branch not analyzable.\n"); ++NumCmpBranchRejs; return false; Index: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h =================================================================== --- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h +++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.h @@ -141,7 +141,7 @@ MachineBasicBlock::iterator InsertPt, int FrameIndex, LiveIntervals *LIS = nullptr) const override; - bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, + bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify = false) const override; Index: llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp +++ llvm/trunk/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -93,11 +93,11 @@ } // Branch analysis. -bool AArch64InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, - MachineBasicBlock *&TBB, - MachineBasicBlock *&FBB, - SmallVectorImpl &Cond, - bool AllowModify) const { +bool AArch64InstrInfo::analyzeBranch(MachineBasicBlock &MBB, + MachineBasicBlock *&TBB, + MachineBasicBlock *&FBB, + SmallVectorImpl &Cond, + bool AllowModify) const { // If the block has no terminators, it just falls into the block after it. MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); if (I == MBB.end()) Index: llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.h =================================================================== --- llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.h +++ llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.h @@ -160,8 +160,7 @@ bool ReverseBranchCondition( SmallVectorImpl &Cond) const override; - bool AnalyzeBranch(MachineBasicBlock &MBB, - MachineBasicBlock *&TBB, + bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const override; Index: llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp +++ llvm/trunk/lib/Target/AMDGPU/R600InstrInfo.cpp @@ -683,12 +683,11 @@ Opcode == AMDGPU::BRANCH_COND_f32; } -bool -R600InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, - MachineBasicBlock *&TBB, - MachineBasicBlock *&FBB, - SmallVectorImpl &Cond, - bool AllowModify) const { +bool R600InstrInfo::analyzeBranch(MachineBasicBlock &MBB, + MachineBasicBlock *&TBB, + MachineBasicBlock *&FBB, + SmallVectorImpl &Cond, + bool AllowModify) const { // Most of the following comes from the ARM implementation of AnalyzeBranch // If the block has no terminators, it just falls into the block after it. Index: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h +++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.h @@ -149,7 +149,7 @@ bool findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1, unsigned &SrcOpIdx2) const override; - bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, + bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const override; Index: llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp +++ llvm/trunk/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -1104,8 +1104,7 @@ } } -bool SIInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, - MachineBasicBlock *&TBB, +bool SIInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const { Index: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h =================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.h @@ -120,7 +120,7 @@ const ScheduleDAG *DAG) const override; // Branch analysis. - bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, + bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify = false) const override; Index: llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ llvm/trunk/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -290,11 +290,11 @@ } // Branch analysis. -bool -ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, - MachineBasicBlock *&FBB, - SmallVectorImpl &Cond, - bool AllowModify) const { +bool ARMBaseInstrInfo::analyzeBranch(MachineBasicBlock &MBB, + MachineBasicBlock *&TBB, + MachineBasicBlock *&FBB, + SmallVectorImpl &Cond, + bool AllowModify) const { TBB = nullptr; FBB = nullptr; Index: llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp =================================================================== --- llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp +++ llvm/trunk/lib/Target/ARM/ARMConstantIslandPass.cpp @@ -675,7 +675,7 @@ // have an unconditional branch for whatever reason. MachineBasicBlock *TBB, *FBB; SmallVector Cond; - bool TooDifficult = TII->AnalyzeBranch(*MBB, TBB, FBB, Cond); + bool TooDifficult = TII->analyzeBranch(*MBB, TBB, FBB, Cond); return TooDifficult || FBB == nullptr; } @@ -2272,13 +2272,13 @@ MachineFunction::iterator OldPrior = std::prev(BBi); // If the block terminator isn't analyzable, don't try to move the block - bool B = TII->AnalyzeBranch(*BB, TBB, FBB, Cond); + bool B = TII->analyzeBranch(*BB, TBB, FBB, Cond); // If the block ends in an unconditional branch, move it. The prior block // has to have an analyzable terminator for us to move this one. Be paranoid // and make sure we're not trying to move the entry block of the function. if (!B && Cond.empty() && BB != &MF->front() && - !TII->AnalyzeBranch(*OldPrior, TBB, FBB, CondPrior)) { + !TII->analyzeBranch(*OldPrior, TBB, FBB, CondPrior)) { BB->moveAfter(JTBB); OldPrior->updateTerminator(); BB->updateTerminator(); Index: llvm/trunk/lib/Target/AVR/AVRInstrInfo.h =================================================================== --- llvm/trunk/lib/Target/AVR/AVRInstrInfo.h +++ llvm/trunk/lib/Target/AVR/AVRInstrInfo.h @@ -90,7 +90,7 @@ int &FrameIndex) const override; // Branch analysis. - bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, + bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify = false) const override; Index: llvm/trunk/lib/Target/AVR/AVRInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/AVR/AVRInstrInfo.cpp +++ llvm/trunk/lib/Target/AVR/AVRInstrInfo.cpp @@ -238,7 +238,7 @@ } } -bool AVRInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, +bool AVRInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, Index: llvm/trunk/lib/Target/BPF/BPFInstrInfo.h =================================================================== --- llvm/trunk/lib/Target/BPF/BPFInstrInfo.h +++ llvm/trunk/lib/Target/BPF/BPFInstrInfo.h @@ -44,7 +44,7 @@ MachineBasicBlock::iterator MBBI, unsigned DestReg, int FrameIndex, const TargetRegisterClass *RC, const TargetRegisterInfo *TRI) const override; - bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, + bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const override; Index: llvm/trunk/lib/Target/BPF/BPFInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/BPF/BPFInstrInfo.cpp +++ llvm/trunk/lib/Target/BPF/BPFInstrInfo.cpp @@ -75,7 +75,7 @@ llvm_unreachable("Can't load this register from stack slot"); } -bool BPFInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, +bool BPFInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, Index: llvm/trunk/lib/Target/Hexagon/HexagonBranchRelaxation.cpp =================================================================== --- llvm/trunk/lib/Target/Hexagon/HexagonBranchRelaxation.cpp +++ llvm/trunk/lib/Target/Hexagon/HexagonBranchRelaxation.cpp @@ -148,7 +148,7 @@ SmallVector Cond; // Try to analyze this branch. - if (HII->AnalyzeBranch(B, TBB, FBB, Cond, false)) { + if (HII->analyzeBranch(B, TBB, FBB, Cond, false)) { // Could not analyze it. See if this is something we can recognize. // If it is a NVJ, it should always have its target in // a fixed location. Index: llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp =================================================================== --- llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp +++ llvm/trunk/lib/Target/Hexagon/HexagonHardwareLoops.cpp @@ -436,7 +436,7 @@ SmallVector Cond; MachineBasicBlock *TB = nullptr, *FB = nullptr; - bool NotAnalyzed = TII->AnalyzeBranch(*ExitingBlock, TB, FB, Cond, false); + bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false); if (NotAnalyzed) return false; @@ -583,7 +583,7 @@ SmallVector Cond; MachineBasicBlock *TB = nullptr, *FB = nullptr; - bool NotAnalyzed = TII->AnalyzeBranch(*ExitingBlock, TB, FB, Cond, false); + bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false); if (NotAnalyzed) return nullptr; @@ -595,7 +595,7 @@ if (ExitingBlock != Latch && (TB == Latch || FB == Latch)) { MachineBasicBlock *LTB = 0, *LFB = 0; SmallVector LCond; - bool NotAnalyzed = TII->AnalyzeBranch(*Latch, LTB, LFB, LCond, false); + bool NotAnalyzed = TII->analyzeBranch(*Latch, LTB, LFB, LCond, false); if (NotAnalyzed) return nullptr; if (TB == Latch) @@ -1186,7 +1186,7 @@ MachineBasicBlock *TB = 0, *FB = 0; SmallVector Cond; - if (TII->AnalyzeBranch(*ExitingBlock, TB, FB, Cond, false)) + if (TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false)) return false; if (L->contains(TB)) @@ -1425,7 +1425,7 @@ MachineBasicBlock *TBB = 0, *FBB = 0; SmallVector Cond; - if (TII->AnalyzeBranch(*MI->getParent(), TBB, FBB, Cond, false)) + if (TII->analyzeBranch(*MI->getParent(), TBB, FBB, Cond, false)) continue; Comparison::Kind Cmp = getComparisonKind(MI->getOpcode(), 0, 0, 0); @@ -1621,14 +1621,14 @@ MachineBasicBlock *TB = nullptr, *FB = nullptr; SmallVector Cond; // AnalyzeBranch returns true if it fails to analyze branch. - bool NotAnalyzed = TII->AnalyzeBranch(*ExitingBlock, TB, FB, Cond, false); + bool NotAnalyzed = TII->analyzeBranch(*ExitingBlock, TB, FB, Cond, false); if (NotAnalyzed || Cond.empty()) return false; if (ExitingBlock != Latch && (TB == Latch || FB == Latch)) { MachineBasicBlock *LTB = 0, *LFB = 0; SmallVector LCond; - bool NotAnalyzed = TII->AnalyzeBranch(*Latch, LTB, LFB, LCond, false); + bool NotAnalyzed = TII->analyzeBranch(*Latch, LTB, LFB, LCond, false); if (NotAnalyzed) return false; @@ -1839,12 +1839,12 @@ SmallVector Tmp1; MachineBasicBlock *TB = nullptr, *FB = nullptr; - if (TII->AnalyzeBranch(*ExitingBlock, TB, FB, Tmp1, false)) + if (TII->analyzeBranch(*ExitingBlock, TB, FB, Tmp1, false)) return nullptr; for (MBBVector::iterator I = Preds.begin(), E = Preds.end(); I != E; ++I) { MachineBasicBlock *PB = *I; - bool NotAnalyzed = TII->AnalyzeBranch(*PB, TB, FB, Tmp1, false); + bool NotAnalyzed = TII->analyzeBranch(*PB, TB, FB, Tmp1, false); if (NotAnalyzed) return nullptr; } @@ -1930,7 +1930,7 @@ MachineBasicBlock *PB = *I; if (PB != Latch) { Tmp2.clear(); - bool NotAnalyzed = TII->AnalyzeBranch(*PB, TB, FB, Tmp2, false); + bool NotAnalyzed = TII->analyzeBranch(*PB, TB, FB, Tmp2, false); (void)NotAnalyzed; // suppress compiler warning assert (!NotAnalyzed && "Should be analyzable!"); if (TB != Header && (Tmp2.empty() || FB != Header)) @@ -1942,7 +1942,7 @@ // It can happen that the latch block will fall through into the header. // Insert an unconditional branch to the header. TB = FB = nullptr; - bool LatchNotAnalyzed = TII->AnalyzeBranch(*Latch, TB, FB, Tmp2, false); + bool LatchNotAnalyzed = TII->analyzeBranch(*Latch, TB, FB, Tmp2, false); (void)LatchNotAnalyzed; // suppress compiler warning assert (!LatchNotAnalyzed && "Should be analyzable!"); if (!TB && !FB) Index: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h =================================================================== --- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h +++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h @@ -79,10 +79,10 @@ /// If AllowModify is true, then this routine is allowed to modify the basic /// block (e.g. delete instructions after the unconditional branch). /// - bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, - MachineBasicBlock *&FBB, - SmallVectorImpl &Cond, - bool AllowModify) const override; + bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, + MachineBasicBlock *&FBB, + SmallVectorImpl &Cond, + bool AllowModify) const override; /// Remove the branching code at the end of the specific MBB. /// This is only invoked in cases where AnalyzeBranch returns success. It Index: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -370,7 +370,7 @@ /// Cond[1] = R /// Cond[2] = Imm /// -bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, +bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, @@ -587,7 +587,7 @@ SmallVector Cond; auto Term = MBB.getFirstTerminator(); if (Term != MBB.end() && isPredicated(*Term) && - !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond, false)) { + !analyzeBranch(MBB, NewTBB, NewFBB, Cond, false)) { MachineBasicBlock *NextBB = &*++MBB.getIterator(); if (NewTBB == NextBB) { ReverseBranchCondition(Cond); Index: llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp =================================================================== --- llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp +++ llvm/trunk/lib/Target/Hexagon/HexagonSplitDouble.cpp @@ -439,7 +439,7 @@ MachineBasicBlock *TB = 0, *FB = 0; MachineBasicBlock *TmpLB = const_cast(LB); SmallVector Cond; - bool BadLB = TII->AnalyzeBranch(*TmpLB, TB, FB, Cond, false); + bool BadLB = TII->analyzeBranch(*TmpLB, TB, FB, Cond, false); // Only analyzable conditional branches. HII::AnalyzeBranch will put // the branch opcode as the first element of Cond, and the predicate // operand as the second. Index: llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.h =================================================================== --- llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.h +++ llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.h @@ -81,7 +81,7 @@ ArrayRef> getSerializableDirectMachineOperandTargetFlags() const override; - bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TrueBlock, + bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TrueBlock, MachineBasicBlock *&FalseBlock, SmallVectorImpl &Condition, bool AllowModify) const override; Index: llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.cpp +++ llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.cpp @@ -562,7 +562,7 @@ // - condition is populated with machine operands needed to generate the branch // to insert in InsertBranch; // Returns: false if branch could successfully be analyzed. -bool LanaiInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, +bool LanaiInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TrueBlock, MachineBasicBlock *&FalseBlock, SmallVectorImpl &Condition, Index: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h =================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h +++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.h @@ -74,8 +74,8 @@ bool ReverseBranchCondition(SmallVectorImpl &Cond) const override; bool isUnpredicatedTerminator(const MachineInstr &MI) const override; - bool AnalyzeBranch(MachineBasicBlock &MBB, - MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, + bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, + MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const override; Index: llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp +++ llvm/trunk/lib/Target/MSP430/MSP430InstrInfo.cpp @@ -170,7 +170,7 @@ return !isPredicated(MI); } -bool MSP430InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, +bool MSP430InstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, Index: llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp +++ llvm/trunk/lib/Target/Mips/MipsDelaySlotFiller.cpp @@ -815,7 +815,7 @@ SmallVector Cond; MipsInstrInfo::BranchType R = - TII->AnalyzeBranch(MBB, TrueBB, FalseBB, Cond, false, BranchInstrs); + TII->analyzeBranch(MBB, TrueBB, FalseBB, Cond, false, BranchInstrs); if ((R == MipsInstrInfo::BT_None) || (R == MipsInstrInfo::BT_NoBranch)) return std::make_pair(R, nullptr); Index: llvm/trunk/lib/Target/Mips/MipsInstrInfo.h =================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.h +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.h @@ -50,7 +50,7 @@ static const MipsInstrInfo *create(MipsSubtarget &STI); /// Branch Analysis - bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, + bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const override; @@ -64,11 +64,11 @@ bool ReverseBranchCondition(SmallVectorImpl &Cond) const override; - BranchType AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, + BranchType analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify, - SmallVectorImpl &BranchInstrs) const; + SmallVectorImpl &BranchInstrs) const; /// Determine the opcode of a non-delay slot form for a branch if one exists. unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const; Index: llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp +++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.cpp @@ -83,13 +83,13 @@ Cond.push_back(Inst->getOperand(i)); } -bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, +bool MipsInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const { SmallVector BranchInstrs; - BranchType BT = AnalyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); + BranchType BT = analyzeBranch(MBB, TBB, FBB, Cond, AllowModify, BranchInstrs); return (BT == BT_None) || (BT == BT_Indirect); } @@ -176,7 +176,7 @@ return false; } -MipsInstrInfo::BranchType MipsInstrInfo::AnalyzeBranch( +MipsInstrInfo::BranchType MipsInstrInfo::analyzeBranch( MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify, SmallVectorImpl &BranchInstrs) const { Index: llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.h =================================================================== --- llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.h +++ llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.h @@ -59,9 +59,10 @@ virtual bool CanTailMerge(const MachineInstr *MI) const; // Branch analysis. - bool AnalyzeBranch( - MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond, bool AllowModify) const override; + bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, + MachineBasicBlock *&FBB, + SmallVectorImpl &Cond, + bool AllowModify) const override; unsigned RemoveBranch(MachineBasicBlock &MBB) const override; unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, ArrayRef Cond, Index: llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.cpp +++ llvm/trunk/lib/Target/NVPTX/NVPTXInstrInfo.cpp @@ -146,9 +146,11 @@ /// Note that RemoveBranch and InsertBranch must be implemented to support /// cases where this method returns success. /// -bool NVPTXInstrInfo::AnalyzeBranch( - MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, - SmallVectorImpl &Cond, bool AllowModify) const { +bool NVPTXInstrInfo::analyzeBranch(MachineBasicBlock &MBB, + MachineBasicBlock *&TBB, + MachineBasicBlock *&FBB, + SmallVectorImpl &Cond, + bool AllowModify) const { // If the block has no terminators, it just falls into the block after it. MachineBasicBlock::iterator I = MBB.end(); if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) Index: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h =================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.h @@ -164,7 +164,7 @@ // Branch analysis. - bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, + bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const override; Index: llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp +++ llvm/trunk/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -444,7 +444,8 @@ // Branch analysis. // Note: If the condition register is set to CTR or CTR8 then this is a // BDNZ (imm == 1) or BDZ (imm == 0) branch. -bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB, +bool PPCInstrInfo::analyzeBranch(MachineBasicBlock &MBB, + MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const { Index: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h =================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.h @@ -65,10 +65,10 @@ unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override; - bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, + bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, - bool AllowModify = false) const override ; + bool AllowModify = false) const override; unsigned RemoveBranch(MachineBasicBlock &MBB) const override; Index: llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp +++ llvm/trunk/lib/Target/Sparc/SparcInstrInfo.cpp @@ -157,7 +157,7 @@ Target = LastInst->getOperand(0).getMBB(); } -bool SparcInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, +bool SparcInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, Index: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h =================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h +++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.h @@ -160,7 +160,7 @@ int &FrameIndex) const override; bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, int &SrcFrameIndex) const override; - bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, + bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const override; Index: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -271,7 +271,7 @@ return true; } -bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, +bool SystemZInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, Index: llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.h =================================================================== --- llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.h +++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.h @@ -44,7 +44,7 @@ unsigned OpIdx1, unsigned OpIdx2) const override; - bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, + bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify = false) const override; Index: llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp +++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp @@ -92,7 +92,7 @@ } // Branch analysis. -bool WebAssemblyInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, +bool WebAssemblyInstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, Index: llvm/trunk/lib/Target/X86/X86InstrInfo.h =================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.h +++ llvm/trunk/lib/Target/X86/X86InstrInfo.h @@ -304,7 +304,7 @@ // Branch analysis. bool isUnpredicatedTerminator(const MachineInstr &MI) const override; - bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, + bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const override; @@ -312,7 +312,7 @@ bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, int64_t &Offset, const TargetRegisterInfo *TRI) const override; - bool AnalyzeBranchPredicate(MachineBasicBlock &MBB, + bool analyzeBranchPredicate(MachineBasicBlock &MBB, TargetInstrInfo::MachineBranchPredicate &MBP, bool AllowModify = false) const override; Index: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp @@ -4117,7 +4117,7 @@ return false; } -bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, +bool X86InstrInfo::analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, @@ -4126,7 +4126,7 @@ return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify); } -bool X86InstrInfo::AnalyzeBranchPredicate(MachineBasicBlock &MBB, +bool X86InstrInfo::analyzeBranchPredicate(MachineBasicBlock &MBB, MachineBranchPredicate &MBP, bool AllowModify) const { using namespace std::placeholders; Index: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h =================================================================== --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.h @@ -50,7 +50,7 @@ unsigned isStoreToStackSlot(const MachineInstr &MI, int &FrameIndex) const override; - bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, + bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, SmallVectorImpl &Cond, bool AllowModify) const override; Index: llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp =================================================================== --- llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp +++ llvm/trunk/lib/Target/XCore/XCoreInstrInfo.cpp @@ -187,11 +187,11 @@ /// Note that RemoveBranch and InsertBranch must be implemented to support /// cases where this method returns success. /// -bool -XCoreInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, - MachineBasicBlock *&FBB, - SmallVectorImpl &Cond, - bool AllowModify) const { +bool XCoreInstrInfo::analyzeBranch(MachineBasicBlock &MBB, + MachineBasicBlock *&TBB, + MachineBasicBlock *&FBB, + SmallVectorImpl &Cond, + bool AllowModify) const { // If the block has no terminators, it just falls into the block after it. MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); if (I == MBB.end())