Index: llvm/trunk/lib/CodeGen/MIRParser/MILexer.h
===================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MILexer.h
+++ llvm/trunk/lib/CodeGen/MIRParser/MILexer.h
@@ -38,6 +38,7 @@
     underscore,
     colon,
     coloncolon,
+    dot,
     exclaim,
     lparen,
     rparen,
Index: llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp
+++ llvm/trunk/lib/CodeGen/MIRParser/MILexer.cpp
@@ -237,7 +237,7 @@
 }
 
 static Cursor maybeLexIdentifier(Cursor C, MIToken &Token) {
-  if (!isalpha(C.peek()) && C.peek() != '_' && C.peek() != '.')
+  if (!isalpha(C.peek()) && C.peek() != '_')
     return None;
   auto Range = C;
   while (isIdentifierChar(C.peek()))
@@ -372,6 +372,11 @@
   return C;
 }
 
+/// Returns true for a character allowed in a register name.
+static bool isRegisterChar(char C) {
+  return isIdentifierChar(C) && C != '.';
+}
+
 static Cursor maybeLexRegister(Cursor C, MIToken &Token) {
   if (C.peek() != '%')
     return None;
@@ -379,7 +384,7 @@
     return lexVirtualRegister(C, Token);
   auto Range = C;
   C.advance(); // Skip '%'
-  while (isIdentifierChar(C.peek()))
+  while (isRegisterChar(C.peek()))
     C.advance();
   Token.reset(MIToken::NamedRegister, Range.upto(C))
       .setStringValue(Range.upto(C).drop_front(1)); // Drop the '%'
@@ -491,6 +496,8 @@
   switch (C) {
   case ',':
     return MIToken::comma;
+  case '.':
+    return MIToken::dot;
   case '=':
     return MIToken::equal;
   case ':':
Index: llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
+++ llvm/trunk/lib/CodeGen/MIRParser/MIParser.cpp
@@ -882,10 +882,10 @@
 }
 
 bool MIParser::parseSubRegisterIndex(unsigned &SubReg) {
-  assert(Token.is(MIToken::colon));
+  assert(Token.is(MIToken::dot));
   lex();
   if (Token.isNot(MIToken::Identifier))
-    return error("expected a subregister index after ':'");
+    return error("expected a subregister index after '.'");
   auto Name = Token.stringValue();
   SubReg = getSubRegIndex(Name);
   if (!SubReg)
@@ -970,7 +970,7 @@
     return true;
   lex();
   unsigned SubReg = 0;
-  if (Token.is(MIToken::colon)) {
+  if (Token.is(MIToken::dot)) {
     if (parseSubRegisterIndex(SubReg))
       return true;
     if (!TargetRegisterInfo::isVirtualRegister(Reg))
Index: llvm/trunk/lib/CodeGen/MIRPrinter.cpp
===================================================================
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp
@@ -779,7 +779,7 @@
     printReg(Op.getReg(), OS, TRI);
     // Print the sub register.
     if (Op.getSubReg() != 0)
-      OS << ':' << TRI->getSubRegIndexName(Op.getSubReg());
+      OS << '.' << TRI->getSubRegIndexName(Op.getSubReg());
     if (ShouldPrintRegisterTies && Op.isTied() && !Op.isDef())
       OS << "(tied-def " << Op.getParent()->findTiedOperandIdx(I) << ")";
     assert((!IsDef || MRI) && "for IsDef, MRI must be provided");
Index: llvm/trunk/test/CodeGen/AMDGPU/detect-dead-lanes.mir
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/detect-dead-lanes.mir
+++ llvm/trunk/test/CodeGen/AMDGPU/detect-dead-lanes.mir
@@ -17,14 +17,14 @@
 # CHECK: S_NOP 0, implicit-def %1
 # CHECK: S_NOP 0, implicit-def dead %2
 # CHECK: %3 = REG_SEQUENCE %0, {{[0-9]+}}, %1, {{[0-9]+}}, undef %2, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit %3:sub0
-# CHECK: S_NOP 0, implicit %3:sub1
-# CHECK: S_NOP 0, implicit undef %3:sub2
-# CHECK: %4 = COPY %3:sub0_sub1
-# CHECK: %5 = COPY undef %3:sub2_sub3
-# CHECK: S_NOP 0, implicit %4:sub0
-# CHECK: S_NOP 0, implicit %4:sub1
-# CHECK: S_NOP 0, implicit undef %5:sub0
+# CHECK: S_NOP 0, implicit %3.sub0
+# CHECK: S_NOP 0, implicit %3.sub1
+# CHECK: S_NOP 0, implicit undef %3.sub2
+# CHECK: %4 = COPY %3.sub0_sub1
+# CHECK: %5 = COPY undef %3.sub2_sub3
+# CHECK: S_NOP 0, implicit %4.sub0
+# CHECK: S_NOP 0, implicit %4.sub1
+# CHECK: S_NOP 0, implicit undef %5.sub0
 name: test0
 isSSA: true
 registers:
@@ -40,14 +40,14 @@
     S_NOP 0, implicit-def %1
     S_NOP 0, implicit-def %2
     %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub3
-    S_NOP 0, implicit %3:sub0
-    S_NOP 0, implicit %3:sub1
-    S_NOP 0, implicit %3:sub2
-    %4 = COPY %3:sub0_sub1
-    %5 = COPY %3:sub2_sub3
-    S_NOP 0, implicit %4:sub0
-    S_NOP 0, implicit %4:sub1
-    S_NOP 0, implicit %5:sub0
+    S_NOP 0, implicit %3.sub0
+    S_NOP 0, implicit %3.sub1
+    S_NOP 0, implicit %3.sub2
+    %4 = COPY %3.sub0_sub1
+    %5 = COPY %3.sub2_sub3
+    S_NOP 0, implicit %4.sub0
+    S_NOP 0, implicit %4.sub1
+    S_NOP 0, implicit %5.sub0
 ...
 ---
 # Check defined lanes transfer; Includes checking for some special cases like
@@ -55,20 +55,20 @@
 # CHECK-LABEL: name: test1
 # CHECK: %0 = REG_SEQUENCE %sgpr0, {{[0-9]+}}, %sgpr0, {{[0-9]+}}
 # CHECK: %1 = INSERT_SUBREG %0, %sgpr1, {{[0-9]+}}
-# CHECK: %2 = INSERT_SUBREG %0:sub2_sub3, %sgpr42, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit %1:sub0
-# CHECK: S_NOP 0, implicit undef %1:sub1
-# CHECK: S_NOP 0, implicit %1:sub2
-# CHECK: S_NOP 0, implicit %1:sub3
-# CHECK: S_NOP 0, implicit %2:sub0
-# CHECK: S_NOP 0, implicit undef %2:sub1
+# CHECK: %2 = INSERT_SUBREG %0.sub2_sub3, %sgpr42, {{[0-9]+}}
+# CHECK: S_NOP 0, implicit %1.sub0
+# CHECK: S_NOP 0, implicit undef %1.sub1
+# CHECK: S_NOP 0, implicit %1.sub2
+# CHECK: S_NOP 0, implicit %1.sub3
+# CHECK: S_NOP 0, implicit %2.sub0
+# CHECK: S_NOP 0, implicit undef %2.sub1
 
 # CHECK: %3 = IMPLICIT_DEF
 # CHECK: %4 = INSERT_SUBREG %0, undef %3, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit undef %4:sub0
-# CHECK: S_NOP 0, implicit undef %4:sub1
-# CHECK: S_NOP 0, implicit %4:sub2
-# CHECK: S_NOP 0, implicit undef %4:sub3
+# CHECK: S_NOP 0, implicit undef %4.sub0
+# CHECK: S_NOP 0, implicit undef %4.sub1
+# CHECK: S_NOP 0, implicit %4.sub2
+# CHECK: S_NOP 0, implicit undef %4.sub3
 
 # CHECK: %5 = EXTRACT_SUBREG %0, {{[0-9]+}}
 # CHECK: %6 = EXTRACT_SUBREG %5, {{[0-9]+}}
@@ -101,20 +101,20 @@
   bb.0:
     %0 = REG_SEQUENCE %sgpr0, %subreg.sub0, %sgpr0, %subreg.sub2
     %1 = INSERT_SUBREG %0, %sgpr1, %subreg.sub3
-    %2 = INSERT_SUBREG %0:sub2_sub3, %sgpr42, %subreg.sub0
-    S_NOP 0, implicit %1:sub0
-    S_NOP 0, implicit %1:sub1
-    S_NOP 0, implicit %1:sub2
-    S_NOP 0, implicit %1:sub3
-    S_NOP 0, implicit %2:sub0
-    S_NOP 0, implicit %2:sub1
+    %2 = INSERT_SUBREG %0.sub2_sub3, %sgpr42, %subreg.sub0
+    S_NOP 0, implicit %1.sub0
+    S_NOP 0, implicit %1.sub1
+    S_NOP 0, implicit %1.sub2
+    S_NOP 0, implicit %1.sub3
+    S_NOP 0, implicit %2.sub0
+    S_NOP 0, implicit %2.sub1
 
     %3 = IMPLICIT_DEF
     %4 = INSERT_SUBREG %0, %3, %subreg.sub0
-    S_NOP 0, implicit %4:sub0
-    S_NOP 0, implicit %4:sub1
-    S_NOP 0, implicit %4:sub2
-    S_NOP 0, implicit %4:sub3
+    S_NOP 0, implicit %4.sub0
+    S_NOP 0, implicit %4.sub1
+    S_NOP 0, implicit %4.sub2
+    S_NOP 0, implicit %4.sub3
 
     %5 = EXTRACT_SUBREG %0, %subreg.sub0_sub1
     %6 = EXTRACT_SUBREG %5, %subreg.sub0
@@ -138,8 +138,8 @@
 # CHECK: S_NOP 0, implicit-def %1
 # CHECK: S_NOP 0, implicit-def %2
 # CHECK: %3 = REG_SEQUENCE undef %0, {{[0-9]+}}, %1, {{[0-9]+}}, %2, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit %3:sub1
-# CHECK: S_NOP 0, implicit %3:sub3
+# CHECK: S_NOP 0, implicit %3.sub1
+# CHECK: S_NOP 0, implicit %3.sub3
 
 # CHECK: S_NOP 0, implicit-def %4
 # CHECK: S_NOP 0, implicit-def dead %5
@@ -149,18 +149,18 @@
 # CHECK: S_NOP 0, implicit-def dead %7
 # CHECK: S_NOP 0, implicit-def %8
 # CHECK: %9 = INSERT_SUBREG undef %7, %8, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit %9:sub2
+# CHECK: S_NOP 0, implicit %9.sub2
 
 # CHECK: S_NOP 0, implicit-def %10
 # CHECK: S_NOP 0, implicit-def dead %11
 # CHECK: %12 = INSERT_SUBREG %10, undef %11, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit %12:sub3
+# CHECK: S_NOP 0, implicit %12.sub3
 
 # CHECK: S_NOP 0, implicit-def %13
 # CHECK: S_NOP 0, implicit-def dead %14
 # CHECK: %15 = REG_SEQUENCE %13, {{[0-9]+}}, undef %14, {{[0-9]+}}
 # CHECK: %16 = EXTRACT_SUBREG %15, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit %16:sub1
+# CHECK: S_NOP 0, implicit %16.sub1
 
 name: test2
 isSSA: true
@@ -188,8 +188,8 @@
     S_NOP 0, implicit-def %1
     S_NOP 0, implicit-def %2
     %3 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1, %2, %subreg.sub2_sub3
-    S_NOP 0, implicit %3:sub1
-    S_NOP 0, implicit %3:sub3
+    S_NOP 0, implicit %3.sub1
+    S_NOP 0, implicit %3.sub3
 
     S_NOP 0, implicit-def %4
     S_NOP 0, implicit-def %5
@@ -199,18 +199,18 @@
     S_NOP 0, implicit-def %7
     S_NOP 0, implicit-def %8
     %9 = INSERT_SUBREG %7, %8, %subreg.sub2_sub3
-    S_NOP 0, implicit %9:sub2
+    S_NOP 0, implicit %9.sub2
 
     S_NOP 0, implicit-def %10
     S_NOP 0, implicit-def %11
     %12 = INSERT_SUBREG %10, %11, %subreg.sub0_sub1
-    S_NOP 0, implicit %12:sub3
+    S_NOP 0, implicit %12.sub3
 
     S_NOP 0, implicit-def %13
     S_NOP 0, implicit-def %14
     %15 = REG_SEQUENCE %13, %subreg.sub0_sub1, %14, %subreg.sub2_sub3
     %16 = EXTRACT_SUBREG %15, %subreg.sub0_sub1
-    S_NOP 0, implicit %16:sub1
+    S_NOP 0, implicit %16.sub1
 ...
 ---
 # Check that copies to physregs use all lanes, copies from physregs define all
@@ -261,7 +261,7 @@
 # CHECK-LABEL: name: test5
 # CHECK: S_NOP 0, implicit-def %0
 # CHECK: %1 = REG_SEQUENCE undef %0, {{[0-9]+}}, %0, {{[0-9]+}}
-# CHECK: S_NOP 0, implicit %1:sub1
+# CHECK: S_NOP 0, implicit %1.sub1
 name: test5
 isSSA: true
 tracksRegLiveness: true
@@ -272,7 +272,7 @@
   bb.0:
     S_NOP 0, implicit-def %0
     %1 = REG_SEQUENCE %0, %subreg.sub0, %0, %subreg.sub1
-    S_NOP 0, implicit %1:sub1
+    S_NOP 0, implicit %1.sub1
 ...
 ---
 # Check "optimistic" dataflow fixpoint in phi-loops.
@@ -287,8 +287,8 @@
 # CHECK: %4 = PHI %3, %bb.0, %5, %bb.1
 
 # CHECK: bb.2:
-# CHECK:   S_NOP 0, implicit %4:sub0
-# CHECK:   S_NOP 0, implicit undef %4:sub3
+# CHECK:   S_NOP 0, implicit %4.sub0
+# CHECK:   S_NOP 0, implicit undef %4.sub3
 name: loop0
 isSSA: true
 tracksRegLiveness: true
@@ -313,14 +313,14 @@
     %4 = PHI %3, %bb.0, %5, %bb.1
 
     ; let's swiffle some lanes around for fun...
-    %5 = REG_SEQUENCE %4:sub0, %subreg.sub0, %4:sub2, %subreg.sub1, %4:sub1, %subreg.sub2, %4:sub3, %subreg.sub3
+    %5 = REG_SEQUENCE %4.sub0, %subreg.sub0, %4.sub2, %subreg.sub1, %4.sub1, %subreg.sub2, %4.sub3, %subreg.sub3
 
     S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
     S_BRANCH %bb.2
 
   bb.2:
-    S_NOP 0, implicit %4:sub0
-    S_NOP 0, implicit %4:sub3
+    S_NOP 0, implicit %4.sub0
+    S_NOP 0, implicit %4.sub3
 ...
 ---
 # Check a loop that needs to be traversed multiple times to reach the fixpoint
@@ -339,10 +339,10 @@
 # CHECK: bb.1:
 # CHECK: %5 = PHI %4, %bb.0, %6, %bb.1
 
-# CHECK: %6 = REG_SEQUENCE %5:sub1, {{[0-9]+}}, %5:sub3, {{[0-9]+}}, undef %5:sub2, {{[0-9]+}}, %5:sub0, {{[0-9]+}}
+# CHECK: %6 = REG_SEQUENCE %5.sub1, {{[0-9]+}}, %5.sub3, {{[0-9]+}}, undef %5.sub2, {{[0-9]+}}, %5.sub0, {{[0-9]+}}
 
 # CHECK: bb.2:
-# CHECK:   S_NOP 0, implicit %6:sub3
+# CHECK:   S_NOP 0, implicit %6.sub3
 name: loop1
 isSSA: true
 tracksRegLiveness: true
@@ -369,13 +369,13 @@
     %5 = PHI %4, %bb.0, %6, %bb.1
 
     ; rotate lanes, but skip sub2 lane...
-    %6 = REG_SEQUENCE %5:sub1, %subreg.sub0, %5:sub3, %subreg.sub1, %5:sub2, %subreg.sub2, %5:sub0, %subreg.sub3
+    %6 = REG_SEQUENCE %5.sub1, %subreg.sub0, %5.sub3, %subreg.sub1, %5.sub2, %subreg.sub2, %5.sub0, %subreg.sub3
 
     S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
     S_BRANCH %bb.2
 
   bb.2:
-    S_NOP 0, implicit %6:sub3
+    S_NOP 0, implicit %6.sub3
 ...
 ---
 # Similar to loop1 test, but check for fixpoint of defined lanes.
@@ -388,13 +388,13 @@
 # CHECK: bb.1:
 # CHECK: %2 = PHI %1, %bb.0, %3, %bb.1
 
-# CHECK: %3 = REG_SEQUENCE %2:sub3, {{[0-9]+}}, undef %2:sub1, {{[0-9]+}}, %2:sub0, {{[0-9]+}}, %2:sub2, {{[0-9]+}}
+# CHECK: %3 = REG_SEQUENCE %2.sub3, {{[0-9]+}}, undef %2.sub1, {{[0-9]+}}, %2.sub0, {{[0-9]+}}, %2.sub2, {{[0-9]+}}
 
 # CHECK: bb.2:
-# CHECK:   S_NOP 0, implicit %2:sub0
-# CHECK:   S_NOP 0, implicit undef %2:sub1
-# CHECK:   S_NOP 0, implicit %2:sub2
-# CHECK:   S_NOP 0, implicit %2:sub3
+# CHECK:   S_NOP 0, implicit %2.sub0
+# CHECK:   S_NOP 0, implicit undef %2.sub1
+# CHECK:   S_NOP 0, implicit %2.sub2
+# CHECK:   S_NOP 0, implicit %2.sub3
 name: loop2
 isSSA: true
 tracksRegLiveness: true
@@ -415,14 +415,14 @@
     %2 = PHI %1, %bb.0, %3, %bb.1
 
     ; rotate subreg lanes, skipping sub1
-    %3 = REG_SEQUENCE %2:sub3, %subreg.sub0, %2:sub1, %subreg.sub1, %2:sub0, %subreg.sub2, %2:sub2, %subreg.sub3
+    %3 = REG_SEQUENCE %2.sub3, %subreg.sub0, %2.sub1, %subreg.sub1, %2.sub0, %subreg.sub2, %2.sub2, %subreg.sub3
 
     S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
     S_BRANCH %bb.2
 
   bb.2:
-    S_NOP 0, implicit %2:sub0
-    S_NOP 0, implicit undef %2:sub1
-    S_NOP 0, implicit %2:sub2
-    S_NOP 0, implicit %2:sub3
+    S_NOP 0, implicit %2.sub0
+    S_NOP 0, implicit undef %2.sub1
+    S_NOP 0, implicit %2.sub2
+    S_NOP 0, implicit %2.sub3
 ...
Index: llvm/trunk/test/CodeGen/AMDGPU/liveness.mir
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/liveness.mir
+++ llvm/trunk/test/CodeGen/AMDGPU/liveness.mir
@@ -17,16 +17,16 @@
 body: |
   bb.0:
     successors: %bb.1, %bb.2
-    S_NOP 0, implicit-def undef %0:sub0
+    S_NOP 0, implicit-def undef %0.sub0
     S_CBRANCH_VCCNZ %bb.1, implicit undef %vcc
     S_BRANCH %bb.2
 
   bb.1:
     successors: %bb.2
-    S_NOP 0, implicit-def %0:sub1
-    S_NOP 0, implicit %0:sub1
+    S_NOP 0, implicit-def %0.sub1
+    S_NOP 0, implicit %0.sub1
     S_BRANCH %bb.2
 
   bb.2:
-    S_NOP 0, implicit %0:sub0
+    S_NOP 0, implicit %0.sub0
 ...
Index: llvm/trunk/test/CodeGen/AMDGPU/rename-independent-subregs.mir
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/rename-independent-subregs.mir
+++ llvm/trunk/test/CodeGen/AMDGPU/rename-independent-subregs.mir
@@ -7,12 +7,12 @@
 # can be moved to a new virtual register. The third def of sub1 however is used
 # in combination with sub0 and needs to stay with the original vreg.
 # CHECK-LABEL: name: test0
-# CHECK: S_NOP 0, implicit-def undef %0:sub0
-# CHECK: S_NOP 0, implicit-def undef %2:sub1
-# CHECK: S_NOP 0, implicit %2:sub1
-# CHECK: S_NOP 0, implicit-def undef %1:sub1
-# CHECK: S_NOP 0, implicit %1:sub1
-# CHECK: S_NOP 0, implicit-def %0:sub1
+# CHECK: S_NOP 0, implicit-def undef %0.sub0
+# CHECK: S_NOP 0, implicit-def undef %2.sub1
+# CHECK: S_NOP 0, implicit %2.sub1
+# CHECK: S_NOP 0, implicit-def undef %1.sub1
+# CHECK: S_NOP 0, implicit %1.sub1
+# CHECK: S_NOP 0, implicit-def %0.sub1
 # CHECK: S_NOP 0, implicit %0
 name: test0
 isSSA: true
@@ -20,11 +20,11 @@
   - { id: 0, class: sreg_128 }
 body: |
   bb.0:
-    S_NOP 0, implicit-def undef %0:sub0
-    S_NOP 0, implicit-def %0:sub1
-    S_NOP 0, implicit %0:sub1
-    S_NOP 0, implicit-def %0:sub1
-    S_NOP 0, implicit %0:sub1
-    S_NOP 0, implicit-def %0:sub1
+    S_NOP 0, implicit-def undef %0.sub0
+    S_NOP 0, implicit-def %0.sub1
+    S_NOP 0, implicit %0.sub1
+    S_NOP 0, implicit-def %0.sub1
+    S_NOP 0, implicit %0.sub1
+    S_NOP 0, implicit-def %0.sub1
     S_NOP 0, implicit %0
 ...
Index: llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
===================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
+++ llvm/trunk/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
@@ -19,8 +19,8 @@
 body: |
   bb.0.entry:
     %0 = COPY %edi
-    ; CHECK: [[@LINE+1]]:20: expected a subregister index after ':'
-    %1 = COPY %0 : 42
+    ; CHECK: [[@LINE+1]]:20: expected a subregister index after '.'
+    %1 = COPY %0 . 42
     %2 = AND8ri %1, 1, implicit-def %eflags
     %al = COPY %2
     RETQ %al
Index: llvm/trunk/test/CodeGen/MIR/X86/subreg-on-physreg.mir
===================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/subreg-on-physreg.mir
+++ llvm/trunk/test/CodeGen/MIR/X86/subreg-on-physreg.mir
@@ -8,5 +8,5 @@
 body: |
   bb.0:
     ; CHECK: [[@LINE+1]]:19: subregister index expects a virtual register
-    %eax:sub_8bit = COPY %bl
+    %eax.sub_8bit = COPY %bl
 ...
Index: llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir
===================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir
+++ llvm/trunk/test/CodeGen/MIR/X86/subregister-operands.mir
@@ -22,9 +22,9 @@
   bb.0.entry:
     liveins: %edi
     ; CHECK:      %0 = COPY %edi
-    ; CHECK-NEXT: %1 = COPY %0:sub_8bit
+    ; CHECK-NEXT: %1 = COPY %0.sub_8bit
     %0 = COPY %edi
-    %1 = COPY %0:sub_8bit
+    %1 = COPY %0.sub_8bit
     %2 = AND8ri %1, 1, implicit-def %eflags
     %al = COPY %2
     RETQ %al
Index: llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir
===================================================================
--- llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir
+++ llvm/trunk/test/CodeGen/MIR/X86/unknown-subregister-index.mir
@@ -22,7 +22,7 @@
   bb.0.entry:
     %0 = COPY %edi
     ; CHECK: [[@LINE+1]]:18: use of unknown subregister index 'bit8'
-    %1 = COPY %0:bit8
+    %1 = COPY %0.bit8
     %2 = AND8ri %1, 1, implicit-def %eflags
     %al = COPY %2
     RETQ %al
Index: llvm/trunk/unittests/MI/LiveIntervalTest.cpp
===================================================================
--- llvm/trunk/unittests/MI/LiveIntervalTest.cpp
+++ llvm/trunk/unittests/MI/LiveIntervalTest.cpp
@@ -367,11 +367,11 @@
 "    S_BRANCH %bb.1\n"
 "  bb.2:\n"
 "    successors: %bb.1\n"
-"    S_NOP 0, implicit %0:sub0\n"
-"    S_NOP 0, implicit %0:sub1\n"
+"    S_NOP 0, implicit %0.sub0\n"
+"    S_NOP 0, implicit %0.sub1\n"
 "    S_NOP 0\n"
-"    undef %0:sub0 = IMPLICIT_DEF\n"
-"    %0:sub1 = IMPLICIT_DEF\n"
+"    undef %0.sub0 = IMPLICIT_DEF\n"
+"    %0.sub1 = IMPLICIT_DEF\n"
 "  bb.1:\n"
 "    S_NOP 0, implicit %0\n",
   [](MachineFunction &MF, LiveIntervals &LIS) {